| York Sun | 149eb33 | 2016-09-26 08:09:27 -0700 | [diff] [blame] | 1 | config ARCH_LS1021A |
| York Sun | fcd0e74 | 2016-10-04 14:31:47 -0700 | [diff] [blame] | 2 | bool |
| York Sun | 1dc61ca | 2016-12-28 08:43:41 -0800 | [diff] [blame^] | 3 | select SYS_FSL_ERRATUM_A008378 |
| 4 | select SYS_FSL_ERRATUM_A008407 |
| 5 | select SYS_FSL_ERRATUM_A009663 |
| 6 | select SYS_FSL_ERRATUM_A009942 |
| York Sun | 149eb33 | 2016-09-26 08:09:27 -0700 | [diff] [blame] | 7 | select SYS_FSL_ERRATUM_A010315 |
| York Sun | 6b62ef0 | 2016-10-04 18:01:34 -0700 | [diff] [blame] | 8 | select SYS_FSL_SRDS_1 |
| 9 | select SYS_HAS_SERDES |
| York Sun | d297d39 | 2016-12-28 08:43:40 -0800 | [diff] [blame] | 10 | select SYS_FSL_DDR_BE if SYS_FSL_DDR |
| 11 | select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR |
| 12 | select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR |
| 13 | select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR |
| York Sun | 92c36e2 | 2016-12-28 08:43:30 -0800 | [diff] [blame] | 14 | select SYS_FSL_HAS_SEC |
| 15 | select SYS_FSL_SEC_COMPAT_5 |
| York Sun | fa419942 | 2016-12-28 08:43:31 -0800 | [diff] [blame] | 16 | select SYS_FSL_SEC_LE |
| York Sun | 4de7e93 | 2016-09-26 08:09:29 -0700 | [diff] [blame] | 17 | |
| York Sun | 4dd8c61 | 2016-10-04 14:31:48 -0700 | [diff] [blame] | 18 | menu "LS102xA architecture" |
| 19 | depends on ARCH_LS1021A |
| 20 | |
| York Sun | 4de7e93 | 2016-09-26 08:09:29 -0700 | [diff] [blame] | 21 | config LS1_DEEP_SLEEP |
| York Sun | fcd0e74 | 2016-10-04 14:31:47 -0700 | [diff] [blame] | 22 | bool "Deep sleep" |
| 23 | depends on ARCH_LS1021A |
| York Sun | 4dd8c61 | 2016-10-04 14:31:48 -0700 | [diff] [blame] | 24 | |
| York Sun | f188d22 | 2016-10-04 14:45:01 -0700 | [diff] [blame] | 25 | config MAX_CPUS |
| 26 | int "Maximum number of CPUs permitted for LS102xA" |
| 27 | depends on ARCH_LS1021A |
| 28 | default 2 |
| 29 | help |
| 30 | Set this number to the maximum number of possible CPUs in the SoC. |
| 31 | SoCs may have multiple clusters with each cluster may have multiple |
| 32 | ports. If some ports are reserved but higher ports are used for |
| 33 | cores, count the reserved ports. This will allocate enough memory |
| 34 | in spin table to properly handle all cores. |
| 35 | |
| York Sun | f64fc5c | 2016-10-04 18:04:37 -0700 | [diff] [blame] | 36 | config NUM_DDR_CONTROLLERS |
| 37 | int "Maximum DDR controllers" |
| 38 | default 1 |
| 39 | |
| York Sun | dfa93a9 | 2016-12-02 09:31:43 -0800 | [diff] [blame] | 40 | config SECURE_BOOT |
| 41 | bool "Secure Boot" |
| 42 | help |
| 43 | Enable Freescale Secure Boot feature. Normally selected |
| 44 | by defconfig. If unsure, do not change. |
| 45 | |
| York Sun | 4dd8c61 | 2016-10-04 14:31:48 -0700 | [diff] [blame] | 46 | config SYS_FSL_ERRATUM_A010315 |
| 47 | bool "Workaround for PCIe erratum A010315" |
| 48 | |
| York Sun | 6b62ef0 | 2016-10-04 18:01:34 -0700 | [diff] [blame] | 49 | config SYS_FSL_SRDS_1 |
| 50 | bool |
| 51 | |
| 52 | config SYS_FSL_SRDS_2 |
| 53 | bool |
| 54 | |
| 55 | config SYS_HAS_SERDES |
| 56 | bool |
| York Sun | f64fc5c | 2016-10-04 18:04:37 -0700 | [diff] [blame] | 57 | |
| York Sun | e7310a3 | 2016-10-04 14:45:54 -0700 | [diff] [blame] | 58 | config SYS_FSL_IFC_BANK_COUNT |
| 59 | int "Maximum banks of Integrated flash controller" |
| 60 | depends on ARCH_LS1021A |
| 61 | default 8 |
| 62 | |
| York Sun | 1dc61ca | 2016-12-28 08:43:41 -0800 | [diff] [blame^] | 63 | config SYS_FSL_ERRATUM_A008407 |
| 64 | bool |
| 65 | |
| York Sun | 4dd8c61 | 2016-10-04 14:31:48 -0700 | [diff] [blame] | 66 | endmenu |