blob: 17f19758a6948d01045f66c4d899ade6362460f5 [file] [log] [blame]
York Sun149eb332016-09-26 08:09:27 -07001config ARCH_LS1021A
York Sunfcd0e742016-10-04 14:31:47 -07002 bool
York Sun149eb332016-09-26 08:09:27 -07003 select SYS_FSL_ERRATUM_A010315
York Sun6b62ef02016-10-04 18:01:34 -07004 select SYS_FSL_SRDS_1
5 select SYS_HAS_SERDES
York Sun4de7e932016-09-26 08:09:29 -07006
York Sun4dd8c612016-10-04 14:31:48 -07007menu "LS102xA architecture"
8 depends on ARCH_LS1021A
9
York Sun4de7e932016-09-26 08:09:29 -070010config LS1_DEEP_SLEEP
York Sunfcd0e742016-10-04 14:31:47 -070011 bool "Deep sleep"
12 depends on ARCH_LS1021A
York Sun4dd8c612016-10-04 14:31:48 -070013
York Sunf188d222016-10-04 14:45:01 -070014config MAX_CPUS
15 int "Maximum number of CPUs permitted for LS102xA"
16 depends on ARCH_LS1021A
17 default 2
18 help
19 Set this number to the maximum number of possible CPUs in the SoC.
20 SoCs may have multiple clusters with each cluster may have multiple
21 ports. If some ports are reserved but higher ports are used for
22 cores, count the reserved ports. This will allocate enough memory
23 in spin table to properly handle all cores.
24
York Sun4dd8c612016-10-04 14:31:48 -070025config SYS_FSL_ERRATUM_A010315
26 bool "Workaround for PCIe erratum A010315"
27
York Sun6b62ef02016-10-04 18:01:34 -070028config SYS_FSL_SRDS_1
29 bool
30
31config SYS_FSL_SRDS_2
32 bool
33
34config SYS_HAS_SERDES
35 bool
36
York Sune7310a32016-10-04 14:45:54 -070037config SYS_FSL_IFC_BANK_COUNT
38 int "Maximum banks of Integrated flash controller"
39 depends on ARCH_LS1021A
40 default 8
41
York Sun4dd8c612016-10-04 14:31:48 -070042endmenu