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York Sun149eb332016-09-26 08:09:27 -07001config ARCH_LS1021A
York Sunfcd0e742016-10-04 14:31:47 -07002 bool
York Sun149eb332016-09-26 08:09:27 -07003 select SYS_FSL_ERRATUM_A010315
York Sun4de7e932016-09-26 08:09:29 -07004
York Sun4dd8c612016-10-04 14:31:48 -07005menu "LS102xA architecture"
6 depends on ARCH_LS1021A
7
York Sun4de7e932016-09-26 08:09:29 -07008config LS1_DEEP_SLEEP
York Sunfcd0e742016-10-04 14:31:47 -07009 bool "Deep sleep"
10 depends on ARCH_LS1021A
York Sun4dd8c612016-10-04 14:31:48 -070011
York Sunf188d222016-10-04 14:45:01 -070012config MAX_CPUS
13 int "Maximum number of CPUs permitted for LS102xA"
14 depends on ARCH_LS1021A
15 default 2
16 help
17 Set this number to the maximum number of possible CPUs in the SoC.
18 SoCs may have multiple clusters with each cluster may have multiple
19 ports. If some ports are reserved but higher ports are used for
20 cores, count the reserved ports. This will allocate enough memory
21 in spin table to properly handle all cores.
22
York Sun4dd8c612016-10-04 14:31:48 -070023config SYS_FSL_ERRATUM_A010315
24 bool "Workaround for PCIe erratum A010315"
25
York Sune7310a32016-10-04 14:45:54 -070026config SYS_FSL_IFC_BANK_COUNT
27 int "Maximum banks of Integrated flash controller"
28 depends on ARCH_LS1021A
29 default 8
30
York Sun4dd8c612016-10-04 14:31:48 -070031endmenu