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git01.mediatek.com / filogic / uboot / 92c36e2c2ce2f6a4af03de3a7ebe7c71a93ca23d / . / arch / arm / cpu / armv7 / ls102xa / Kconfig
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York Sun149eb332016-09-26 08:09:27 -0700[diff] [blame]1config ARCH_LS1021A
York Sunfcd0e742016-10-04 14:31:47 -0700[diff] [blame]2 bool
York Sun149eb332016-09-26 08:09:27 -0700[diff] [blame]3 select SYS_FSL_ERRATUM_A010315
York Sun6b62ef02016-10-04 18:01:34 -0700[diff] [blame]4 select SYS_FSL_SRDS_1
5 select SYS_HAS_SERDES
York Sunf64fc5c2016-10-04 18:04:37 -0700[diff] [blame]6 select SYS_FSL_DDR_BE
7 select SYS_FSL_DDR_VER_50
York Sun92c36e22016-12-28 08:43:30 -0800[diff] [blame^]8 select SYS_FSL_HAS_SEC
9 select SYS_FSL_SEC_COMPAT_5
York Sun4de7e932016-09-26 08:09:29 -0700[diff] [blame]10
York Sun4dd8c612016-10-04 14:31:48 -0700[diff] [blame]11menu "LS102xA architecture"
12 depends on ARCH_LS1021A
13
York Sun4de7e932016-09-26 08:09:29 -0700[diff] [blame]14config LS1_DEEP_SLEEP
York Sunfcd0e742016-10-04 14:31:47 -0700[diff] [blame]15 bool "Deep sleep"
16 depends on ARCH_LS1021A
York Sun4dd8c612016-10-04 14:31:48 -0700[diff] [blame]17
York Sunf188d222016-10-04 14:45:01 -0700[diff] [blame]18config MAX_CPUS
19 int "Maximum number of CPUs permitted for LS102xA"
20 depends on ARCH_LS1021A
21 default 2
22 help
23 Set this number to the maximum number of possible CPUs in the SoC.
24 SoCs may have multiple clusters with each cluster may have multiple
25 ports. If some ports are reserved but higher ports are used for
26 cores, count the reserved ports. This will allocate enough memory
27 in spin table to properly handle all cores.
28
York Sunf64fc5c2016-10-04 18:04:37 -0700[diff] [blame]29config NUM_DDR_CONTROLLERS
30 int "Maximum DDR controllers"
31 default 1
32
York Sundfa93a92016-12-02 09:31:43 -0800[diff] [blame]33config SECURE_BOOT
34 bool "Secure Boot"
35 help
36 Enable Freescale Secure Boot feature. Normally selected
37 by defconfig. If unsure, do not change.
38
York Sun4dd8c612016-10-04 14:31:48 -0700[diff] [blame]39config SYS_FSL_ERRATUM_A010315
40 bool "Workaround for PCIe erratum A010315"
41
York Sun6b62ef02016-10-04 18:01:34 -0700[diff] [blame]42config SYS_FSL_SRDS_1
43 bool
44
45config SYS_FSL_SRDS_2
46 bool
47
48config SYS_HAS_SERDES
49 bool
York Sunf64fc5c2016-10-04 18:04:37 -0700[diff] [blame]50
51config SYS_FSL_DDR
52 bool "Freescale DDR driver"
53 help
54 Select Freescale General DDR driver, shared between most Freescale
55 PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
56 based Layerscape SoCs (such as ls2080a).
57
58config SYS_FSL_DDR_BE
59 bool
60 default y
61 help
62 Access DDR registers in big-endian.
63
64config SYS_FSL_DDR_VER
65 int
66 default 50 if SYS_FSL_DDR_VER_50
67
68config SYS_FSL_DDR_VER_50
69 bool
70
71config SYS_FSL_DDRC_ARM_GEN3
72 bool
73
74config SYS_FSL_DDRC_GEN4
75 bool
76
77config SYS_FSL_DDR3
78 bool "Freescale DDR3 controller"
79 depends on !SYS_FSL_DDR4
80 select SYS_FSL_DDR
81 select SYS_FSL_DDRC_ARM_GEN3
82 help
83 Enable Freescale DDR3 controller on ARM-based SoCs.
84
85config SYS_FSL_DDR4
86 bool "Freescale DDR4 controller"
87 select SYS_FSL_DDR
88 select SYS_FSL_DDRC_GEN4
89 help
90 Enable Freescale DDR4 controller.
York Sun6b62ef02016-10-04 18:01:34 -0700[diff] [blame]91
York Sune7310a32016-10-04 14:45:54 -0700[diff] [blame]92config SYS_FSL_IFC_BANK_COUNT
93 int "Maximum banks of Integrated flash controller"
94 depends on ARCH_LS1021A
95 default 8
96
York Sun4dd8c612016-10-04 14:31:48 -0700[diff] [blame]97endmenu