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git01.mediatek.com / filogic / uboot / 1123406ebbc1d72dd1f456ce29972a154f68f91a / . / arch / arm / cpu / armv7 / ls102xa / Kconfig
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York Sun149eb332016-09-26 08:09:27 -0700[diff] [blame]1config ARCH_LS1021A
York Sunfcd0e742016-10-04 14:31:47 -0700[diff] [blame]2 bool
York Sun1dc61ca2016-12-28 08:43:41 -0800[diff] [blame]3 select SYS_FSL_ERRATUM_A008378
4 select SYS_FSL_ERRATUM_A008407
5 select SYS_FSL_ERRATUM_A009663
6 select SYS_FSL_ERRATUM_A009942
York Sun149eb332016-09-26 08:09:27 -0700[diff] [blame]7 select SYS_FSL_ERRATUM_A010315
Ashish Kumar11234062017-08-11 11:09:14 +0530[diff] [blame^]8 select SYS_FSL_HAS_CCI400
York Sun6b62ef02016-10-04 18:01:34 -0700[diff] [blame]9 select SYS_FSL_SRDS_1
10 select SYS_HAS_SERDES
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]11 select SYS_FSL_DDR_BE if SYS_FSL_DDR
12 select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
13 select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR
14 select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR
York Sun92c36e22016-12-28 08:43:30 -0800[diff] [blame]15 select SYS_FSL_HAS_SEC
16 select SYS_FSL_SEC_COMPAT_5
York Sunfa4199422016-12-28 08:43:31 -0800[diff] [blame]17 select SYS_FSL_SEC_LE
Simon Glass0e5faf02017-06-14 21:28:21 -0600[diff] [blame]18 imply SCSI
Simon Glassc88a09a2017-08-04 16:34:34 -0600[diff] [blame]19 imply CMD_PCI
York Sun4de7e932016-09-26 08:09:29 -0700[diff] [blame]20
York Sun4dd8c612016-10-04 14:31:48 -0700[diff] [blame]21menu "LS102xA architecture"
22 depends on ARCH_LS1021A
23
Hou Zhiqiangd553bf22016-12-13 14:54:24 +0800[diff] [blame]24config FSL_PCIE_COMPAT
25 string "PCIe compatible of Kernel DT"
26 depends on PCIE_LAYERSCAPE
27 default "fsl,ls1021a-pcie" if ARCH_LS1021A
28 help
29 This compatible is used to find pci controller node in Kernel DT
30 to complete fixup.
31
York Sun4de7e932016-09-26 08:09:29 -0700[diff] [blame]32config LS1_DEEP_SLEEP
York Sunfcd0e742016-10-04 14:31:47 -0700[diff] [blame]33 bool "Deep sleep"
34 depends on ARCH_LS1021A
York Sun4dd8c612016-10-04 14:31:48 -0700[diff] [blame]35
York Sunf188d222016-10-04 14:45:01 -0700[diff] [blame]36config MAX_CPUS
37 int "Maximum number of CPUs permitted for LS102xA"
38 depends on ARCH_LS1021A
39 default 2
40 help
41 Set this number to the maximum number of possible CPUs in the SoC.
42 SoCs may have multiple clusters with each cluster may have multiple
43 ports. If some ports are reserved but higher ports are used for
44 cores, count the reserved ports. This will allocate enough memory
45 in spin table to properly handle all cores.
46
York Sundfa93a92016-12-02 09:31:43 -0800[diff] [blame]47config SECURE_BOOT
48 bool "Secure Boot"
49 help
50 Enable Freescale Secure Boot feature. Normally selected
51 by defconfig. If unsure, do not change.
52
Ashish Kumar11234062017-08-11 11:09:14 +0530[diff] [blame^]53config SYS_CCI400_OFFSET
54 hex "Offset for CCI400 base"
55 depends on SYS_FSL_HAS_CCI400
56 default 0x180000
57 help
58 Offset for CCI400 base.
59 CCI400 base addr = CCSRBAR + CCI400_OFFSET
60
York Sun4dd8c612016-10-04 14:31:48 -0700[diff] [blame]61config SYS_FSL_ERRATUM_A010315
62 bool "Workaround for PCIe erratum A010315"
63
Ashish Kumar11234062017-08-11 11:09:14 +0530[diff] [blame^]64config SYS_FSL_HAS_CCI400
65 bool
66
York Sun6b62ef02016-10-04 18:01:34 -0700[diff] [blame]67config SYS_FSL_SRDS_1
68 bool
69
70config SYS_FSL_SRDS_2
71 bool
72
73config SYS_HAS_SERDES
74 bool
York Sunf64fc5c2016-10-04 18:04:37 -0700[diff] [blame]75
York Sune7310a32016-10-04 14:45:54 -0700[diff] [blame]76config SYS_FSL_IFC_BANK_COUNT
77 int "Maximum banks of Integrated flash controller"
78 depends on ARCH_LS1021A
79 default 8
80
York Sun1dc61ca2016-12-28 08:43:41 -0800[diff] [blame]81config SYS_FSL_ERRATUM_A008407
82 bool
83
York Sun4dd8c612016-10-04 14:31:48 -0700[diff] [blame]84endmenu