Blame - arch/arm/cpu/armv7/ls102xa/Kconfig - filogic/uboot

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York Sun	149eb33	2016-09-26 08:09:27 -0700	[diff] [blame]	1	config ARCH_LS1021A
York Sun	fcd0e74	2016-10-04 14:31:47 -0700	[diff] [blame]	2	bool
York Sun	1dc61ca	2016-12-28 08:43:41 -0800	[diff] [blame]	3	select SYS_FSL_ERRATUM_A008378
				4	select SYS_FSL_ERRATUM_A008407
Ran Wang	373a7b0	2017-09-04 18:46:54 +0800	[diff] [blame]	5	select SYS_FSL_ERRATUM_A008997
Ran Wang	2eb4898	2017-09-04 18:46:55 +0800	[diff] [blame]	6	select SYS_FSL_ERRATUM_A009007
Ran Wang	1509c8a	2017-09-04 18:46:52 +0800	[diff] [blame]	7	select SYS_FSL_ERRATUM_A009008
York Sun	1dc61ca	2016-12-28 08:43:41 -0800	[diff] [blame]	8	select SYS_FSL_ERRATUM_A009663
Ran Wang	d2b711b7	2017-09-04 18:46:53 +0800	[diff] [blame]	9	select SYS_FSL_ERRATUM_A009798
York Sun	1dc61ca	2016-12-28 08:43:41 -0800	[diff] [blame]	10	select SYS_FSL_ERRATUM_A009942
York Sun	149eb33	2016-09-26 08:09:27 -0700	[diff] [blame]	11	select SYS_FSL_ERRATUM_A010315
Ashish Kumar	1123406	2017-08-11 11:09:14 +0530	[diff] [blame]	12	select SYS_FSL_HAS_CCI400
York Sun	6b62ef0	2016-10-04 18:01:34 -0700	[diff] [blame]	13	select SYS_FSL_SRDS_1
				14	select SYS_HAS_SERDES
York Sun	d297d39	2016-12-28 08:43:40 -0800	[diff] [blame]	15	select SYS_FSL_DDR_BE if SYS_FSL_DDR
				16	select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
				17	select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR
				18	select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR
York Sun	92c36e2	2016-12-28 08:43:30 -0800	[diff] [blame]	19	select SYS_FSL_HAS_SEC
				20	select SYS_FSL_SEC_COMPAT_5
York Sun	fa419942	2016-12-28 08:43:31 -0800	[diff] [blame]	21	select SYS_FSL_SEC_LE
Simon Glass	0e5faf0	2017-06-14 21:28:21 -0600	[diff] [blame]	22	imply SCSI
Tuomas Tynkkynen	edf9f62	2017-12-08 15:36:19 +0200	[diff] [blame]	23	imply SCSI_AHCI
Simon Glass	c88a09a	2017-08-04 16:34:34 -0600	[diff] [blame]	24	imply CMD_PCI
York Sun	4de7e93	2016-09-26 08:09:29 -0700	[diff] [blame]	25
York Sun	4dd8c61	2016-10-04 14:31:48 -0700	[diff] [blame]	26	menu "LS102xA architecture"
				27	depends on ARCH_LS1021A
				28
Hou Zhiqiang	d553bf2	2016-12-13 14:54:24 +0800	[diff] [blame]	29	config FSL_PCIE_COMPAT
				30	string "PCIe compatible of Kernel DT"
				31	depends on PCIE_LAYERSCAPE
				32	default "fsl,ls1021a-pcie" if ARCH_LS1021A
				33	help
				34	This compatible is used to find pci controller node in Kernel DT
				35	to complete fixup.
				36
York Sun	4de7e93	2016-09-26 08:09:29 -0700	[diff] [blame]	37	config LS1_DEEP_SLEEP
York Sun	fcd0e74	2016-10-04 14:31:47 -0700	[diff] [blame]	38	bool "Deep sleep"
				39	depends on ARCH_LS1021A
York Sun	4dd8c61	2016-10-04 14:31:48 -0700	[diff] [blame]	40
York Sun	f188d22	2016-10-04 14:45:01 -0700	[diff] [blame]	41	config MAX_CPUS
				42	int "Maximum number of CPUs permitted for LS102xA"
				43	depends on ARCH_LS1021A
				44	default 2
				45	help
				46	Set this number to the maximum number of possible CPUs in the SoC.
				47	SoCs may have multiple clusters with each cluster may have multiple
				48	ports. If some ports are reserved but higher ports are used for
				49	cores, count the reserved ports. This will allocate enough memory
				50	in spin table to properly handle all cores.
				51
York Sun	dfa93a9	2016-12-02 09:31:43 -0800	[diff] [blame]	52	config SECURE_BOOT
				53	bool "Secure Boot"
				54	help
				55	Enable Freescale Secure Boot feature. Normally selected
				56	by defconfig. If unsure, do not change.
				57
Ashish Kumar	1123406	2017-08-11 11:09:14 +0530	[diff] [blame]	58	config SYS_CCI400_OFFSET
				59	hex "Offset for CCI400 base"
				60	depends on SYS_FSL_HAS_CCI400
				61	default 0x180000
				62	help
				63	Offset for CCI400 base.
				64	CCI400 base addr = CCSRBAR + CCI400_OFFSET
				65
Ran Wang	373a7b0	2017-09-04 18:46:54 +0800	[diff] [blame]	66	config SYS_FSL_ERRATUM_A008997
				67	bool
				68	help
				69	Workaround for USB PHY erratum A008997
				70
Ran Wang	2eb4898	2017-09-04 18:46:55 +0800	[diff] [blame]	71	config SYS_FSL_ERRATUM_A009007
				72	bool
				73	help
				74	Workaround for USB PHY erratum A009007
				75
Ran Wang	1509c8a	2017-09-04 18:46:52 +0800	[diff] [blame]	76	config SYS_FSL_ERRATUM_A009008
				77	bool
				78	help
				79	Workaround for USB PHY erratum A009008
				80
Ran Wang	d2b711b7	2017-09-04 18:46:53 +0800	[diff] [blame]	81	config SYS_FSL_ERRATUM_A009798
				82	bool
				83	help
				84	Workaround for USB PHY erratum A009798
				85
York Sun	4dd8c61	2016-10-04 14:31:48 -0700	[diff] [blame]	86	config SYS_FSL_ERRATUM_A010315
				87	bool "Workaround for PCIe erratum A010315"
				88
Ashish Kumar	1123406	2017-08-11 11:09:14 +0530	[diff] [blame]	89	config SYS_FSL_HAS_CCI400
				90	bool
				91
York Sun	6b62ef0	2016-10-04 18:01:34 -0700	[diff] [blame]	92	config SYS_FSL_SRDS_1
				93	bool
				94
				95	config SYS_FSL_SRDS_2
				96	bool
				97
				98	config SYS_HAS_SERDES
				99	bool
York Sun	f64fc5c	2016-10-04 18:04:37 -0700	[diff] [blame]	100
York Sun	e7310a3	2016-10-04 14:45:54 -0700	[diff] [blame]	101	config SYS_FSL_IFC_BANK_COUNT
				102	int "Maximum banks of Integrated flash controller"
				103	depends on ARCH_LS1021A
				104	default 8
				105
York Sun	1dc61ca	2016-12-28 08:43:41 -0800	[diff] [blame]	106	config SYS_FSL_ERRATUM_A008407
				107	bool
				108
York Sun	4dd8c61	2016-10-04 14:31:48 -0700	[diff] [blame]	109	endmenu