blob: e264b29554cf0c7b89f64751c0d862e88290fb57 [file] [log] [blame]
Simon Glass4cc43bf2021-08-18 21:40:25 -06001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Devicetree file for running sandbox tests
4 *
5 * This includes lots of extra devices used by various tests.
6 *
7 * Note that SPL use the main sandbox.dts file
8 */
9
Simon Glassb2c1cac2014-02-26 15:59:21 -070010/dts-v1/;
11
Eddie James1a55a7a2023-10-24 10:43:51 -050012#include <config.h>
Patrick Delaunay23aee612020-01-13 11:35:13 +010013#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/gpio/sandbox-gpio.h>
Marek Szyprowskiad398592021-02-18 11:33:18 +010015#include <dt-bindings/input/input.h>
Sean Anderson3438e3b2020-09-14 11:01:57 -040016#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +053017#include <dt-bindings/mux/mux.h>
Patrick Delaunay23aee612020-01-13 11:35:13 +010018
Simon Glassb2c1cac2014-02-26 15:59:21 -070019/ {
20 model = "sandbox";
21 compatible = "sandbox";
22 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -060023 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070024
Simon Glassfef72b72014-07-23 06:55:03 -060025 aliases {
26 console = &uart0;
Michael Walle7efcdfd2021-02-25 16:51:11 +010027 ethernet0 = "/eth@10002000";
28 ethernet2 = &swp_0;
29 ethernet3 = &eth_3;
30 ethernet4 = &dsa_eth0;
31 ethernet5 = &eth_5;
Sean Anderson67d93a42022-05-05 13:11:30 -040032 ethernet6 = "/eth@10004000";
33 ethernet7 = &swp_1;
34 ethernet8 = &phy_eth0;
Simon Glass5620cf82018-10-01 12:22:40 -060035 gpio1 = &gpio_a;
36 gpio2 = &gpio_b;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +010037 gpio3 = &gpio_c;
Simon Glass0ccb0972015-01-25 08:27:05 -070038 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -060039 mmc0 = "/mmc0";
40 mmc1 = "/mmc1";
Simon Glassf1eba352022-10-20 18:23:20 -060041 mmc2 = "/mmc2";
42 mmc3 = "/mmc3";
Simon Glassfff928c2023-08-24 13:55:41 -060043 mmc4 = "/mmc4";
44 mmc5 = "/mmc5";
Alexander Gendin038cb022023-10-09 01:24:36 +000045 mmc6 = "/mmc6";
Bin Meng408e5902018-08-03 01:14:41 -070046 pci0 = &pci0;
47 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -070048 pci2 = &pci2;
Michael Walle7c41a222020-06-02 01:47:09 +020049 remoteproc0 = &rproc_1;
50 remoteproc1 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -060051 rtc0 = &rtc_0;
52 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -060053 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +020054 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -070055 testbus3 = "/some-bus";
56 testfdt0 = "/some-bus/c-test@0";
Simon Glass7d5e4112020-12-16 21:20:26 -070057 testfdt12 = "/some-bus/c-test@1";
Simon Glass0ccb0972015-01-25 08:27:05 -070058 testfdt3 = "/b-test";
59 testfdt5 = "/some-bus/c-test@5";
60 testfdt8 = "/a-test";
Simon Glass791a17f2020-12-16 21:20:27 -070061 testfdtm1 = &testfdtm1;
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +020062 fdt-dummy0 = "/translation-test@8000/dev@0,0";
63 fdt-dummy1 = "/translation-test@8000/dev@1,100";
64 fdt-dummy2 = "/translation-test@8000/dev@2,200";
65 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glass31680482015-03-25 12:23:05 -060066 usb0 = &usb_0;
67 usb1 = &usb_1;
68 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +020069 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +020070 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -060071 };
72
Eddie James1a55a7a2023-10-24 10:43:51 -050073 reserved-memory {
74 #address-cells = <1>;
75 #size-cells = <1>;
76 ranges;
77
78 event_log: tcg_event_log {
79 no-map;
80 reg = <(CFG_SYS_SDRAM_SIZE - 0x2000) 0x2000>;
81 };
82 };
83
Simon Glass5e135d32022-10-20 18:23:15 -060084 binman: binman {
Philippe Reynes462d1632022-03-28 22:56:53 +020085 };
86
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020087 config {
Simon Glass0034d962021-08-07 07:24:01 -060088 testing-bool;
89 testing-int = <123>;
90 testing-str = "testing";
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020091 environment {
92 from_fdt = "yes";
93 fdt_env_path = "";
94 };
95 };
96
Michal Simek43c42bd2023-08-31 08:59:05 +020097 options {
98 u-boot {
99 compatible = "u-boot,config";
100 bootscr-ram-offset = /bits/ 64 <0x12345678>;
Michal Simek6a7c1ce2023-08-31 09:04:27 +0200101 bootscr-flash-offset = /bits/ 64 <0>;
102 bootscr-flash-size = /bits/ 64 <0x2000>;
Michal Simek43c42bd2023-08-31 08:59:05 +0200103 };
104 };
105
Simon Glassb255efc2022-04-24 23:31:24 -0600106 bootstd {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700107 bootph-verify;
Simon Glassb255efc2022-04-24 23:31:24 -0600108 compatible = "u-boot,boot-std";
109
110 filename-prefixes = "/", "/boot/";
111 bootdev-order = "mmc2", "mmc1";
112
Simon Glassb71d7f72023-05-10 16:34:46 -0600113 extlinux {
114 compatible = "u-boot,extlinux";
Simon Glassb255efc2022-04-24 23:31:24 -0600115 };
116
117 efi {
118 compatible = "u-boot,distro-efi";
119 };
Simon Glassa9289612022-10-20 18:23:14 -0600120
Simon Glassd2bc33ed2023-01-06 08:52:41 -0600121 theme {
122 font-size = <30>;
Simon Glass86f1ac52023-06-01 10:23:00 -0600123 menu-inset = <3>;
124 menuitem-gap-y = <1>;
Simon Glassd2bc33ed2023-01-06 08:52:41 -0600125 };
126
Simon Glass82adc292023-08-14 16:40:30 -0600127 cedit-theme {
128 font-size = <30>;
129 menu-inset = <3>;
130 menuitem-gap-y = <1>;
131 };
132
Simon Glassf1eba352022-10-20 18:23:20 -0600133 /*
134 * This is used for the VBE OS-request tests. A FAT filesystem
135 * created in a partition with the VBE information appearing
Michal Simek33224372023-09-07 14:55:48 +0200136 * before the partition starts
Simon Glassf1eba352022-10-20 18:23:20 -0600137 */
Simon Glassa9289612022-10-20 18:23:14 -0600138 firmware0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700139 bootph-verify;
Simon Glassa9289612022-10-20 18:23:14 -0600140 compatible = "fwupd,vbe-simple";
141 storage = "mmc1";
142 skip-offset = <0x200>;
143 area-start = <0x400>;
144 area-size = <0x1000>;
145 state-offset = <0x400>;
146 state-size = <0x40>;
147 version-offset = <0x800>;
148 version-size = <0x100>;
149 };
Simon Glassf1eba352022-10-20 18:23:20 -0600150
151 /*
152 * This is used for the VBE VPL tests. The MMC device holds the
153 * binman image.bin file. The test progresses through each phase
154 * of U-Boot, loading each in turn from MMC.
155 *
156 * Note that the test enables this node (and mmc3) before
157 * running U-Boot
158 */
159 firmware1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700160 bootph-verify;
Simon Glassf1eba352022-10-20 18:23:20 -0600161 status = "disabled";
162 compatible = "fwupd,vbe-simple";
163 storage = "mmc3";
Simon Glass9bb73e32023-04-02 14:01:24 +1200164 skip-offset = <0x800000>;
Simon Glassf1eba352022-10-20 18:23:20 -0600165 area-start = <0>;
166 area-size = <0xe00000>;
167 state-offset = <0xdffc00>;
168 state-size = <0x40>;
169 version-offset = <0xdffe00>;
170 version-size = <0x100>;
171 };
Simon Glassb255efc2022-04-24 23:31:24 -0600172 };
173
Simon Glass61300722023-06-01 10:23:01 -0600174 cedit: cedit {
175 };
176
Andrew Scull451b8b12022-05-30 10:00:12 +0000177 fuzzing-engine {
178 compatible = "sandbox,fuzzing-engine";
179 };
180
Nandor Han6521e5d2021-06-10 16:56:44 +0300181 reboot-mode0 {
182 compatible = "reboot-mode-gpio";
183 gpios = <&gpio_c 0 GPIO_ACTIVE_HIGH>, <&gpio_c 1 GPIO_ACTIVE_HIGH>;
184 u-boot,env-variable = "bootstatus";
185 mode-test = <0x01>;
186 mode-download = <0x03>;
187 };
188
Nandor Han7e4067a2021-06-10 16:56:45 +0300189 reboot_mode1: reboot-mode@14 {
190 compatible = "reboot-mode-rtc";
191 rtc = <&rtc_0>;
192 reg = <0x30 4>;
193 u-boot,env-variable = "bootstatus";
194 big-endian;
195 mode-test = <0x21969147>;
196 mode-download = <0x51939147>;
197 };
198
Simon Glassed96cde2018-12-10 10:37:33 -0700199 audio: audio-codec {
200 compatible = "sandbox,audio-codec";
201 #sound-dai-cells = <1>;
202 };
203
Philippe Reynes1ee26482020-07-24 18:19:51 +0200204 buttons {
205 compatible = "gpio-keys";
206
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200207 btn1 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200208 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200209 label = "button1";
Dzmitry Sankouski157f2c52023-01-22 18:21:24 +0300210 linux,code = <BTN_1>;
Philippe Reynes1ee26482020-07-24 18:19:51 +0200211 };
212
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200213 btn2 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200214 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200215 label = "button2";
Dzmitry Sankouski157f2c52023-01-22 18:21:24 +0300216 linux,code = <BTN_2>;
Philippe Reynes1ee26482020-07-24 18:19:51 +0200217 };
218 };
219
Marek Szyprowskiad398592021-02-18 11:33:18 +0100220 buttons2 {
221 compatible = "adc-keys";
222 io-channels = <&adc 3>;
223 keyup-threshold-microvolt = <3000000>;
224
225 button-up {
226 label = "button3";
227 linux,code = <KEY_F3>;
228 press-threshold-microvolt = <1500000>;
229 };
230
231 button-down {
232 label = "button4";
233 linux,code = <KEY_F4>;
234 press-threshold-microvolt = <1000000>;
235 };
236
237 button-enter {
238 label = "button5";
239 linux,code = <KEY_F5>;
240 press-threshold-microvolt = <500000>;
241 };
242 };
243
Simon Glassc953aaf2018-12-10 10:37:34 -0700244 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -0600245 reg = <0 0>;
246 compatible = "google,cros-ec-sandbox";
247
248 /*
249 * This describes the flash memory within the EC. Note
250 * that the STM32L flash erases to 0, not 0xff.
251 */
252 flash {
253 image-pos = <0x08000000>;
254 size = <0x20000>;
255 erase-value = <0>;
256
257 /* Information for sandbox */
258 ro {
259 image-pos = <0>;
260 size = <0xf000>;
261 };
262 wp-ro {
263 image-pos = <0xf000>;
264 size = <0x1000>;
Simon Glassbf0a6922021-01-21 13:57:14 -0700265 used = <0x884>;
266 compress = "lz4";
267 uncomp-size = <0xcf8>;
268 hash {
269 algo = "sha256";
270 value = [00 01 02 03 04 05 06 07
271 08 09 0a 0b 0c 0d 0e 0f
272 10 11 12 13 14 15 16 17
273 18 19 1a 1b 1c 1d 1e 1f];
274 };
Simon Glass699c9ca2018-10-01 12:22:08 -0600275 };
276 rw {
277 image-pos = <0x10000>;
278 size = <0x10000>;
279 };
280 };
Alper Nebi Yasak8a8cd4f2021-05-19 19:33:31 +0300281
282 cros_ec_pwm: cros-ec-pwm {
283 compatible = "google,cros-ec-pwm";
284 #pwm-cells = <1>;
285 };
286
Simon Glass699c9ca2018-10-01 12:22:08 -0600287 };
288
Yannick Fertré9712c822019-10-07 15:29:05 +0200289 dsi_host: dsi_host {
290 compatible = "sandbox,dsi-host";
291 };
292
Simon Glassb2c1cac2014-02-26 15:59:21 -0700293 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600294 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700295 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600296 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700297 ping-add = <0>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700298 bootph-all;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100299 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
300 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass16e10402015-01-05 20:05:29 -0700301 <0>, <&gpio_a 12>;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100302 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
303 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
304 <&gpio_b 7 GPIO_IN 3 2 1>,
305 <&gpio_b 8 GPIO_OUT 3 2 1>,
306 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100307 test3-gpios =
308 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
309 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
310 <&gpio_c 2 GPIO_OUT>,
311 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
312 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong643778b2020-05-05 10:43:18 +0200313 <&gpio_c 5 GPIO_IN>,
314 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
315 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530316 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
317 test5-gpios = <&gpio_a 19>;
318
Simon Glass73025392021-10-23 17:26:04 -0600319 bool-value;
Stefan Herbrechtsmeier1b090e62022-06-14 15:21:30 +0200320 int8-value = /bits/ 8 <0x12>;
321 int16-value = /bits/ 16 <0x1234>;
Simon Glass6df01f92018-12-10 10:37:37 -0700322 int-value = <1234>;
323 uint-value = <(-1234)>;
Dario Binacchi421e81e2020-03-29 18:04:40 +0200324 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi81d80b52020-03-29 18:04:41 +0200325 int-array = <5678 9123 4567>;
Michal Simek08a194e2023-08-25 11:37:46 +0200326 int64-array = /bits/ 64 <0x1111222233334444 0x4444333322221111>;
Simon Glassdd0ed902020-07-07 13:11:58 -0600327 str-value = "test string";
Simon Glass515dcff2020-02-06 09:55:00 -0700328 interrupts-extended = <&irq 3 0>;
Simon Glass09642392020-07-07 13:12:11 -0600329 acpi,name = "GHIJ";
Patrick Delaunay8cd28012020-09-25 09:41:16 +0200330 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530331
332 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
333 <&muxcontroller0 2>, <&muxcontroller0 3>,
334 <&muxcontroller1>;
335 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
336 mux-syscon = <&syscon3>;
Dario Binacchi836cc9d2020-12-30 00:16:26 +0100337 display-timings {
338 timing0: 240x320 {
339 clock-frequency = <6500000>;
340 hactive = <240>;
341 vactive = <320>;
342 hfront-porch = <6>;
343 hback-porch = <7>;
344 hsync-len = <1>;
345 vback-porch = <5>;
346 vfront-porch = <8>;
347 vsync-len = <2>;
348 hsync-active = <1>;
349 vsync-active = <0>;
350 de-active = <1>;
351 pixelclk-active = <1>;
352 interlaced;
353 doublescan;
354 doubleclk;
355 };
356 timing1: 480x800 {
357 clock-frequency = <9000000>;
358 hactive = <480>;
359 vactive = <800>;
360 hfront-porch = <10>;
361 hback-porch = <59>;
362 hsync-len = <12>;
363 vback-porch = <15>;
364 vfront-porch = <17>;
365 vsync-len = <16>;
366 hsync-active = <0>;
367 vsync-active = <1>;
368 de-active = <0>;
369 pixelclk-active = <0>;
370 };
371 timing2: 800x480 {
372 clock-frequency = <33500000>;
373 hactive = <800>;
374 vactive = <480>;
375 hback-porch = <89>;
376 hfront-porch = <164>;
377 vback-porch = <23>;
378 vfront-porch = <10>;
379 hsync-len = <11>;
380 vsync-len = <13>;
381 };
382 };
Raphael Gallais-Poua853b922023-05-11 16:36:52 +0200383 panel-timing {
Nikhil M Jainbb9d1312023-01-31 15:35:15 +0530384 clock-frequency = <6500000>;
385 hactive = <240>;
386 vactive = <320>;
387 hfront-porch = <6>;
388 hback-porch = <7>;
389 hsync-len = <1>;
390 vback-porch = <5>;
391 vfront-porch = <8>;
392 vsync-len = <2>;
393 hsync-active = <1>;
394 vsync-active = <0>;
395 de-active = <1>;
396 pixelclk-active = <1>;
397 interlaced;
398 doublescan;
399 doubleclk;
400 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700401 };
402
403 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600404 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700405 compatible = "not,compatible";
406 };
407
408 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600409 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700410 };
411
Simon Glass5620cf82018-10-01 12:22:40 -0600412 backlight: backlight {
413 compatible = "pwm-backlight";
414 enable-gpios = <&gpio_a 1>;
415 power-supply = <&ldo_1>;
416 pwms = <&pwm 0 1000>;
417 default-brightness-level = <5>;
418 brightness-levels = <0 16 32 64 128 170 202 234 255>;
419 };
420
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200421 bind-test {
Patrice Chotard7b7f9392020-07-28 09:13:33 +0200422 compatible = "simple-bus";
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200423 bind-test-child1 {
424 compatible = "sandbox,phy";
425 #phy-cells = <1>;
426 };
427
428 bind-test-child2 {
429 compatible = "simple-bus";
430 };
431 };
432
Simon Glassb2c1cac2014-02-26 15:59:21 -0700433 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600434 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700435 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600436 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700437 ping-add = <3>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530438
439 mux-controls = <&muxcontroller0 0>;
440 mux-control-names = "mux0";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700441 };
442
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200443 phy_provider0: gen_phy@0 {
444 compatible = "sandbox,phy";
445 #phy-cells = <1>;
446 };
447
448 phy_provider1: gen_phy@1 {
449 compatible = "sandbox,phy";
450 #phy-cells = <0>;
451 broken;
452 };
453
developer71092972020-05-02 11:35:12 +0200454 phy_provider2: gen_phy@2 {
455 compatible = "sandbox,phy";
456 #phy-cells = <0>;
457 };
458
Jonas Karlman9f89e682023-08-31 22:16:35 +0000459 phy_provider3: gen_phy@3 {
460 compatible = "sandbox,phy";
461 #phy-cells = <2>;
462 };
463
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200464 gen_phy_user: gen_phy_user {
465 compatible = "simple-bus";
466 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
467 phy-names = "phy1", "phy2", "phy3";
468 };
469
developer71092972020-05-02 11:35:12 +0200470 gen_phy_user1: gen_phy_user1 {
471 compatible = "simple-bus";
472 phys = <&phy_provider0 0>, <&phy_provider2>;
473 phy-names = "phy1", "phy2";
474 };
475
Jonas Karlman9f89e682023-08-31 22:16:35 +0000476 gen_phy_user2: gen_phy_user2 {
477 compatible = "simple-bus";
478 phys = <&phy_provider3 0 0>;
479 phy-names = "phy1";
480 };
481
Simon Glassb2c1cac2014-02-26 15:59:21 -0700482 some-bus {
483 #address-cells = <1>;
484 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600485 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600486 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600487 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700488 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600489 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700490 compatible = "denx,u-boot-fdt-test";
491 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600492 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700493 ping-add = <5>;
494 };
Simon Glass40717422014-07-23 06:55:18 -0600495 c-test@0 {
496 compatible = "denx,u-boot-fdt-test";
497 reg = <0>;
498 ping-expect = <6>;
499 ping-add = <6>;
500 };
501 c-test@1 {
502 compatible = "denx,u-boot-fdt-test";
503 reg = <1>;
504 ping-expect = <7>;
505 ping-add = <7>;
506 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700507 };
508
509 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600510 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600511 ping-expect = <6>;
512 ping-add = <6>;
513 compatible = "google,another-fdt-test";
514 };
515
516 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600517 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600518 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700519 ping-add = <6>;
520 compatible = "google,another-fdt-test";
521 };
522
Simon Glass0ccb0972015-01-25 08:27:05 -0700523 f-test {
524 compatible = "denx,u-boot-fdt-test";
525 };
526
527 g-test {
528 compatible = "denx,u-boot-fdt-test";
529 };
530
Bin Mengd9d24782018-10-10 22:07:01 -0700531 h-test {
532 compatible = "denx,u-boot-fdt-test1";
533 };
534
developercf8bc132020-05-02 11:35:10 +0200535 i-test {
536 compatible = "mediatek,u-boot-fdt-test";
537 #address-cells = <1>;
538 #size-cells = <0>;
539
540 subnode@0 {
541 reg = <0>;
542 };
543
544 subnode@1 {
545 reg = <1>;
546 };
547
548 subnode@2 {
549 reg = <2>;
550 };
551 };
552
Simon Glass204675c2019-12-29 21:19:25 -0700553 devres-test {
554 compatible = "denx,u-boot-devres-test";
555 };
556
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530557 another-test {
558 reg = <0 2>;
559 compatible = "denx,u-boot-fdt-test";
560 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
561 test5-gpios = <&gpio_a 19>;
562 };
563
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100564 mmio-bus@0 {
565 #address-cells = <1>;
566 #size-cells = <1>;
567 compatible = "denx,u-boot-test-bus";
568 dma-ranges = <0x10000000 0x00000000 0x00040000>;
569
570 subnode@0 {
571 compatible = "denx,u-boot-fdt-test";
572 };
573 };
574
575 mmio-bus@1 {
576 #address-cells = <1>;
577 #size-cells = <1>;
578 compatible = "denx,u-boot-test-bus";
Nicolas Saenz Julienne892e9b42021-01-12 13:55:25 +0100579
580 subnode@0 {
581 compatible = "denx,u-boot-fdt-test";
582 };
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100583 };
584
Simon Glass3c601b12020-07-07 13:12:06 -0600585 acpi_test1: acpi-test {
Simon Glass2d67fdf2020-04-08 16:57:34 -0600586 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600587 acpi-ssdt-test-data = "ab";
Simon Glass990cd5b2020-07-07 13:12:08 -0600588 acpi-dsdt-test-data = "hi";
Simon Glassebb2e832020-07-07 13:11:39 -0600589 child {
590 compatible = "denx,u-boot-acpi-test";
591 };
Simon Glass2d67fdf2020-04-08 16:57:34 -0600592 };
593
Simon Glass3c601b12020-07-07 13:12:06 -0600594 acpi_test2: acpi-test2 {
Simon Glass17968c32020-04-26 09:19:46 -0600595 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600596 acpi-ssdt-test-data = "cd";
Simon Glass990cd5b2020-07-07 13:12:08 -0600597 acpi-dsdt-test-data = "jk";
Simon Glass17968c32020-04-26 09:19:46 -0600598 };
599
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200600 clocks {
601 clk_fixed: clk-fixed {
602 compatible = "fixed-clock";
603 #clock-cells = <0>;
604 clock-frequency = <1234>;
605 };
Anup Patel8d28c3c2019-02-25 08:14:55 +0000606
607 clk_fixed_factor: clk-fixed-factor {
608 compatible = "fixed-factor-clock";
609 #clock-cells = <0>;
610 clock-div = <3>;
611 clock-mult = <2>;
612 clocks = <&clk_fixed>;
613 };
Lukasz Majewskiccafcdd2019-06-24 15:50:47 +0200614
615 osc {
616 compatible = "fixed-clock";
617 #clock-cells = <0>;
618 clock-frequency = <20000000>;
619 };
Stephen Warrena9622432016-06-17 09:44:00 -0600620 };
621
622 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600623 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600624 #clock-cells = <1>;
Jean-Jacques Hiblotc1e9c942019-10-22 14:00:07 +0200625 assigned-clocks = <&clk_sandbox 3>;
626 assigned-clock-rates = <321>;
Stephen Warrena9622432016-06-17 09:44:00 -0600627 };
628
629 clk-test {
630 compatible = "sandbox,clk-test";
631 clocks = <&clk_fixed>,
632 <&clk_sandbox 1>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200633 <&clk_sandbox 0>,
Yang Xiwene89289c2023-12-16 02:28:52 +0800634 <&ccf 11>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200635 <&clk_sandbox 3>,
636 <&clk_sandbox 2>;
Yang Xiwene89289c2023-12-16 02:28:52 +0800637 clock-names = "fixed", "i2c", "spi", "i2c_root", "uart2", "uart1";
Simon Glass8cc4d822015-07-06 12:54:24 -0600638 };
639
Ashok Reddy Soma8f03cef2023-08-30 10:31:42 +0200640 clk-test2 {
641 compatible = "sandbox,clk-test";
642 assigned-clock-rates = <321>;
643 };
644
645 clk-test3 {
646 compatible = "sandbox,clk-test";
647 assigned-clocks = <&clk_sandbox 1>;
648 };
649
650 clk-test4 {
651 compatible = "sandbox,clk-test";
652 assigned-clock-rates = <654>, <321>;
653 assigned-clocks = <&clk_sandbox 1>;
654 };
655
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200656 ccf: clk-ccf {
657 compatible = "sandbox,clk-ccf";
Yang Xiwene89289c2023-12-16 02:28:52 +0800658 #clock-cells = <1>;
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200659 };
660
Simon Glass507ab962021-12-04 08:56:31 -0700661 efi-media {
662 compatible = "sandbox,efi-media";
663 };
664
Simon Glass5b968632015-05-22 15:42:15 -0600665 eth@10002000 {
666 compatible = "sandbox,eth";
667 reg = <0x10002000 0x1000>;
Simon Glass5b968632015-05-22 15:42:15 -0600668 };
669
670 eth_5: eth@10003000 {
671 compatible = "sandbox,eth";
672 reg = <0x10003000 0x1000>;
Sean Anderson13652b82022-05-05 13:11:44 -0400673 nvmem-cells = <&eth5_addr>;
674 nvmem-cell-names = "mac-address";
Simon Glass5b968632015-05-22 15:42:15 -0600675 };
676
Bin Meng04a11cb2015-08-27 22:25:53 -0700677 eth_3: sbe5 {
678 compatible = "sandbox,eth";
679 reg = <0x10005000 0x1000>;
Sean Andersone2dc0e62022-05-05 13:11:42 -0400680 nvmem-cells = <&eth3_addr>;
681 nvmem-cell-names = "mac-address";
Bin Meng04a11cb2015-08-27 22:25:53 -0700682 };
683
Simon Glass5b968632015-05-22 15:42:15 -0600684 eth@10004000 {
685 compatible = "sandbox,eth";
686 reg = <0x10004000 0x1000>;
Simon Glass5b968632015-05-22 15:42:15 -0600687 };
688
Marek Behúnf4f1ddc2022-04-07 00:32:57 +0200689 phy_eth0: phy-test-eth {
690 compatible = "sandbox,eth";
691 reg = <0x10007000 0x1000>;
Sean Anderson24b1b8d2022-05-05 13:11:35 -0400692 mac-address = [ 02 00 11 22 33 49 ];
Marek Behúnf4f1ddc2022-04-07 00:32:57 +0200693 phy-handle = <&ethphy1>;
Marek Behúnbc194772022-04-07 00:33:01 +0200694 phy-mode = "2500base-x";
Marek Behúnf4f1ddc2022-04-07 00:32:57 +0200695 };
696
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800697 dsa_eth0: dsa-test-eth {
698 compatible = "sandbox,eth";
699 reg = <0x10006000 0x1000>;
Sean Anderson5768e8b2022-05-05 13:11:43 -0400700 nvmem-cells = <&eth4_addr>;
701 nvmem-cell-names = "mac-address";
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800702 };
703
704 dsa-test {
705 compatible = "sandbox,dsa";
706
707 ports {
708 #address-cells = <1>;
709 #size-cells = <0>;
710 swp_0: port@0 {
711 reg = <0>;
712 label = "lan0";
713 phy-mode = "rgmii-rxid";
714
715 fixed-link {
716 speed = <100>;
717 full-duplex;
718 };
719 };
720
721 swp_1: port@1 {
722 reg = <1>;
723 label = "lan1";
724 phy-mode = "rgmii-txid";
Bin Meng381ed972021-03-14 20:14:58 +0800725 fixed-link = <0 1 100 0 0>;
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800726 };
727
728 port@2 {
729 reg = <2>;
730 ethernet = <&dsa_eth0>;
731
732 fixed-link {
733 speed = <1000>;
734 full-duplex;
735 };
736 };
737 };
738 };
739
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700740 firmware {
741 sandbox_firmware: sandbox-firmware {
742 compatible = "sandbox,firmware";
743 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200744
Etienne Carriere09665cb2022-02-21 09:22:39 +0100745 scmi {
Etienne Carriere02fd1262020-09-09 18:44:00 +0200746 compatible = "sandbox,scmi-agent";
747 #address-cells = <1>;
748 #size-cells = <0>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200749
AKASHI Takahiro535a7bd2023-10-16 14:39:45 +0900750 pwrdom_scmi: protocol@11 {
751 reg = <0x11>;
752 #power-domain-cells = <1>;
753 };
754
Etienne Carriere09665cb2022-02-21 09:22:39 +0100755 clk_scmi: protocol@14 {
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200756 reg = <0x14>;
757 #clock-cells = <1>;
AKASHI Takahirocc4ecda2023-10-11 19:06:59 +0900758 linaro,sandbox-channel-id = <0x14>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200759 };
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200760
Etienne Carriere09665cb2022-02-21 09:22:39 +0100761 reset_scmi: protocol@16 {
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200762 reg = <0x16>;
763 #reset-cells = <1>;
764 };
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100765
766 protocol@17 {
767 reg = <0x17>;
768
769 regulators {
770 #address-cells = <1>;
771 #size-cells = <0>;
772
Etienne Carriere09665cb2022-02-21 09:22:39 +0100773 regul0_scmi: reg@0 {
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100774 reg = <0>;
775 regulator-name = "sandbox-voltd0";
776 regulator-min-microvolt = <1100000>;
777 regulator-max-microvolt = <3300000>;
778 };
Etienne Carriere09665cb2022-02-21 09:22:39 +0100779 regul1_scmi: reg@1 {
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100780 reg = <0x1>;
781 regulator-name = "sandbox-voltd1";
782 regulator-min-microvolt = <1800000>;
783 };
784 };
785 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200786 };
Alexey Romanov9dc617d2023-09-21 11:13:36 +0300787
788 sm: secure-monitor {
789 compatible = "sandbox,sm";
790 };
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700791 };
792
Alexander Dahl6ac319d2022-09-30 14:04:30 +0200793 fpga {
794 compatible = "sandbox,fpga";
795 };
796
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100797 pinctrl-gpio {
798 compatible = "sandbox,pinctrl-gpio";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700799
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100800 gpio_a: base-gpios {
801 compatible = "sandbox,gpio";
802 gpio-controller;
803 #gpio-cells = <1>;
804 gpio-bank-name = "a";
805 sandbox,gpio-count = <20>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200806 hog_input_active_low {
807 gpio-hog;
808 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200809 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200810 };
811 hog_input_active_high {
812 gpio-hog;
813 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200814 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200815 };
816 hog_output_low {
817 gpio-hog;
818 output-low;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200819 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200820 };
821 hog_output_high {
822 gpio-hog;
823 output-high;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200824 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200825 };
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100826 };
827
828 gpio_b: extra-gpios {
829 compatible = "sandbox,gpio";
830 gpio-controller;
831 #gpio-cells = <5>;
832 gpio-bank-name = "b";
833 sandbox,gpio-count = <10>;
834 };
Simon Glass25348a42014-10-13 23:42:11 -0600835
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100836 gpio_c: pinmux-gpios {
837 compatible = "sandbox,gpio";
838 gpio-controller;
839 #gpio-cells = <2>;
840 gpio-bank-name = "c";
841 sandbox,gpio-count = <10>;
842 };
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100843 };
844
Simon Glass7df766e2014-12-10 08:55:55 -0700845 i2c@0 {
846 #address-cells = <1>;
847 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600848 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700849 compatible = "sandbox,i2c";
850 clock-frequency = <100000>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200851 pinctrl-names = "default";
852 pinctrl-0 = <&pinmux_i2c0_pins>;
853
Simon Glass7df766e2014-12-10 08:55:55 -0700854 eeprom@2c {
Sean Andersone2dc0e62022-05-05 13:11:42 -0400855 #address-cells = <1>;
856 #size-cells = <1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700857 reg = <0x2c>;
858 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700859 sandbox,emul = <&emul_eeprom>;
Michal Simek4f18f922020-05-28 11:48:55 +0200860 partitions {
861 compatible = "fixed-partitions";
862 #address-cells = <1>;
863 #size-cells = <1>;
864 bootcount_i2c: bootcount@10 {
865 reg = <10 2>;
866 };
867 };
Sean Andersone2dc0e62022-05-05 13:11:42 -0400868
869 eth3_addr: mac-address@24 {
870 reg = <24 6>;
871 };
Simon Glass7df766e2014-12-10 08:55:55 -0700872 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200873
Simon Glass336b2952015-05-22 15:42:17 -0600874 rtc_0: rtc@43 {
Sean Anderson5768e8b2022-05-05 13:11:43 -0400875 #address-cells = <1>;
876 #size-cells = <1>;
Simon Glass336b2952015-05-22 15:42:17 -0600877 reg = <0x43>;
878 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700879 sandbox,emul = <&emul0>;
Sean Anderson5768e8b2022-05-05 13:11:43 -0400880
881 eth4_addr: mac-address@40 {
882 reg = <0x40 6>;
883 };
Simon Glass336b2952015-05-22 15:42:17 -0600884 };
885
886 rtc_1: rtc@61 {
887 reg = <0x61>;
888 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700889 sandbox,emul = <&emul1>;
890 };
891
892 i2c_emul: emul {
893 reg = <0xff>;
894 compatible = "sandbox,i2c-emul-parent";
895 emul_eeprom: emul-eeprom {
896 compatible = "sandbox,i2c-eeprom";
897 sandbox,filename = "i2c.bin";
898 sandbox,size = <256>;
899 };
900 emul0: emul0 {
Simon Glass98af3742021-02-03 06:01:17 -0700901 compatible = "sandbox,i2c-rtc-emul";
Simon Glass17b56f62018-11-18 08:14:34 -0700902 };
903 emul1: emull {
Simon Glass98af3742021-02-03 06:01:17 -0700904 compatible = "sandbox,i2c-rtc-emul";
Simon Glass336b2952015-05-22 15:42:17 -0600905 };
906 };
907
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200908 sandbox_pmic: sandbox_pmic {
909 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700910 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200911 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200912
913 mc34708: pmic@41 {
914 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700915 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200916 };
Simon Glass7df766e2014-12-10 08:55:55 -0700917 };
918
Philipp Tomsich1fc53302018-12-14 21:14:29 +0100919 bootcount@0 {
920 compatible = "u-boot,bootcount-rtc";
921 rtc = <&rtc_1>;
922 offset = <0x13>;
923 };
924
Michal Simek4f18f922020-05-28 11:48:55 +0200925 bootcount {
926 compatible = "u-boot,bootcount-i2c-eeprom";
927 i2c-eeprom = <&bootcount_i2c>;
928 };
929
Nandor Han88895812021-06-10 15:40:38 +0300930 bootcount_4@0 {
931 compatible = "u-boot,bootcount-syscon";
932 syscon = <&syscon0>;
933 reg = <0x0 0x04>, <0x0 0x04>;
934 reg-names = "syscon_reg", "offset";
935 };
936
937 bootcount_2@0 {
938 compatible = "u-boot,bootcount-syscon";
939 syscon = <&syscon0>;
940 reg = <0x0 0x04>, <0x0 0x02> ;
941 reg-names = "syscon_reg", "offset";
942 };
943
Marek Szyprowskiad398592021-02-18 11:33:18 +0100944 adc: adc@0 {
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100945 compatible = "sandbox,adc";
Marek Szyprowskiad398592021-02-18 11:33:18 +0100946 #io-channel-cells = <1>;
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100947 vdd-supply = <&buck2>;
948 vss-microvolts = <0>;
949 };
950
Mark Kettenis67748ee2021-10-23 16:58:02 +0200951 iommu: iommu@0 {
952 compatible = "sandbox,iommu";
953 #iommu-cells = <0>;
954 };
955
Simon Glass515dcff2020-02-06 09:55:00 -0700956 irq: irq {
Simon Glass54028bc2019-12-06 21:41:59 -0700957 compatible = "sandbox,irq";
Simon Glass515dcff2020-02-06 09:55:00 -0700958 interrupt-controller;
959 #interrupt-cells = <2>;
Simon Glass54028bc2019-12-06 21:41:59 -0700960 };
961
Simon Glass90b6fef2016-01-18 19:52:26 -0700962 lcd {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700963 bootph-all;
Simon Glass90b6fef2016-01-18 19:52:26 -0700964 compatible = "sandbox,lcd-sdl";
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200965 pinctrl-names = "default";
966 pinctrl-0 = <&pinmux_lcd_pins>;
Simon Glass90b6fef2016-01-18 19:52:26 -0700967 xres = <1366>;
968 yres = <768>;
969 };
970
Simon Glassd783eb32015-07-06 12:54:34 -0600971 leds {
972 compatible = "gpio-leds";
973
974 iracibble {
975 gpios = <&gpio_a 1 0>;
976 label = "sandbox:red";
977 };
978
979 martinet {
980 gpios = <&gpio_a 2 0>;
981 label = "sandbox:green";
982 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200983
984 default_on {
985 gpios = <&gpio_a 5 0>;
986 label = "sandbox:default_on";
987 default-state = "on";
988 };
989
990 default_off {
991 gpios = <&gpio_a 6 0>;
Sean Andersonfbf8d652020-09-14 11:02:03 -0400992 /* label intentionally omitted */
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200993 default-state = "off";
994 };
Simon Glassd783eb32015-07-06 12:54:34 -0600995 };
996
Paul Doelle709f0372022-07-04 09:00:25 +0000997 wdt-gpio-toggle {
Simon Glasse0f8cd22023-08-10 09:53:13 -0600998 gpios = <&gpio_a 8 0>;
Rasmus Villemoes2b673872021-08-19 11:57:05 +0200999 compatible = "linux,wdt-gpio";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +02001000 hw_margin_ms = <100>;
Paul Doelle709f0372022-07-04 09:00:25 +00001001 hw_algo = "toggle";
1002 always-running;
1003 };
1004
1005 wdt-gpio-level {
1006 gpios = <&gpio_a 7 0>;
1007 compatible = "linux,wdt-gpio";
1008 hw_margin_ms = <100>;
1009 hw_algo = "level";
Rasmus Villemoes2b673872021-08-19 11:57:05 +02001010 always-running;
1011 };
1012
Stephen Warren62f2c902016-05-16 17:41:37 -06001013 mbox: mbox {
1014 compatible = "sandbox,mbox";
1015 #mbox-cells = <1>;
1016 };
1017
1018 mbox-test {
1019 compatible = "sandbox,mbox-test";
1020 mboxes = <&mbox 100>, <&mbox 1>;
1021 mbox-names = "other", "test";
1022 };
1023
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001024 cpus {
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +02001025 #address-cells = <1>;
1026 #size-cells = <0>;
Sean Anderson79d3bba2020-09-28 10:52:23 -04001027 timebase-frequency = <2000000>;
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +02001028 cpu1: cpu@1 {
1029 device_type = "cpu";
1030 reg = <0x1>;
Sean Anderson79d3bba2020-09-28 10:52:23 -04001031 timebase-frequency = <3000000>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001032 compatible = "sandbox,cpu_sandbox";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001033 bootph-all;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001034 };
Mario Sixdea5df72018-08-06 10:23:44 +02001035
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +02001036 cpu2: cpu@2 {
1037 device_type = "cpu";
1038 reg = <0x2>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001039 compatible = "sandbox,cpu_sandbox";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001040 bootph-all;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001041 };
Mario Sixdea5df72018-08-06 10:23:44 +02001042
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +02001043 cpu3: cpu@3 {
1044 device_type = "cpu";
1045 reg = <0x3>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001046 compatible = "sandbox,cpu_sandbox";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001047 bootph-all;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001048 };
Mario Sixdea5df72018-08-06 10:23:44 +02001049 };
1050
Dave Gerlach75dbdfc2020-07-15 23:39:58 -05001051 chipid: chipid {
1052 compatible = "sandbox,soc";
1053 };
1054
Simon Glassc953aaf2018-12-10 10:37:34 -07001055 i2s: i2s {
1056 compatible = "sandbox,i2s";
1057 #sound-dai-cells = <1>;
Simon Glass4d5814c2019-02-16 20:24:56 -07001058 sandbox,silent; /* Don't emit sounds while testing */
Simon Glassc953aaf2018-12-10 10:37:34 -07001059 };
1060
Jean-Jacques Hiblotdb97c7f2019-07-05 09:33:57 +02001061 nop-test_0 {
1062 compatible = "sandbox,nop_sandbox1";
1063 nop-test_1 {
1064 compatible = "sandbox,nop_sandbox2";
1065 bind = "True";
1066 };
1067 nop-test_2 {
1068 compatible = "sandbox,nop_sandbox2";
1069 bind = "False";
1070 };
1071 };
1072
Roger Quadrosb0679a72022-10-20 16:30:46 +03001073 memory-controller {
1074 compatible = "sandbox,memory";
1075 };
1076
Mario Sixa8ce0ee2018-07-31 14:24:14 +02001077 misc-test {
Sean Anderson13652b82022-05-05 13:11:44 -04001078 #address-cells = <1>;
1079 #size-cells = <1>;
Mario Sixa8ce0ee2018-07-31 14:24:14 +02001080 compatible = "sandbox,misc_sandbox";
Sean Anderson13652b82022-05-05 13:11:44 -04001081
1082 eth5_addr: mac-address@10 {
1083 reg = <0x10 6>;
1084 };
Mario Sixa8ce0ee2018-07-31 14:24:14 +02001085 };
1086
Simon Glasse4fef742017-04-23 20:02:07 -06001087 mmc2 {
1088 compatible = "sandbox,mmc";
Simon Glass965cd402021-07-05 16:32:58 -06001089 non-removable;
Simon Glasse4fef742017-04-23 20:02:07 -06001090 };
1091
Simon Glassb255efc2022-04-24 23:31:24 -06001092 /* This is used for the bootdev tests */
Simon Glasse4fef742017-04-23 20:02:07 -06001093 mmc1 {
1094 compatible = "sandbox,mmc";
Simon Glassb255efc2022-04-24 23:31:24 -06001095 filename = "mmc1.img";
Simon Glasse4fef742017-04-23 20:02:07 -06001096 };
1097
Simon Glassb255efc2022-04-24 23:31:24 -06001098 /* This is used for the fastboot tests */
Sughosh Ganu77079e72022-10-21 18:16:05 +05301099 mmc0: mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -06001100 compatible = "sandbox,mmc";
1101 };
1102
Simon Glassf1eba352022-10-20 18:23:20 -06001103 /* This is used for VBE VPL tests */
1104 mmc3 {
1105 status = "disabled";
1106 compatible = "sandbox,mmc";
1107 filename = "image.bin";
1108 non-removable;
1109 };
1110
Simon Glassd2bc33ed2023-01-06 08:52:41 -06001111 /* This is used for bootstd bootmenu tests */
1112 mmc4 {
1113 status = "disabled";
1114 compatible = "sandbox,mmc";
1115 filename = "mmc4.img";
1116 };
1117
Simon Glassfff928c2023-08-24 13:55:41 -06001118 /* This is used for ChromiumOS tests */
1119 mmc5 {
1120 status = "disabled";
1121 compatible = "sandbox,mmc";
1122 filename = "mmc5.img";
1123 };
1124
Alexander Gendin038cb022023-10-09 01:24:36 +00001125 /* This is used for mbr tests */
1126 mmc6 {
1127 status = "disabled";
1128 compatible = "sandbox,mmc";
1129 filename = "mmc6.img";
1130 };
1131
Simon Glass53a68b32019-02-16 20:24:50 -07001132 pch {
1133 compatible = "sandbox,pch";
1134 };
1135
Tom Rini4a3ca482020-02-11 12:41:23 -05001136 pci0: pci@0 {
Simon Glass3a6eae62015-03-05 12:25:34 -07001137 compatible = "sandbox,pci";
1138 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001139 bus-range = <0x00 0xff>;
Simon Glass3a6eae62015-03-05 12:25:34 -07001140 #address-cells = <3>;
1141 #size-cells = <2>;
Simon Glass35464f72019-09-25 08:56:08 -06001142 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glass3a6eae62015-03-05 12:25:34 -07001143 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Mark Kettenis5dfd4ec2023-01-21 20:27:57 +01001144 iommu-map = <0x0010 &iommu 0 1>;
1145 iommu-map-mask = <0xfffffff8>;
Bin Mengcbf071b2018-08-03 01:14:39 -07001146 pci@0,0 {
1147 compatible = "pci-generic";
1148 reg = <0x0000 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001149 sandbox,emul = <&swap_case_emul0_0>;
Bin Mengcbf071b2018-08-03 01:14:39 -07001150 };
Alex Margineanf1274432019-06-07 11:24:24 +03001151 pci@1,0 {
1152 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -06001153 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
Simon Glass4289c262023-09-26 08:14:58 -06001154 reg = <0x02000814 0 0 0x80 0
1155 0x01000810 0 0 0xc0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001156 sandbox,emul = <&swap_case_emul0_1>;
Alex Margineanf1274432019-06-07 11:24:24 +03001157 };
Simon Glass937bb472019-12-06 21:41:57 -07001158 p2sb-pci@2,0 {
1159 compatible = "sandbox,p2sb";
1160 reg = <0x02001010 0 0 0 0>;
1161 sandbox,emul = <&p2sb_emul>;
1162
1163 adder {
1164 intel,p2sb-port-id = <3>;
1165 compatible = "sandbox,adder";
1166 };
1167 };
Simon Glass8c501022019-12-06 21:41:54 -07001168 pci@1e,0 {
1169 compatible = "sandbox,pmc";
1170 reg = <0xf000 0 0 0 0>;
1171 sandbox,emul = <&pmc_emul1e>;
1172 acpi-base = <0x400>;
1173 gpe0-dwx-mask = <0xf>;
1174 gpe0-dwx-shift-base = <4>;
1175 gpe0-dw = <6 7 9>;
1176 gpe0-sts = <0x20>;
1177 gpe0-en = <0x30>;
1178 };
Simon Glass3a6eae62015-03-05 12:25:34 -07001179 pci@1f,0 {
1180 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -06001181 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
Simon Glass4289c262023-09-26 08:14:58 -06001182 reg = <0x0100f810 0 0 0x100 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001183 sandbox,emul = <&swap_case_emul0_1f>;
Simon Glass3a6eae62015-03-05 12:25:34 -07001184 };
1185 };
1186
Simon Glassb98ba4c2019-09-25 08:56:10 -06001187 pci-emul0 {
1188 compatible = "sandbox,pci-emul-parent";
1189 swap_case_emul0_0: emul0@0,0 {
1190 compatible = "sandbox,swap-case";
1191 };
1192 swap_case_emul0_1: emul0@1,0 {
1193 compatible = "sandbox,swap-case";
1194 use-ea;
1195 };
1196 swap_case_emul0_1f: emul0@1f,0 {
1197 compatible = "sandbox,swap-case";
1198 };
Simon Glass937bb472019-12-06 21:41:57 -07001199 p2sb_emul: emul@2,0 {
1200 compatible = "sandbox,p2sb-emul";
1201 };
Simon Glass8c501022019-12-06 21:41:54 -07001202 pmc_emul1e: emul@1e,0 {
1203 compatible = "sandbox,pmc-emul";
1204 };
Simon Glassb98ba4c2019-09-25 08:56:10 -06001205 };
1206
Tom Rini4a3ca482020-02-11 12:41:23 -05001207 pci1: pci@1 {
Bin Meng408e5902018-08-03 01:14:41 -07001208 compatible = "sandbox,pci";
1209 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001210 bus-range = <0x00 0xff>;
Bin Meng408e5902018-08-03 01:14:41 -07001211 #address-cells = <3>;
1212 #size-cells = <2>;
Suneel Garapati3ac3aec2019-10-19 17:10:20 -07001213 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
Andrew Scullc7456a42022-04-21 16:11:09 +00001214 0x02000000 0 0x31000000 0x3e000000 0 0x2000 // MEM1
Suneel Garapati3ac3aec2019-10-19 17:10:20 -07001215 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -07001216 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +02001217 0x0c 0x00 0x1234 0x5678
1218 0x10 0x00 0x1234 0x5678>;
1219 pci@10,0 {
1220 reg = <0x8000 0 0 0 0>;
1221 };
Bin Meng408e5902018-08-03 01:14:41 -07001222 };
1223
Tom Rini4a3ca482020-02-11 12:41:23 -05001224 pci2: pci@2 {
Bin Meng510dddb2018-08-03 01:14:50 -07001225 compatible = "sandbox,pci";
1226 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001227 bus-range = <0x00 0xff>;
Bin Meng510dddb2018-08-03 01:14:50 -07001228 #address-cells = <3>;
1229 #size-cells = <2>;
1230 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
1231 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
1232 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
1233 pci@1f,0 {
1234 compatible = "pci-generic";
1235 reg = <0xf800 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001236 sandbox,emul = <&swap_case_emul2_1f>;
1237 };
1238 };
1239
1240 pci-emul2 {
1241 compatible = "sandbox,pci-emul-parent";
1242 swap_case_emul2_1f: emul2@1f,0 {
1243 compatible = "sandbox,swap-case";
Bin Meng510dddb2018-08-03 01:14:50 -07001244 };
1245 };
1246
Ramon Friedc64f19b2019-04-27 11:15:23 +03001247 pci_ep: pci_ep {
1248 compatible = "sandbox,pci_ep";
1249 };
1250
Simon Glass9c433fe2017-04-23 20:10:44 -06001251 probing {
1252 compatible = "simple-bus";
1253 test1 {
1254 compatible = "denx,u-boot-probe-test";
1255 };
1256
1257 test2 {
1258 compatible = "denx,u-boot-probe-test";
1259 };
1260
1261 test3 {
1262 compatible = "denx,u-boot-probe-test";
1263 };
1264
1265 test4 {
1266 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001267 first-syscon = <&syscon0>;
1268 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunayee010432019-03-07 09:57:13 +01001269 third-syscon = <&syscon2>;
Simon Glass9c433fe2017-04-23 20:10:44 -06001270 };
1271 };
1272
Stephen Warren92c67fa2016-07-13 13:45:31 -06001273 pwrdom: power-domain {
1274 compatible = "sandbox,power-domain";
1275 #power-domain-cells = <1>;
1276 };
1277
1278 power-domain-test {
1279 compatible = "sandbox,power-domain-test";
1280 power-domains = <&pwrdom 2>;
1281 };
1282
Simon Glass5620cf82018-10-01 12:22:40 -06001283 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -06001284 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001285 #pwm-cells = <2>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001286 pinctrl-names = "default";
1287 pinctrl-0 = <&pinmux_pwm_pins>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001288 };
1289
1290 pwm2 {
1291 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001292 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001293 };
1294
Simon Glass3d355e62015-07-06 12:54:31 -06001295 ram {
1296 compatible = "sandbox,ram";
1297 };
1298
Simon Glassd860f222015-07-06 12:54:29 -06001299 reset@0 {
1300 compatible = "sandbox,warm-reset";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001301 bootph-some-ram;
Simon Glassd860f222015-07-06 12:54:29 -06001302 };
1303
1304 reset@1 {
1305 compatible = "sandbox,reset";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001306 bootph-some-ram;
Simon Glassd860f222015-07-06 12:54:29 -06001307 };
1308
Stephen Warren6488e642016-06-17 09:43:59 -06001309 resetc: reset-ctl {
1310 compatible = "sandbox,reset-ctl";
1311 #reset-cells = <1>;
1312 };
1313
1314 reset-ctl-test {
1315 compatible = "sandbox,reset-ctl-test";
Neil Armstrong9b4cdef2021-04-20 10:42:25 +02001316 resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>;
1317 reset-names = "other", "test", "test2", "test3";
Stephen Warren6488e642016-06-17 09:43:59 -06001318 };
1319
Sughosh Ganu23e37512019-12-28 23:58:31 +05301320 rng {
1321 compatible = "sandbox,sandbox-rng";
1322 };
1323
Nishanth Menonedf85812015-09-17 15:42:41 -05001324 rproc_1: rproc@1 {
1325 compatible = "sandbox,test-processor";
1326 remoteproc-name = "remoteproc-test-dev1";
1327 };
1328
1329 rproc_2: rproc@2 {
1330 compatible = "sandbox,test-processor";
1331 internal-memory-mapped;
1332 remoteproc-name = "remoteproc-test-dev2";
1333 };
1334
Simon Glass5620cf82018-10-01 12:22:40 -06001335 panel {
1336 compatible = "simple-panel";
1337 backlight = <&backlight 0 100>;
1338 };
1339
Simon Glass509f32e2022-09-21 16:21:47 +02001340 scsi {
1341 compatible = "sandbox,scsi";
1342 sandbox,filepath = "scsi.img";
1343 };
1344
Ramon Fried26ed32e2018-07-02 02:57:59 +03001345 smem@0 {
1346 compatible = "sandbox,smem";
1347 };
1348
Simon Glass76072ac2018-12-10 10:37:36 -07001349 sound {
1350 compatible = "sandbox,sound";
1351 cpu {
1352 sound-dai = <&i2s 0>;
1353 };
1354
1355 codec {
1356 sound-dai = <&audio 0>;
1357 };
1358 };
1359
Simon Glass25348a42014-10-13 23:42:11 -06001360 spi@0 {
1361 #address-cells = <1>;
1362 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -06001363 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -06001364 compatible = "sandbox,spi";
Ovidiu Panaitae734732020-12-14 19:06:47 +02001365 cs-gpios = <0>, <0>, <&gpio_a 0>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001366 pinctrl-names = "default";
1367 pinctrl-0 = <&pinmux_spi0_pins>;
1368
Simon Glass25348a42014-10-13 23:42:11 -06001369 spi.bin@0 {
1370 reg = <0>;
Neil Armstronga009fa72019-02-10 10:16:20 +00001371 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass25348a42014-10-13 23:42:11 -06001372 spi-max-frequency = <40000000>;
1373 sandbox,filename = "spi.bin";
1374 };
Ovidiu Panaitae734732020-12-14 19:06:47 +02001375 spi.bin@1 {
1376 reg = <1>;
1377 compatible = "spansion,m25p16", "jedec,spi-nor";
1378 spi-max-frequency = <50000000>;
1379 sandbox,filename = "spi.bin";
1380 spi-cpol;
1381 spi-cpha;
1382 };
Simon Glass25348a42014-10-13 23:42:11 -06001383 };
1384
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001385 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -06001386 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +02001387 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -06001388 };
1389
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001390 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -06001391 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -06001392 reg = <0x20 5
1393 0x28 6
1394 0x30 7
1395 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -06001396 };
1397
Patrick Delaunayee010432019-03-07 09:57:13 +01001398 syscon2: syscon@2 {
Masahiro Yamada42ab1072018-04-23 13:26:53 +09001399 compatible = "simple-mfd", "syscon";
1400 reg = <0x40 5
1401 0x48 6
1402 0x50 7
1403 0x58 8>;
1404 };
1405
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +05301406 syscon3: syscon@3 {
1407 compatible = "simple-mfd", "syscon";
1408 reg = <0x000100 0x10>;
1409
1410 muxcontroller0: a-mux-controller {
1411 compatible = "mmio-mux";
1412 #mux-control-cells = <1>;
1413
1414 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
1415 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
1416 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
1417 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
1418 u-boot,mux-autoprobe;
1419 };
1420 };
1421
1422 muxcontroller1: emul-mux-controller {
1423 compatible = "mux-emul";
1424 #mux-control-cells = <0>;
1425 u-boot,mux-autoprobe;
1426 idle-state = <0xabcd>;
1427 };
1428
Simon Glass791a17f2020-12-16 21:20:27 -07001429 testfdtm0 {
1430 compatible = "denx,u-boot-fdtm-test";
1431 };
1432
1433 testfdtm1: testfdtm1 {
1434 compatible = "denx,u-boot-fdtm-test";
1435 };
1436
1437 testfdtm2 {
1438 compatible = "denx,u-boot-fdtm-test";
1439 };
1440
Sean Anderson79d3bba2020-09-28 10:52:23 -04001441 timer@0 {
Thomas Chou6f2cfbf2015-12-11 16:27:34 +08001442 compatible = "sandbox,timer";
1443 clock-frequency = <1000000>;
1444 };
1445
Sean Anderson79d3bba2020-09-28 10:52:23 -04001446 timer@1 {
1447 compatible = "sandbox,timer";
1448 sandbox,timebase-frequency-fallback;
1449 };
1450
Miquel Raynal80938c12018-05-15 11:57:27 +02001451 tpm2 {
1452 compatible = "sandbox,tpm2";
Eddie James1a55a7a2023-10-24 10:43:51 -05001453 memory-region = <&event_log>;
Miquel Raynal80938c12018-05-15 11:57:27 +02001454 };
1455
Simon Glasseef107e2023-02-21 06:24:51 -07001456 tpm {
1457 compatible = "google,sandbox-tpm";
1458 };
1459
Simon Glass5b968632015-05-22 15:42:15 -06001460 uart0: serial {
1461 compatible = "sandbox,serial";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001462 bootph-all;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001463 pinctrl-names = "default";
1464 pinctrl-0 = <&pinmux_uart0_pins>;
Joe Hershberger4c197242015-03-22 17:09:15 -05001465 };
1466
Simon Glass31680482015-03-25 12:23:05 -06001467 usb_0: usb@0 {
1468 compatible = "sandbox,usb";
1469 status = "disabled";
1470 hub {
1471 compatible = "sandbox,usb-hub";
1472 #address-cells = <1>;
1473 #size-cells = <0>;
1474 flash-stick {
1475 reg = <0>;
1476 compatible = "sandbox,usb-flash";
1477 };
1478 };
1479 };
1480
1481 usb_1: usb@1 {
1482 compatible = "sandbox,usb";
Mark Kettenis67748ee2021-10-23 16:58:02 +02001483 iommus = <&iommu>;
Simon Glass31680482015-03-25 12:23:05 -06001484 hub {
1485 compatible = "usb-hub";
1486 usb,device-class = <9>;
Michael Walle7c961322020-06-02 01:47:07 +02001487 #address-cells = <1>;
1488 #size-cells = <0>;
Simon Glass31680482015-03-25 12:23:05 -06001489 hub-emul {
1490 compatible = "sandbox,usb-hub";
1491 #address-cells = <1>;
1492 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -07001493 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -06001494 reg = <0>;
1495 compatible = "sandbox,usb-flash";
1496 sandbox,filepath = "testflash.bin";
1497 };
1498
Simon Glass4700fe52015-11-08 23:48:01 -07001499 flash-stick@1 {
1500 reg = <1>;
1501 compatible = "sandbox,usb-flash";
1502 sandbox,filepath = "testflash1.bin";
1503 };
1504
1505 flash-stick@2 {
1506 reg = <2>;
1507 compatible = "sandbox,usb-flash";
1508 sandbox,filepath = "testflash2.bin";
1509 };
1510
Simon Glassc0ccc722015-11-08 23:48:08 -07001511 keyb@3 {
1512 reg = <3>;
1513 compatible = "sandbox,usb-keyb";
1514 };
1515
Simon Glass31680482015-03-25 12:23:05 -06001516 };
Michael Walle7c961322020-06-02 01:47:07 +02001517
1518 usbstor@1 {
1519 reg = <1>;
1520 };
1521 usbstor@3 {
1522 reg = <3>;
1523 };
Simon Glass31680482015-03-25 12:23:05 -06001524 };
1525 };
1526
1527 usb_2: usb@2 {
1528 compatible = "sandbox,usb";
1529 status = "disabled";
1530 };
1531
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001532 spmi: spmi@0 {
1533 compatible = "sandbox,spmi";
1534 #address-cells = <0x1>;
1535 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001536 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001537 pm8916@0 {
1538 compatible = "qcom,spmi-pmic";
1539 reg = <0x0 0x1>;
1540 #address-cells = <0x1>;
1541 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001542 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001543
1544 spmi_gpios: gpios@c000 {
1545 compatible = "qcom,pm8916-gpio";
1546 reg = <0xc000 0x400>;
Caleb Connolly1edc45f2024-01-08 15:30:51 +00001547 gpio-ranges = <&spmi_gpios 0 0 4>;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001548 gpio-controller;
1549 gpio-count = <4>;
1550 #gpio-cells = <2>;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001551 };
1552 };
1553 };
maxims@google.comdaea6d42017-04-17 12:00:21 -07001554
1555 wdt0: wdt@0 {
1556 compatible = "sandbox,wdt";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +02001557 hw_margin_ms = <200>;
maxims@google.comdaea6d42017-04-17 12:00:21 -07001558 };
Rob Clarka471b672018-01-10 11:33:30 +01001559
Mario Six95922152018-08-09 14:51:19 +02001560 axi: axi@0 {
1561 compatible = "sandbox,axi";
1562 #address-cells = <0x1>;
1563 #size-cells = <0x1>;
1564 store@0 {
1565 compatible = "sandbox,sandbox_store";
1566 reg = <0x0 0x400>;
1567 };
1568 };
1569
Rob Clarka471b672018-01-10 11:33:30 +01001570 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -07001571 #address-cells = <1>;
1572 #size-cells = <1>;
Simon Glassf3455962020-01-27 08:49:43 -07001573 setting = "sunrise ohoka";
1574 other-node = "/some-bus/c-test@5";
Simon Glasse09223c2020-01-27 08:49:46 -07001575 int-values = <0x1937 72993>;
Simon Glass3c601b12020-07-07 13:12:06 -06001576 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Algapally Santosh Sagardf178992023-09-21 16:50:43 +05301577 stdout-path = "serial0:115200n8";
Rob Clarka471b672018-01-10 11:33:30 +01001578 chosen-test {
1579 compatible = "denx,u-boot-fdt-test";
1580 reg = <9 1>;
1581 };
1582 };
Mario Six35616ef2018-03-12 14:53:33 +01001583
1584 translation-test@8000 {
1585 compatible = "simple-bus";
1586 reg = <0x8000 0x4000>;
1587
1588 #address-cells = <0x2>;
1589 #size-cells = <0x1>;
1590
1591 ranges = <0 0x0 0x8000 0x1000
1592 1 0x100 0x9000 0x1000
1593 2 0x200 0xA000 0x1000
1594 3 0x300 0xB000 0x1000
1595 >;
1596
Fabien Dessenne22236e02019-05-31 15:11:30 +02001597 dma-ranges = <0 0x000 0x10000000 0x1000
1598 1 0x100 0x20000000 0x1000
1599 >;
1600
Mario Six35616ef2018-03-12 14:53:33 +01001601 dev@0,0 {
1602 compatible = "denx,u-boot-fdt-dummy";
1603 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojasa3181152018-12-03 19:37:09 +01001604 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +01001605 };
1606
1607 dev@1,100 {
1608 compatible = "denx,u-boot-fdt-dummy";
1609 reg = <1 0x100 0x1000>;
1610
1611 };
1612
1613 dev@2,200 {
1614 compatible = "denx,u-boot-fdt-dummy";
1615 reg = <2 0x200 0x1000>;
1616 };
1617
1618
1619 noxlatebus@3,300 {
1620 compatible = "simple-bus";
1621 reg = <3 0x300 0x1000>;
1622
1623 #address-cells = <0x1>;
1624 #size-cells = <0x0>;
1625
1626 dev@42 {
1627 compatible = "denx,u-boot-fdt-dummy";
1628 reg = <0x42>;
1629 };
1630 };
1631 };
Mario Six02ad6fb2018-09-27 09:19:31 +02001632
Dzmitry Sankouski54f4c832023-01-22 18:21:23 +03001633 ofnode-foreach {
1634 compatible = "foreach";
1635
1636 first {
1637 prop1 = <1>;
1638 prop2 = <2>;
1639 };
1640
1641 second {
1642 prop1 = <1>;
1643 prop2 = <2>;
1644 };
1645 };
1646
Mario Six02ad6fb2018-09-27 09:19:31 +02001647 osd {
1648 compatible = "sandbox,sandbox_osd";
1649 };
Tom Rinib93eea72018-09-30 18:16:51 -04001650
Jens Wiklander86afaa62018-09-25 16:40:16 +02001651 sandbox_tee {
1652 compatible = "sandbox,tee";
1653 };
Bin Meng1bb290d2018-10-15 02:21:26 -07001654
1655 sandbox_virtio1 {
1656 compatible = "sandbox,virtio1";
Simon Glass8de5a542023-01-17 10:47:51 -07001657 virtio-type = <4>; /* rng */
Bin Meng1bb290d2018-10-15 02:21:26 -07001658 };
1659
1660 sandbox_virtio2 {
1661 compatible = "sandbox,virtio2";
1662 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001663
Simon Glass8de5a542023-01-17 10:47:51 -07001664 sandbox-virtio-blk {
1665 compatible = "sandbox,virtio1";
1666 virtio-type = <2>; /* block */
1667 };
1668
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001669 sandbox_scmi {
1670 compatible = "sandbox,scmi-devices";
AKASHI Takahiro535a7bd2023-10-16 14:39:45 +09001671 power-domains = <&pwrdom_scmi 2>;
Etienne Carrierebf1f1322022-02-21 09:22:41 +01001672 clocks = <&clk_scmi 2>, <&clk_scmi 0>;
Etienne Carriere09665cb2022-02-21 09:22:39 +01001673 resets = <&reset_scmi 3>;
1674 regul0-supply = <&regul0_scmi>;
1675 regul1-supply = <&regul1_scmi>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001676 };
1677
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001678 pinctrl {
1679 compatible = "sandbox,pinctrl";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001680
Sean Anderson3438e3b2020-09-14 11:01:57 -04001681 pinctrl-names = "default", "alternate";
1682 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1683 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001684
Sean Anderson3438e3b2020-09-14 11:01:57 -04001685 pinctrl_gpios: gpios {
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001686 gpio0 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001687 pins = "P5";
1688 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001689 bias-pull-up;
1690 input-disable;
1691 };
1692 gpio1 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001693 pins = "P6";
1694 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001695 output-high;
1696 drive-open-drain;
1697 };
1698 gpio2 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001699 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001700 bias-pull-down;
1701 input-enable;
1702 };
1703 gpio3 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001704 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001705 bias-disable;
1706 };
1707 };
Sean Anderson3438e3b2020-09-14 11:01:57 -04001708
1709 pinctrl_i2c: i2c {
1710 groups {
1711 groups = "I2C_UART";
1712 function = "I2C";
1713 };
1714
1715 pins {
1716 pins = "P0", "P1";
1717 drive-open-drain;
1718 };
1719 };
1720
1721 pinctrl_i2s: i2s {
1722 groups = "SPI_I2S";
1723 function = "I2S";
1724 };
1725
1726 pinctrl_spi: spi {
1727 groups = "SPI_I2S";
1728 function = "SPI";
1729
1730 cs {
1731 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1732 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1733 };
1734 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001735 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001736
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001737 pinctrl-single-no-width {
1738 compatible = "pinctrl-single";
1739 reg = <0x0000 0x238>;
1740 #pinctrl-cells = <1>;
1741 pinctrl-single,function-mask = <0x7f>;
1742 };
1743
1744 pinctrl-single-pins {
1745 compatible = "pinctrl-single";
1746 reg = <0x0000 0x238>;
1747 #pinctrl-cells = <1>;
1748 pinctrl-single,register-width = <32>;
1749 pinctrl-single,function-mask = <0x7f>;
1750
1751 pinmux_pwm_pins: pinmux_pwm_pins {
1752 pinctrl-single,pins = < 0x48 0x06 >;
1753 };
1754
1755 pinmux_spi0_pins: pinmux_spi0_pins {
1756 pinctrl-single,pins = <
1757 0x190 0x0c
1758 0x194 0x0c
1759 0x198 0x23
1760 0x19c 0x0c
1761 >;
1762 };
1763
1764 pinmux_uart0_pins: pinmux_uart0_pins {
1765 pinctrl-single,pins = <
1766 0x70 0x30
1767 0x74 0x00
1768 >;
1769 };
1770 };
1771
1772 pinctrl-single-bits {
1773 compatible = "pinctrl-single";
1774 reg = <0x0000 0x50>;
1775 #pinctrl-cells = <2>;
1776 pinctrl-single,bit-per-mux;
1777 pinctrl-single,register-width = <32>;
1778 pinctrl-single,function-mask = <0xf>;
1779
1780 pinmux_i2c0_pins: pinmux_i2c0_pins {
1781 pinctrl-single,bits = <
1782 0x10 0x00002200 0x0000ff00
1783 >;
1784 };
1785
1786 pinmux_lcd_pins: pinmux_lcd_pins {
1787 pinctrl-single,bits = <
1788 0x40 0x22222200 0xffffff00
1789 0x44 0x22222222 0xffffffff
1790 0x48 0x00000022 0x000000ff
1791 0x48 0x02000000 0x0f000000
1792 0x4c 0x02000022 0x0f0000ff
1793 >;
1794 };
1795 };
1796
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001797 hwspinlock@0 {
1798 compatible = "sandbox,hwspinlock";
1799 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +01001800
1801 dma: dma {
1802 compatible = "sandbox,dma";
1803 #dma-cells = <1>;
1804
1805 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1806 dma-names = "m2m", "tx0", "rx0";
1807 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001808
Alex Marginean0649be52019-07-12 10:13:53 +03001809 /*
1810 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1811 * end of the test. If parent mdio is removed first, clean-up of the
1812 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1813 * active at the end of the test. That it turn doesn't allow the mdio
1814 * class to be destroyed, triggering an error.
1815 */
1816 mdio-mux-test {
1817 compatible = "sandbox,mdio-mux";
1818 #address-cells = <1>;
1819 #size-cells = <0>;
1820 mdio-parent-bus = <&mdio>;
1821
1822 mdio-ch-test@0 {
1823 reg = <0>;
1824 };
1825 mdio-ch-test@1 {
1826 reg = <1>;
1827 };
1828 };
1829
1830 mdio: mdio-test {
Alex Marginean0daa53a2019-06-03 19:12:28 +03001831 compatible = "sandbox,mdio";
Marek Behúnf4f1ddc2022-04-07 00:32:57 +02001832 #address-cells = <1>;
1833 #size-cells = <0>;
1834
1835 ethphy1: ethernet-phy@1 {
1836 reg = <1>;
1837 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001838 };
Sean Andersonb7860542020-06-24 06:41:12 -04001839
1840 pm-bus-test {
1841 compatible = "simple-pm-bus";
1842 clocks = <&clk_sandbox 4>;
1843 power-domains = <&pwrdom 1>;
1844 };
Sean Anderson0c1f6bf2020-06-24 06:41:14 -04001845
1846 resetc2: syscon-reset {
1847 compatible = "syscon-reset";
1848 #reset-cells = <1>;
1849 regmap = <&syscon0>;
1850 offset = <1>;
1851 mask = <0x27FFFFFF>;
1852 assert-high = <0>;
1853 };
1854
1855 syscon-reset-test {
1856 compatible = "sandbox,misc_sandbox";
1857 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1858 reset-names = "valid", "no_mask", "out_of_range";
1859 };
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301860
Simon Glass458b66a2020-11-05 06:32:05 -07001861 sysinfo {
1862 compatible = "sandbox,sysinfo-sandbox";
1863 };
1864
Sean Anderson1c830672021-04-20 10:50:58 -04001865 sysinfo-gpio {
1866 compatible = "gpio-sysinfo";
1867 gpios = <&gpio_a 15>, <&gpio_a 16>, <&gpio_a 17>;
1868 revisions = <19>, <5>;
1869 names = "rev_a", "foo";
1870 };
1871
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301872 some_regmapped-bus {
1873 #address-cells = <0x1>;
1874 #size-cells = <0x1>;
1875
1876 ranges = <0x0 0x0 0x10>;
1877 compatible = "simple-bus";
1878
1879 regmap-test_0 {
1880 reg = <0 0x10>;
1881 compatible = "sandbox,regmap_test";
1882 };
1883 };
Robert Marko9cf87122022-09-06 13:30:35 +02001884
1885 thermal {
1886 compatible = "sandbox,thermal";
1887 };
Sughosh Ganu77079e72022-10-21 18:16:05 +05301888
1889 fwu-mdata {
1890 compatible = "u-boot,fwu-mdata-gpt";
1891 fwu-mdata-store = <&mmc0>;
1892 };
Abdellatif El Khlifi6b005872023-04-17 10:11:55 +01001893
1894 nvmxip-qspi1@08000000 {
1895 compatible = "nvmxip,qspi";
1896 reg = <0x08000000 0x00200000>;
1897 lba_shift = <9>;
1898 lba = <4096>;
1899 };
1900
1901 nvmxip-qspi2@08200000 {
1902 compatible = "nvmxip,qspi";
1903 reg = <0x08200000 0x00100000>;
1904 lba_shift = <9>;
1905 lba = <2048>;
1906 };
Svyatoslav Ryhel669f5c82023-04-25 10:57:21 +03001907
1908 extcon {
1909 compatible = "sandbox,extcon";
1910 };
Abdellatif El Khlifi4970d5b2023-08-04 14:33:41 +01001911
1912 arm-ffa-emul {
1913 compatible = "sandbox,arm-ffa-emul";
1914
1915 sandbox-arm-ffa {
1916 compatible = "sandbox,arm-ffa";
1917 };
1918 };
Sean Anderson326422b2023-11-04 16:37:52 -04001919
1920 nand-controller {
1921 #address-cells = <1>;
1922 #size-cells = <0>;
1923 compatible = "sandbox,nand";
1924
1925 nand@0 {
1926 reg = <0>;
1927 nand-ecc-mode = "soft";
1928 sandbox,id = [00 e3];
1929 sandbox,erasesize = <(8 * 1024)>;
1930 sandbox,oobsize = <16>;
1931 sandbox,pagesize = <512>;
1932 sandbox,pages = <0x2000>;
1933 sandbox,err-count = <1>;
1934 sandbox,err-step-size = <512>;
1935 };
1936
1937 /* MT29F64G08AKABA */
1938 nand@1 {
1939 reg = <1>;
1940 nand-ecc-mode = "soft_bch";
1941 sandbox,id = [2C 48 00 26 89 00 00 00];
1942 sandbox,onfi = [
1943 4f 4e 46 49 0e 00 5a 00
1944 ff 01 00 00 00 00 03 00
1945 00 00 00 00 00 00 00 00
1946 00 00 00 00 00 00 00 00
1947 4d 49 43 52 4f 4e 20 20
1948 20 20 20 20 4d 54 32 39
1949 46 36 34 47 30 38 41 4b
1950 41 42 41 43 35 20 20 20
1951 2c 00 00 00 00 00 00 00
1952 00 00 00 00 00 00 00 00
1953 00 10 00 00 e0 00 00 02
1954 00 00 1c 00 80 00 00 00
1955 00 10 00 00 02 23 01 50
1956 00 01 05 01 00 00 04 00
1957 04 01 1e 00 00 00 00 00
1958 00 00 00 00 00 00 00 00
1959 0e 1f 00 1f 00 f4 01 ac
1960 0d 19 00 c8 00 00 00 00
1961 00 00 00 00 00 00 0a 07
1962 19 00 00 00 00 00 00 00
1963 00 00 00 00 01 00 01 00
1964 00 00 04 10 01 81 04 02
1965 02 01 1e 90 00 00 00 00
1966 00 00 00 00 00 00 00 00
1967 00 00 00 00 00 00 00 00
1968 00 00 00 00 00 00 00 00
1969 00 00 00 00 00 00 00 00
1970 00 00 00 00 00 00 00 00
1971 00 00 00 00 00 00 00 00
1972 00 00 00 00 00 00 00 00
1973 00 00 00 00 00 00 00 00
1974 00 00 00 00 00 03 20 7d
1975 ];
1976 sandbox,erasesize = <(512 * 1024)>;
1977 sandbox,oobsize = <224>;
1978 sandbox,pagesize = <4096>;
1979 sandbox,pages = <0x200000>;
1980 sandbox,err-count = <3>;
1981 sandbox,err-step-size = <512>;
1982 };
1983 };
Simon Glassb2c1cac2014-02-26 15:59:21 -07001984};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +02001985
1986#include "sandbox_pmic.dtsi"
Heinrich Schuchardte24fdef2021-02-18 13:01:35 +01001987#include "cros-ec-keyboard.dtsi"
Simon Glass5e135d32022-10-20 18:23:15 -06001988
1989#ifdef CONFIG_SANDBOX_VPL
1990#include "sandbox_vpl.dtsi"
1991#endif
Simon Glass61300722023-06-01 10:23:01 -06001992
1993#include "cedit.dtsi"