Blame - arch/arm/cpu/armv7/ls102xa/Kconfig - filogic/uboot

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York Sun	149eb33	2016-09-26 08:09:27 -0700	[diff] [blame]	1	config ARCH_LS1021A
York Sun	fcd0e74	2016-10-04 14:31:47 -0700	[diff] [blame]	2	bool
Michal Simek	7e7ba3b	2018-07-23 15:55:15 +0200	[diff] [blame]	3	select SYS_FSL_DDR_BE if SYS_FSL_DDR
				4	select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
York Sun	1dc61ca	2016-12-28 08:43:41 -0800	[diff] [blame]	5	select SYS_FSL_ERRATUM_A008378
				6	select SYS_FSL_ERRATUM_A008407
Alison Wang	d6be97b	2019-03-06 14:49:14 +0800	[diff] [blame]	7	select SYS_FSL_ERRATUM_A008850
Ran Wang	373a7b0	2017-09-04 18:46:54 +0800	[diff] [blame]	8	select SYS_FSL_ERRATUM_A008997
Ran Wang	2eb4898	2017-09-04 18:46:55 +0800	[diff] [blame]	9	select SYS_FSL_ERRATUM_A009007
Ran Wang	1509c8a	2017-09-04 18:46:52 +0800	[diff] [blame]	10	select SYS_FSL_ERRATUM_A009008
York Sun	1dc61ca	2016-12-28 08:43:41 -0800	[diff] [blame]	11	select SYS_FSL_ERRATUM_A009663
Ran Wang	d2b711b7	2017-09-04 18:46:53 +0800	[diff] [blame]	12	select SYS_FSL_ERRATUM_A009798
York Sun	1dc61ca	2016-12-28 08:43:41 -0800	[diff] [blame]	13	select SYS_FSL_ERRATUM_A009942
York Sun	149eb33	2016-09-26 08:09:27 -0700	[diff] [blame]	14	select SYS_FSL_ERRATUM_A010315
Ashish Kumar	1123406	2017-08-11 11:09:14 +0530	[diff] [blame]	15	select SYS_FSL_HAS_CCI400
York Sun	d297d39	2016-12-28 08:43:40 -0800	[diff] [blame]	16	select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR
				17	select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR
York Sun	92c36e2	2016-12-28 08:43:30 -0800	[diff] [blame]	18	select SYS_FSL_HAS_SEC
				19	select SYS_FSL_SEC_COMPAT_5
York Sun	fa419942	2016-12-28 08:43:31 -0800	[diff] [blame]	20	select SYS_FSL_SEC_LE
Michal Simek	7e7ba3b	2018-07-23 15:55:15 +0200	[diff] [blame]	21	select SYS_FSL_SRDS_1
				22	select SYS_HAS_SERDES
				23	imply CMD_PCI
Simon Glass	0e5faf0	2017-06-14 21:28:21 -0600	[diff] [blame]	24	imply SCSI
Tuomas Tynkkynen	edf9f62	2017-12-08 15:36:19 +0200	[diff] [blame]	25	imply SCSI_AHCI
York Sun	4de7e93	2016-09-26 08:09:29 -0700	[diff] [blame]	26
York Sun	4dd8c61	2016-10-04 14:31:48 -0700	[diff] [blame]	27	menu "LS102xA architecture"
				28	depends on ARCH_LS1021A
				29
York Sun	4de7e93	2016-09-26 08:09:29 -0700	[diff] [blame]	30	config LS1_DEEP_SLEEP
York Sun	fcd0e74	2016-10-04 14:31:47 -0700	[diff] [blame]	31	bool "Deep sleep"
York Sun	4dd8c61	2016-10-04 14:31:48 -0700	[diff] [blame]	32
York Sun	f188d22	2016-10-04 14:45:01 -0700	[diff] [blame]	33	config MAX_CPUS
				34	int "Maximum number of CPUs permitted for LS102xA"
York Sun	f188d22	2016-10-04 14:45:01 -0700	[diff] [blame]	35	default 2
				36	help
				37	Set this number to the maximum number of possible CPUs in the SoC.
				38	SoCs may have multiple clusters with each cluster may have multiple
				39	ports. If some ports are reserved but higher ports are used for
				40	cores, count the reserved ports. This will allocate enough memory
				41	in spin table to properly handle all cores.
				42
Udit Agarwal	22ec238	2019-11-07 16:11:32 +0000	[diff] [blame]	43	config NXP_ESBC
				44	bool "NXP_ESBC"
York Sun	dfa93a9	2016-12-02 09:31:43 -0800	[diff] [blame]	45	help
				46	Enable Freescale Secure Boot feature. Normally selected
				47	by defconfig. If unsure, do not change.
				48
Ashish Kumar	1123406	2017-08-11 11:09:14 +0530	[diff] [blame]	49	config SYS_CCI400_OFFSET
				50	hex "Offset for CCI400 base"
				51	depends on SYS_FSL_HAS_CCI400
				52	default 0x180000
				53	help
				54	Offset for CCI400 base.
				55	CCI400 base addr = CCSRBAR + CCI400_OFFSET
				56
Alison Wang	d6be97b	2019-03-06 14:49:14 +0800	[diff] [blame]	57	config SYS_FSL_ERRATUM_A008850
				58	bool
				59	help
				60	Workaround for DDR erratum A008850
				61
Ran Wang	373a7b0	2017-09-04 18:46:54 +0800	[diff] [blame]	62	config SYS_FSL_ERRATUM_A008997
				63	bool
				64	help
				65	Workaround for USB PHY erratum A008997
				66
Ran Wang	2eb4898	2017-09-04 18:46:55 +0800	[diff] [blame]	67	config SYS_FSL_ERRATUM_A009007
				68	bool
				69	help
				70	Workaround for USB PHY erratum A009007
				71
Ran Wang	1509c8a	2017-09-04 18:46:52 +0800	[diff] [blame]	72	config SYS_FSL_ERRATUM_A009008
				73	bool
				74	help
				75	Workaround for USB PHY erratum A009008
				76
Ran Wang	d2b711b7	2017-09-04 18:46:53 +0800	[diff] [blame]	77	config SYS_FSL_ERRATUM_A009798
				78	bool
				79	help
				80	Workaround for USB PHY erratum A009798
				81
York Sun	4dd8c61	2016-10-04 14:31:48 -0700	[diff] [blame]	82	config SYS_FSL_ERRATUM_A010315
				83	bool "Workaround for PCIe erratum A010315"
				84
Ashish Kumar	1123406	2017-08-11 11:09:14 +0530	[diff] [blame]	85	config SYS_FSL_HAS_CCI400
				86	bool
				87
York Sun	6b62ef0	2016-10-04 18:01:34 -0700	[diff] [blame]	88	config SYS_FSL_SRDS_1
				89	bool
				90
				91	config SYS_FSL_SRDS_2
				92	bool
				93
				94	config SYS_HAS_SERDES
				95	bool
York Sun	f64fc5c	2016-10-04 18:04:37 -0700	[diff] [blame]	96
York Sun	e7310a3	2016-10-04 14:45:54 -0700	[diff] [blame]	97	config SYS_FSL_IFC_BANK_COUNT
				98	int "Maximum banks of Integrated flash controller"
York Sun	e7310a3	2016-10-04 14:45:54 -0700	[diff] [blame]	99	default 8
				100
York Sun	1dc61ca	2016-12-28 08:43:41 -0800	[diff] [blame]	101	config SYS_FSL_ERRATUM_A008407
				102	bool
				103
York Sun	4dd8c61	2016-10-04 14:31:48 -0700	[diff] [blame]	104	endmenu