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Bin Meng6b697752018-09-26 06:55:06 -07001menu "RISC-V architecture"
Rick Chen64d4ead2017-12-26 13:55:52 +08002 depends on RISCV
3
4config SYS_ARCH
5 default "riscv"
6
7choice
8 prompt "Target select"
9 optional
10
Randolph6c9c5ba2023-09-25 17:24:51 +080011config TARGET_ANDES_AE350
12 bool "Support Andes ae350"
Rick Chen64d4ead2017-12-26 13:55:52 +080013
Kongyang Liuad9c1432024-12-15 13:02:41 +080014config TARGET_BANANAPI_F3
15 bool "Support BananaPi F3 Board"
16
Junhui Liu596a4f62025-01-15 00:46:39 +080017config TARGET_K230_CANMV
18 bool "Support K230 CanMV Board"
19
Thomas Bonnefillefcef2ad2024-11-12 15:57:38 +010020config TARGET_LICHEERV_NANO
21 bool "Support LicheeRV Nano Board"
22
Padmarao Begari4216f342019-05-28 15:47:51 +053023config TARGET_MICROCHIP_ICICLE
24 bool "Support Microchip PolarFire-SoC Icicle Board"
25
Kongyang Liub64fc0e2024-01-28 15:05:25 +080026config TARGET_MILKV_DUO
27 bool "Support Milk-v Duo Board"
28
Samuel Hollandbd6a54c2023-10-31 00:32:12 -050029config TARGET_OPENPITON_RISCV64
30 bool "Support RISC-V cores on OpenPiton SoC"
31
Bin Meng8a8694d2018-09-26 06:55:21 -070032config TARGET_QEMU_VIRT
LekKit94ff33a2024-09-22 13:11:02 +030033 bool "Support QEMU Virt & RVVM Boards"
Ɓukasz Stelmach1b100e52024-03-28 10:58:24 +010034 select BOARD_LATE_INIT
Bin Meng8a8694d2018-09-26 06:55:21 -070035
Bin Menge9ead4a2021-03-17 11:10:58 +080036config TARGET_SIFIVE_UNLEASHED
37 bool "Support SiFive Unleashed Board"
Anup Patel7a167f22019-02-25 08:15:19 +000038
Green Wan2e5da522021-05-27 06:52:13 -070039config TARGET_SIFIVE_UNMATCHED
40 bool "Support SiFive Unmatched Board"
Tom Rini3ef67ae2021-08-26 11:47:59 -040041 select SYS_CACHE_SHIFT_6
Green Wan2e5da522021-05-27 06:52:13 -070042
Samuel Hollandbd6a54c2023-10-31 00:32:12 -050043config TARGET_SIPEED_MAIX
44 bool "Support Sipeed Maix Board"
45 select SYS_CACHE_SHIFT_6
46
Yanhong Wang38678792023-03-29 11:42:20 +080047config TARGET_STARFIVE_VISIONFIVE2
48 bool "Support StarFive VisionFive2 Board"
Heinrich Schuchardt03a885b2023-09-07 13:21:28 +020049 select BOARD_LATE_INIT
Yanhong Wang38678792023-03-29 11:42:20 +080050
Yixun Lan5dfa9012023-07-08 19:24:32 +080051config TARGET_TH1520_LPI4A
52 bool "Support Sipeed's TH1520 Lichee PI 4A Board"
53 select SYS_CACHE_SHIFT_6
54
Michal Simek962c10a2023-11-06 12:56:47 +010055config TARGET_XILINX_MBV
56 bool "Support AMD/Xilinx MicroBlaze V"
57
Chia-Wei Wang1c7ed532024-09-10 17:39:16 +080058config TARGET_ASPEED_AST2700_IBEX
59 bool "Support Ibex RISC-V cores on Aspeed AST2700 SoC"
60
Rick Chen64d4ead2017-12-26 13:55:52 +080061endchoice
62
Trevor Woernerba64b8b2019-05-03 09:40:59 -040063config SYS_ICACHE_OFF
64 bool "Do not enable icache"
Trevor Woernerba64b8b2019-05-03 09:40:59 -040065 help
66 Do not enable instruction cache in U-Boot.
67
Trevor Woerner43ec7e02019-05-03 09:41:00 -040068config SPL_SYS_ICACHE_OFF
69 bool "Do not enable icache in SPL"
70 depends on SPL
71 default SYS_ICACHE_OFF
72 help
73 Do not enable instruction cache in SPL.
74
Trevor Woernerba64b8b2019-05-03 09:40:59 -040075config SYS_DCACHE_OFF
76 bool "Do not enable dcache"
Trevor Woernerba64b8b2019-05-03 09:40:59 -040077 help
78 Do not enable data cache in U-Boot.
79
Trevor Woerner43ec7e02019-05-03 09:41:00 -040080config SPL_SYS_DCACHE_OFF
81 bool "Do not enable dcache in SPL"
82 depends on SPL
83 default SYS_DCACHE_OFF
84 help
85 Do not enable data cache in SPL.
86
Shengyu Qud1a32542023-08-09 21:11:31 +080087config SPL_ZERO_MEM_BEFORE_USE
88 bool "Zero memory before use"
89 depends on SPL
Shengyu Qud1a32542023-08-09 21:11:31 +080090 help
91 Zero stack/GD/malloc area in SPL before using them, this is needed for
92 Sifive core devices that uses L2 cache to store SPL.
93
Rick Chen842d5802018-11-07 09:34:06 +080094# board-specific options below
Leo Yu-Chi Liang5d0bbea2024-05-14 17:50:11 +080095source "board/andestech/ae350/Kconfig"
Chia-Wei Wang1c7ed532024-09-10 17:39:16 +080096source "board/aspeed/ibex_ast2700/Kconfig"
Junhui Liu596a4f62025-01-15 00:46:39 +080097source "board/canaan/k230_canmv/Kconfig"
Bin Meng8a8694d2018-09-26 06:55:21 -070098source "board/emulation/qemu-riscv/Kconfig"
Padmarao Begari4216f342019-05-28 15:47:51 +053099source "board/microchip/mpfs_icicle/Kconfig"
Samuel Hollandbd6a54c2023-10-31 00:32:12 -0500100source "board/openpiton/riscv64/Kconfig"
Bin Menge9ead4a2021-03-17 11:10:58 +0800101source "board/sifive/unleashed/Kconfig"
Green Wan2e5da522021-05-27 06:52:13 -0700102source "board/sifive/unmatched/Kconfig"
Sean Andersonedc32ab2020-06-24 06:41:25 -0400103source "board/sipeed/maix/Kconfig"
Kongyang Liub64fc0e2024-01-28 15:05:25 +0800104source "board/sophgo/milkv_duo/Kconfig"
Thomas Bonnefillefcef2ad2024-11-12 15:57:38 +0100105source "board/sophgo/licheerv_nano/Kconfig"
Kongyang Liuad9c1432024-12-15 13:02:41 +0800106source "board/spacemit/bananapi-f3/Kconfig"
Yanhong Wang38678792023-03-29 11:42:20 +0800107source "board/starfive/visionfive2/Kconfig"
Samuel Hollandbd6a54c2023-10-31 00:32:12 -0500108source "board/thead/th1520_lpi4a/Kconfig"
Michal Simek962c10a2023-11-06 12:56:47 +0100109source "board/xilinx/mbv/Kconfig"
Rick Chen64d4ead2017-12-26 13:55:52 +0800110
Rick Chen842d5802018-11-07 09:34:06 +0800111# platform-specific options below
Leo Yu-Chi Liang5d0bbea2024-05-14 17:50:11 +0800112source "arch/riscv/cpu/andes/Kconfig"
Kongyang Liuf7526742024-03-10 00:54:56 +0800113source "arch/riscv/cpu/cv1800b/Kconfig"
Pragnesh Patel25269c02020-05-29 11:33:34 +0530114source "arch/riscv/cpu/fu540/Kconfig"
Green Wan7f337432021-05-27 06:52:07 -0700115source "arch/riscv/cpu/fu740/Kconfig"
Chia-Wei Wang1c7ed532024-09-10 17:39:16 +0800116source "arch/riscv/cpu/ast2700/Kconfig"
Anup Patel1240cd62019-02-25 08:14:10 +0000117source "arch/riscv/cpu/generic/Kconfig"
Yanhong Wang38678792023-03-29 11:42:20 +0800118source "arch/riscv/cpu/jh7110/Kconfig"
Kongyang Liuad9c1432024-12-15 13:02:41 +0800119source "arch/riscv/cpu/k1/Kconfig"
Junhui Liu596a4f62025-01-15 00:46:39 +0800120source "arch/riscv/cpu/k230/Kconfig"
Rick Chen842d5802018-11-07 09:34:06 +0800121
122# architecture-specific options below
123
Rick Chen64d4ead2017-12-26 13:55:52 +0800124choice
Lukas Auer54ebfe72018-11-22 11:26:12 +0100125 prompt "Base ISA"
126 default ARCH_RV32I
Rick Chen64d4ead2017-12-26 13:55:52 +0800127
Lukas Auer54ebfe72018-11-22 11:26:12 +0100128config ARCH_RV32I
129 bool "RV32I"
Rick Chen64d4ead2017-12-26 13:55:52 +0800130 select 32BIT
131 help
Lukas Auer54ebfe72018-11-22 11:26:12 +0100132 Choose this option to target the RV32I base integer instruction set.
Rick Chen64d4ead2017-12-26 13:55:52 +0800133
Lukas Auer54ebfe72018-11-22 11:26:12 +0100134config ARCH_RV64I
135 bool "RV64I"
Rick Chen64d4ead2017-12-26 13:55:52 +0800136 select 64BIT
Andrew Goodbody5b5322c2024-12-16 18:07:35 +0000137 select SPL_64BIT if SPL
Lukas Auer7ab1df02018-11-22 11:26:13 +0100138 select PHYS_64BIT
Rick Chen64d4ead2017-12-26 13:55:52 +0800139 help
Lukas Auer54ebfe72018-11-22 11:26:12 +0100140 Choose this option to target the RV64I base integer instruction set.
Rick Chen64d4ead2017-12-26 13:55:52 +0800141
142endchoice
143
Ben Dooks8a813c12023-09-05 13:12:53 +0100144config FRAMEPOINTER
145 bool "Build with frame pointer for stack unwinding"
146 help
147 Choose this option to use the frame pointer so the stack can be
148 unwound if needed. This is useful for tracing where faults came
149 from as the source may be several functions back
150
151 If you say Y here, then the code size will be increased due to
152 having to store the fp.
153
154config SPL_FRAMEPOINTER
155 bool "Build SPL with frame pointer for stack unwinding"
Heinrich Schuchardt512d41c2024-08-11 11:51:09 +0200156 depends on SPL
Ben Dooks8a813c12023-09-05 13:12:53 +0100157 help
158 Choose this option to use the frame pointer so the stack can be
159 unwound if needed. This is useful for tracing where faults came
160 from as the source may be several functions back
161
162 If you say Y here, then the code size will be increased due to
163 having to store the fp.
164
Lukas Auerecc5d832018-12-12 06:12:23 -0800165choice
166 prompt "Code Model"
167 default CMODEL_MEDLOW
168
169config CMODEL_MEDLOW
170 bool "medium low code model"
171 help
172 U-Boot and its statically defined symbols must lie within a single 2 GiB
173 address range and must lie between absolute addresses -2 GiB and +2 GiB.
174
175config CMODEL_MEDANY
176 bool "medium any code model"
177 help
178 U-Boot and its statically defined symbols must be within any single 2 GiB
179 address range.
180
181endchoice
182
Anup Patel27881772018-12-12 06:12:29 -0800183choice
184 prompt "Run Mode"
185 default RISCV_MMODE
186
187config RISCV_MMODE
188 bool "Machine"
189 help
190 Choose this option to build U-Boot for RISC-V M-Mode.
191
192config RISCV_SMODE
193 bool "Supervisor"
Heinrich Schuchardt20964b62023-09-23 01:35:26 +0200194 imply DEBUG_UART
Anup Patel27881772018-12-12 06:12:29 -0800195 help
196 Choose this option to build U-Boot for RISC-V S-Mode.
197
198endchoice
199
Lukas Auer61346592019-08-21 21:14:43 +0200200choice
201 prompt "SPL Run Mode"
202 default SPL_RISCV_MMODE
203 depends on SPL
204
205config SPL_RISCV_MMODE
206 bool "Machine"
207 help
208 Choose this option to build U-Boot SPL for RISC-V M-Mode.
209
210config SPL_RISCV_SMODE
211 bool "Supervisor"
212 help
213 Choose this option to build U-Boot SPL for RISC-V S-Mode.
214
215endchoice
216
Lukas Auer002012f2018-11-22 11:26:14 +0100217config RISCV_ISA_C
218 bool "Emit compressed instructions"
219 default y
220 help
221 Adds "C" to the ISA subsets that the toolchain is allowed to emit
222 when building U-Boot, which results in compressed instructions in the
223 U-Boot binary.
224
Heinrich Schuchardtc66c9502022-10-12 14:59:51 +0200225config RISCV_ISA_F
226 bool "Standard extension for Single-Precision Floating Point"
227 default y
228 help
229 Adds "F" to the ISA string passed to the compiler.
230
231config RISCV_ISA_D
232 bool "Standard extension for Double-Precision Floating Point"
233 depends on RISCV_ISA_F
234 default y
235 help
236 Adds "D" to the ISA string passed to the compiler and changes the
237 riscv32 ABI from ilp32 to ilp32d and the riscv64 ABI from lp64 to
238 lp64d.
239
Yu Chien Peter Lin60814cb2023-08-09 18:49:30 +0800240config RISCV_ISA_ZBB
241 bool "Zbb extension support for bit manipulation instructions"
242 help
243 Adds ZBB extension (basic bit manipulation) to the ISA subsets
244 that the toolchain is allowed to emit when building U-Boot.
245 The Zbb extension provides instructions to accelerate a number
246 of bit-specific operations (count bit population, sign extending,
247 bitrotation, etc) and enables optimized string routines.
248
249menu "Use assembly optimized implementation of string routines"
250
251config USE_ARCH_STRLEN
252 bool "Use an assembly optimized implementation of strlen"
253 default y
254 depends on RISCV_ISA_ZBB
255 help
256 Enable the generation of an optimized version of strlen using
257 Zbb extension.
258
259config SPL_USE_ARCH_STRLEN
260 bool "Use an assembly optimized implementation of strlen for SPL"
261 default y if USE_ARCH_STRLEN
262 depends on RISCV_ISA_ZBB
263 depends on SPL
264 help
265 Enable the generation of an optimized version of strlen using
266 Zbb extension.
267
268config TPL_USE_ARCH_STRLEN
269 bool "Use an assembly optimized implementation of strlen for TPL"
270 default y if USE_ARCH_STRLEN
271 depends on RISCV_ISA_ZBB
272 depends on TPL
273 help
274 Enable the generation of an optimized version of strlen using
275 Zbb extension.
276
277config USE_ARCH_STRCMP
278 bool "Use an assembly optimized implementation of strcmp"
279 default y
280 depends on RISCV_ISA_ZBB
281 help
282 Enable the generation of an optimized version of strcmp using
283 Zbb extension.
284
285config SPL_USE_ARCH_STRCMP
286 bool "Use an assembly optimized implementation of strcmp for SPL"
287 default y if USE_ARCH_STRCMP
288 depends on RISCV_ISA_ZBB
289 depends on SPL
290 help
291 Enable the generation of an optimized version of strcmp using
292 Zbb extension.
293
294config TPL_USE_ARCH_STRCMP
295 bool "Use an assembly optimized implementation of strcmp for TPL"
296 default y if USE_ARCH_STRCMP
297 depends on RISCV_ISA_ZBB
298 depends on TPL
299 help
300 Enable the generation of an optimized version of strcmp using
301 Zbb extension.
302
303config USE_ARCH_STRNCMP
304 bool "Use an assembly optimized implementation of strncmp"
305 default y
306 depends on RISCV_ISA_ZBB
307 help
308 Enable the generation of an optimized version of strncmp using
309 Zbb extension.
310
311config SPL_USE_ARCH_STRNCMP
312 bool "Use an assembly optimized implementation of strncmp for SPL"
313 default y if USE_ARCH_STRNCMP
314 depends on RISCV_ISA_ZBB
315 depends on SPL
316 help
317 Enable the generation of an optimized version of strncmp using
318 Zbb extension.
319
320config TPL_USE_ARCH_STRNCMP
321 bool "Use an assembly optimized implementation of strncmp for TPL"
322 default y if USE_ARCH_STRNCMP
323 depends on RISCV_ISA_ZBB
324 depends on TPL
325 help
326 Enable the generation of an optimized version of strncmp using
327 Zbb extension.
328
329endmenu
330
Lukas Auer002012f2018-11-22 11:26:14 +0100331config RISCV_ISA_A
Chia-Wei Wang6eda8742024-09-10 17:39:13 +0800332 bool "Standard extension for Atomic Instructions"
333 default y
334 help
335 Adds "A" to the ISA string passed to the compiler.
Lukas Auer002012f2018-11-22 11:26:14 +0100336
Mayuresh Chitalec3abcaa2024-08-23 09:41:26 +0000337config RISCV_ISA_ZICBOM
338 bool "Zicbom support"
339 depends on !SYS_DISABLE_DCACHE_OPS
340
Padmarao Begaria235d432021-01-15 08:20:35 +0530341config DMA_ADDR_T_64BIT
342 bool
343 default y if 64BIT
344
Bin Mengb5f03722023-06-21 23:11:46 +0800345config RISCV_ACLINT
Bin Mengb6ee5e12018-12-12 06:12:30 -0800346 bool
Bin Meng614b1d82021-05-11 20:04:12 +0800347 depends on RISCV_MMODE
Bin Meng08b8d262023-06-21 23:11:45 +0800348 select REGMAP
349 select SYSCON
Bin Meng614b1d82021-05-11 20:04:12 +0800350 help
Bin Mengb5f03722023-06-21 23:11:46 +0800351 The RISC-V ACLINT block holds memory-mapped control and status registers
Bin Meng614b1d82021-05-11 20:04:12 +0800352 associated with software and timer interrupts.
353
Bin Mengb5f03722023-06-21 23:11:46 +0800354config SPL_RISCV_ACLINT
Bin Meng614b1d82021-05-11 20:04:12 +0800355 bool
356 depends on SPL_RISCV_MMODE
Bin Meng08b8d262023-06-21 23:11:45 +0800357 select SPL_REGMAP
358 select SPL_SYSCON
Bin Mengb6ee5e12018-12-12 06:12:30 -0800359 help
Bin Mengb5f03722023-06-21 23:11:46 +0800360 The RISC-V ACLINT block holds memory-mapped control and status registers
Bin Mengb6ee5e12018-12-12 06:12:30 -0800361 associated with software and timer interrupts.
362
Zong Lic39544c2021-09-01 15:01:41 +0800363config SIFIVE_CACHE
364 bool
365 help
366 This enables the operations to configure SiFive cache
367
Yu Chien Peter Lin739cd6f2022-10-25 23:03:50 +0800368config ANDES_PLICSW
Rick Chen6df4ed02019-04-02 15:56:39 +0800369 bool
Lukas Auer61346592019-08-21 21:14:43 +0200370 depends on RISCV_MMODE || SPL_RISCV_MMODE
Rick Chen6df4ed02019-04-02 15:56:39 +0800371 select REGMAP
372 select SYSCON
Lukas Auer61346592019-08-21 21:14:43 +0200373 select SPL_REGMAP if SPL
374 select SPL_SYSCON if SPL
Rick Chen6df4ed02019-04-02 15:56:39 +0800375 help
Yu Chien Peter Lin739cd6f2022-10-25 23:03:50 +0800376 The Andes PLICSW block holds memory-mapped claim and pending
377 registers associated with software interrupt.
Rick Chen6df4ed02019-04-02 15:56:39 +0800378
Lukas Auer83d573d2019-03-17 19:28:32 +0100379config SMP
380 bool "Symmetric Multi-Processing"
Bin Meng49975222020-04-16 08:09:31 -0700381 depends on SBI_V01 || !RISCV_SMODE
Lukas Auer83d573d2019-03-17 19:28:32 +0100382 help
383 This enables support for systems with more than one CPU. If
384 you say N here, U-Boot will run on single and multiprocessor
385 machines, but will use only one CPU of a multiprocessor
386 machine. If you say Y here, U-Boot will run on many, but not
387 all, single processor machines.
388
Bin Mengb161f902020-04-16 08:09:30 -0700389config SPL_SMP
390 bool "Symmetric Multi-Processing in SPL"
391 depends on SPL && SPL_RISCV_MMODE
392 default y
393 help
394 This enables support for systems with more than one CPU in SPL.
395 If you say N here, U-Boot SPL will run on single and multiprocessor
396 machines, but will use only one CPU of a multiprocessor
397 machine. If you say Y here, U-Boot SPL will run on many, but not
398 all, single processor machines.
399
Lukas Auer83d573d2019-03-17 19:28:32 +0100400config NR_CPUS
401 int "Maximum number of CPUs (2-32)"
402 range 2 32
Bin Mengb161f902020-04-16 08:09:30 -0700403 depends on SMP || SPL_SMP
Lukas Auer83d573d2019-03-17 19:28:32 +0100404 default 8
405 help
406 On multiprocessor machines, U-Boot sets up a stack for each CPU.
407 Stack memory is pre-allocated. U-Boot must therefore know the
408 maximum number of CPUs that may be present.
409
Bin Mengee3bcd02020-03-09 19:35:28 -0700410config SBI
411 bool
412 default y if RISCV_SMODE || SPL_RISCV_SMODE
413
Bin Menga75325e2020-04-16 08:09:32 -0700414choice
415 prompt "SBI support"
Bin Meng3aecc4b2020-04-16 08:09:33 -0700416 default SBI_V02
Bin Menga75325e2020-04-16 08:09:32 -0700417
Bin Meng887d8092020-03-09 19:35:30 -0700418config SBI_V01
419 bool "SBI v0.1 support"
Bin Meng887d8092020-03-09 19:35:30 -0700420 depends on SBI
421 help
422 This config allows kernel to use SBI v0.1 APIs. This will be
423 deprecated in future once legacy M-mode software are no longer in use.
424
Bin Menga75325e2020-04-16 08:09:32 -0700425config SBI_V02
Heinrich Schuchardt693baee2022-11-08 15:53:12 +0100426 bool "SBI v0.2 or later support"
Bin Menga75325e2020-04-16 08:09:32 -0700427 depends on SBI
428 help
Heinrich Schuchardt693baee2022-11-08 15:53:12 +0100429 The SBI specification introduced the concept of extensions in version
430 v0.2. With this configuration option U-Boot can detect and use SBI
431 extensions. With the HSM extension introduced in SBI 0.2, only a
432 single hart needs to boot and enter the operating system. The booting
433 hart can bring up secondary harts one by one afterwards.
Bin Menga75325e2020-04-16 08:09:32 -0700434
Heinrich Schuchardt693baee2022-11-08 15:53:12 +0100435 Choose this option if OpenSBI release v0.7 or above is used together
Bin Menga75325e2020-04-16 08:09:32 -0700436 with U-Boot.
437
438endchoice
439
Lukas Auere79178b2019-03-17 19:28:34 +0100440config SBI_IPI
441 bool
Bin Mengee3bcd02020-03-09 19:35:28 -0700442 depends on SBI
Lukas Auer61346592019-08-21 21:14:43 +0200443 default y if RISCV_SMODE || SPL_RISCV_SMODE
Lukas Auere79178b2019-03-17 19:28:34 +0100444 depends on SMP
445
Rick Chene5e6c362019-04-30 13:49:33 +0800446config XIP
447 bool "XIP mode"
448 help
449 XIP (eXecute In Place) is a method for executing code directly
450 from a NOR flash memory without copying the code to ram.
451 Say yes here if U-Boot boots from flash directly.
452
Nikita Shubin7e5e0292022-09-02 11:47:39 +0300453config SPL_XIP
454 bool "Enable XIP mode for SPL"
455 help
456 If SPL starts in read-only memory (XIP for example) then we shouldn't
457 rely on lock variables (for example hart_lottery and available_harts_lock),
458 this affects only SPL, other stages should proceed as non-XIP.
459
Rick Chen9c4d5c12022-09-21 14:34:54 +0800460config AVAILABLE_HARTS
461 bool "Send IPI by available harts"
Heinrich Schuchardt9800f1f2025-01-23 03:21:40 +0100462 depends on !XIP
Rick Chen9c4d5c12022-09-21 14:34:54 +0800463 default y
464 help
465 By default, IPI sending mechanism will depend on available_harts.
466 If disable this, it will send IPI by CPUs node numbers of device tree.
467
Sean Andersone8b46a12019-12-25 00:27:44 -0500468config SHOW_REGS
Heinrich Schuchardt943e6be2024-08-11 13:01:04 +0200469 default y
Sean Andersone8b46a12019-12-25 00:27:44 -0500470 bool "Show registers on unhandled exception"
Heinrich Schuchardt99e92102024-08-11 13:01:03 +0200471 help
472 By default only the program counter and the return address register
473 are shown in crash dumps. Enable this symbol to show all registers in
474 main U-Boot.
475
476config SPL_SHOW_REGS
477 bool "In SPL show registers on unhandled exception"
478 depends on SPL
479 help
480 By default only the program counter and the return address register
481 are shown in crash dumps. Enable this symbol to show all registers in
482 SPL.
Sean Andersone8b46a12019-12-25 00:27:44 -0500483
Sean Anderson7f4b6662020-06-24 06:41:19 -0400484config RISCV_PRIV_1_9
485 bool "Use version 1.9 of the RISC-V priviledged specification"
486 help
487 Older versions of the RISC-V priviledged specification had
488 separate counter enable CSRs for each privilege mode. Writing
489 to the unified mcounteren CSR on a processor implementing the
490 old specification will result in an illegal instruction
491 exception. In addition to counter CSR changes, the way virtual
492 memory is configured was also changed.
493
Lukas Auera3596652019-03-17 19:28:37 +0100494config STACK_SIZE_SHIFT
Chia-Wei Wang20144dc2024-09-10 17:39:14 +0800495 int "Stack size shift"
Lukas Auer03813702019-10-20 20:53:47 +0200496 default 14
Lukas Auera3596652019-03-17 19:28:37 +0100497
Bin Meng2bdcd052020-06-25 18:16:08 -0700498config OF_BOARD_FIXUP
Sean Anderson584a5ee2020-09-05 09:22:11 -0400499 default y if OF_SEPARATE && RISCV_SMODE
Bin Meng2bdcd052020-06-25 18:16:08 -0700500
Bin Mengce64bd32021-05-13 16:46:18 +0800501menu "Use assembly optimized implementation of memory routines"
502
Heinrich Schuchardt23caf662021-03-27 12:37:04 +0100503config USE_ARCH_MEMCPY
504 bool "Use an assembly optimized implementation of memcpy"
505 default y
506 help
507 Enable the generation of an optimized version of memcpy.
508 Such an implementation may be faster under some conditions
509 but may increase the binary size.
510
511config SPL_USE_ARCH_MEMCPY
512 bool "Use an assembly optimized implementation of memcpy for SPL"
513 default y if USE_ARCH_MEMCPY
514 depends on SPL
515 help
516 Enable the generation of an optimized version of memcpy.
517 Such an implementation may be faster under some conditions
518 but may increase the binary size.
519
520config TPL_USE_ARCH_MEMCPY
521 bool "Use an assembly optimized implementation of memcpy for TPL"
522 default y if USE_ARCH_MEMCPY
523 depends on TPL
524 help
525 Enable the generation of an optimized version of memcpy.
526 Such an implementation may be faster under some conditions
527 but may increase the binary size.
528
529config USE_ARCH_MEMMOVE
530 bool "Use an assembly optimized implementation of memmove"
531 default y
532 help
533 Enable the generation of an optimized version of memmove.
534 Such an implementation may be faster under some conditions
535 but may increase the binary size.
536
537config SPL_USE_ARCH_MEMMOVE
538 bool "Use an assembly optimized implementation of memmove for SPL"
539 default y if USE_ARCH_MEMCPY
540 depends on SPL
541 help
542 Enable the generation of an optimized version of memmove.
543 Such an implementation may be faster under some conditions
544 but may increase the binary size.
545
546config TPL_USE_ARCH_MEMMOVE
547 bool "Use an assembly optimized implementation of memmove for TPL"
548 default y if USE_ARCH_MEMCPY
549 depends on TPL
550 help
551 Enable the generation of an optimized version of memmove.
552 Such an implementation may be faster under some conditions
553 but may increase the binary size.
554
555config USE_ARCH_MEMSET
556 bool "Use an assembly optimized implementation of memset"
557 default y
558 help
559 Enable the generation of an optimized version of memset.
560 Such an implementation may be faster under some conditions
561 but may increase the binary size.
562
563config SPL_USE_ARCH_MEMSET
564 bool "Use an assembly optimized implementation of memset for SPL"
565 default y if USE_ARCH_MEMSET
566 depends on SPL
567 help
568 Enable the generation of an optimized version of memset.
569 Such an implementation may be faster under some conditions
570 but may increase the binary size.
571
572config TPL_USE_ARCH_MEMSET
573 bool "Use an assembly optimized implementation of memset for TPL"
574 default y if USE_ARCH_MEMSET
575 depends on TPL
576 help
577 Enable the generation of an optimized version of memset.
578 Such an implementation may be faster under some conditions
579 but may increase the binary size.
580
Rick Chen64d4ead2017-12-26 13:55:52 +0800581endmenu
Bin Mengce64bd32021-05-13 16:46:18 +0800582
Randolphb1bc7a72023-10-12 14:35:04 +0800583config SPL_LOAD_FIT_OPENSBI_OS_BOOT
584 bool "Enable SPL (OpenSBI OS boot mode) applying linux from FIT"
585 depends on SPL_LOAD_FIT
586 help
587 Use fw_dynamic from the FIT image, and u-boot SPL will invoke it directly.
588 This is a shortcut boot flow, from u-boot SPL -> OpenSBI -> u-boot proper
589 -> linux to u-boot SPL -> OpenSBI -> linux.
590
Yu-Chien Peter Lincac40df2025-01-11 09:55:26 +0800591config SPL_OPTEE_LOAD_ADDR
592 hex "OP-TEE Trusted OS image load address"
593 depends on OPTEE
594 help
595 Load address of the OP-TEE binary.
596
Bin Mengce64bd32021-05-13 16:46:18 +0800597endmenu