riscv: Add AST2700 SoC initial platform support
AST2700 SoCs integrates a Ibex 32-bits RISC-V core as the boot MCU
for the first stage bootloader execution, namely SPL.
This patch implements the preliminary base to successfully run SPL
on this RV32-based MCU to the console banner message.
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index d0476f9..6b854cc 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -46,6 +46,9 @@
config TARGET_XILINX_MBV
bool "Support AMD/Xilinx MicroBlaze V"
+config TARGET_ASPEED_AST2700_IBEX
+ bool "Support Ibex RISC-V cores on Aspeed AST2700 SoC"
+
endchoice
config SYS_ICACHE_OFF
@@ -81,6 +84,7 @@
# board-specific options below
source "board/andestech/ae350/Kconfig"
+source "board/aspeed/ibex_ast2700/Kconfig"
source "board/emulation/qemu-riscv/Kconfig"
source "board/microchip/mpfs_icicle/Kconfig"
source "board/openpiton/riscv64/Kconfig"
@@ -97,6 +101,7 @@
source "arch/riscv/cpu/cv1800b/Kconfig"
source "arch/riscv/cpu/fu540/Kconfig"
source "arch/riscv/cpu/fu740/Kconfig"
+source "arch/riscv/cpu/ast2700/Kconfig"
source "arch/riscv/cpu/generic/Kconfig"
source "arch/riscv/cpu/jh7110/Kconfig"