| commit | c3abcaa641afc96fef602e2491d02de74d710c37 | [log] [tgz] |
|---|---|---|
| author | Mayuresh Chitale <mchitale@ventanamicro.com> | Fri Aug 23 09:41:26 2024 +0000 |
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | Mon Oct 28 18:56:54 2024 +0800 |
| tree | 6b8fd72381d41b2d8af7fef322ce912b1af6138d | |
| parent | f440c0692cd3ea3fc5884fd09dda66755c3144b5 [diff] |
riscv: cache: Add CBO instructions Define CBO inval and flush instructions and use those for the dcache inval and flush operations respectively. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>