Blame - arch/riscv/Kconfig - filogic/uboot

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Bin Meng	6b69775	2018-09-26 06:55:06 -0700	[diff] [blame]	1	menu "RISC-V architecture"
Rick Chen	64d4ead	2017-12-26 13:55:52 +0800	[diff] [blame]	2	depends on RISCV
				3
				4	config SYS_ARCH
				5	default "riscv"
				6
				7	choice
				8	prompt "Target select"
				9	optional
				10
Rick Chen	b66af37	2018-05-29 09:54:40 +0800	[diff] [blame]	11	config TARGET_AX25_AE350
				12	bool "Support ax25-ae350"
Rick Chen	64d4ead	2017-12-26 13:55:52 +0800	[diff] [blame]	13
Bin Meng	8a8694d	2018-09-26 06:55:21 -0700	[diff] [blame]	14	config TARGET_QEMU_VIRT
				15	bool "Support QEMU Virt Board"
				16
Anup Patel	7a167f2	2019-02-25 08:15:19 +0000	[diff] [blame^]	17	config TARGET_SIFIVE_FU540
				18	bool "Support SiFive FU540 Board"
				19
Rick Chen	64d4ead	2017-12-26 13:55:52 +0800	[diff] [blame]	20	endchoice
				21
Rick Chen	842d580	2018-11-07 09:34:06 +0800	[diff] [blame]	22	# board-specific options below
Rick Chen	b66af37	2018-05-29 09:54:40 +0800	[diff] [blame]	23	source "board/AndesTech/ax25-ae350/Kconfig"
Bin Meng	8a8694d	2018-09-26 06:55:21 -0700	[diff] [blame]	24	source "board/emulation/qemu-riscv/Kconfig"
Anup Patel	7a167f2	2019-02-25 08:15:19 +0000	[diff] [blame^]	25	source "board/sifive/fu540/Kconfig"
Rick Chen	64d4ead	2017-12-26 13:55:52 +0800	[diff] [blame]	26
Rick Chen	842d580	2018-11-07 09:34:06 +0800	[diff] [blame]	27	# platform-specific options below
				28	source "arch/riscv/cpu/ax25/Kconfig"
Anup Patel	1240cd6	2019-02-25 08:14:10 +0000	[diff] [blame]	29	source "arch/riscv/cpu/generic/Kconfig"
Rick Chen	842d580	2018-11-07 09:34:06 +0800	[diff] [blame]	30
				31	# architecture-specific options below
				32
Rick Chen	64d4ead	2017-12-26 13:55:52 +0800	[diff] [blame]	33	choice
Lukas Auer	54ebfe7	2018-11-22 11:26:12 +0100	[diff] [blame]	34	prompt "Base ISA"
				35	default ARCH_RV32I
Rick Chen	64d4ead	2017-12-26 13:55:52 +0800	[diff] [blame]	36
Lukas Auer	54ebfe7	2018-11-22 11:26:12 +0100	[diff] [blame]	37	config ARCH_RV32I
				38	bool "RV32I"
Rick Chen	64d4ead	2017-12-26 13:55:52 +0800	[diff] [blame]	39	select 32BIT
				40	help
Lukas Auer	54ebfe7	2018-11-22 11:26:12 +0100	[diff] [blame]	41	Choose this option to target the RV32I base integer instruction set.
Rick Chen	64d4ead	2017-12-26 13:55:52 +0800	[diff] [blame]	42
Lukas Auer	54ebfe7	2018-11-22 11:26:12 +0100	[diff] [blame]	43	config ARCH_RV64I
				44	bool "RV64I"
Rick Chen	64d4ead	2017-12-26 13:55:52 +0800	[diff] [blame]	45	select 64BIT
Lukas Auer	7ab1df0	2018-11-22 11:26:13 +0100	[diff] [blame]	46	select PHYS_64BIT
Rick Chen	64d4ead	2017-12-26 13:55:52 +0800	[diff] [blame]	47	help
Lukas Auer	54ebfe7	2018-11-22 11:26:12 +0100	[diff] [blame]	48	Choose this option to target the RV64I base integer instruction set.
Rick Chen	64d4ead	2017-12-26 13:55:52 +0800	[diff] [blame]	49
				50	endchoice
				51
Lukas Auer	ecc5d83	2018-12-12 06:12:23 -0800	[diff] [blame]	52	choice
				53	prompt "Code Model"
				54	default CMODEL_MEDLOW
				55
				56	config CMODEL_MEDLOW
				57	bool "medium low code model"
				58	help
				59	U-Boot and its statically defined symbols must lie within a single 2 GiB
				60	address range and must lie between absolute addresses -2 GiB and +2 GiB.
				61
				62	config CMODEL_MEDANY
				63	bool "medium any code model"
				64	help
				65	U-Boot and its statically defined symbols must be within any single 2 GiB
				66	address range.
				67
				68	endchoice
				69
Anup Patel	2788177	2018-12-12 06:12:29 -0800	[diff] [blame]	70	choice
				71	prompt "Run Mode"
				72	default RISCV_MMODE
				73
				74	config RISCV_MMODE
				75	bool "Machine"
				76	help
				77	Choose this option to build U-Boot for RISC-V M-Mode.
				78
				79	config RISCV_SMODE
				80	bool "Supervisor"
				81	help
				82	Choose this option to build U-Boot for RISC-V S-Mode.
				83
				84	endchoice
				85
Lukas Auer	002012f	2018-11-22 11:26:14 +0100	[diff] [blame]	86	config RISCV_ISA_C
				87	bool "Emit compressed instructions"
				88	default y
				89	help
				90	Adds "C" to the ISA subsets that the toolchain is allowed to emit
				91	when building U-Boot, which results in compressed instructions in the
				92	U-Boot binary.
				93
				94	config RISCV_ISA_A
				95	def_bool y
				96
Rick Chen	64d4ead	2017-12-26 13:55:52 +0800	[diff] [blame]	97	config 32BIT
				98	bool
				99
				100	config 64BIT
				101	bool
				102
Bin Meng	b6ee5e1	2018-12-12 06:12:30 -0800	[diff] [blame]	103	config SIFIVE_CLINT
				104	bool
				105	depends on RISCV_MMODE
				106	select REGMAP
				107	select SYSCON
				108	help
				109	The SiFive CLINT block holds memory-mapped control and status registers
				110	associated with software and timer interrupts.
				111
Anup Patel	f3c8479	2018-12-12 06:12:31 -0800	[diff] [blame]	112	config RISCV_RDTIME
				113	bool
				114	default y if RISCV_SMODE
				115	help
				116	The provides the riscv_get_time() API that is implemented using the
				117	standard rdtime instruction. This is the case for S-mode U-Boot, and
				118	is useful for processors that support rdtime in M-mode too.
				119
Bin Meng	dada2d1	2018-12-12 06:12:33 -0800	[diff] [blame]	120	config SYS_MALLOC_F_LEN
				121	default 0x1000
				122
Rick Chen	64d4ead	2017-12-26 13:55:52 +0800	[diff] [blame]	123	endmenu