842d5809d380bcabd430679f899c3d45ef01fa46 - filogic/uboot

commit	842d5809d380bcabd430679f899c3d45ef01fa46	[log] [tgz]
author	Rick Chen <rick@andestech.com>	Wed Nov 07 09:34:06 2018 +0800
committer	Andes <uboot@andestech.com>	Mon Nov 26 13:58:01 2018 +0800
tree	903fe89d39120e2cfaf553f8cdfe0aeb2b5b106c
parent	baaa062e9adaf6b142a266a36efda127b9bc3e94 [diff]

riscv: cache: Implement i/dcache [status, enable, disable]

AndeStar RISC-V(V5) provide mcache_ctl register which
can configure I/D cache as enabled or disabled.

This CSR will be encapsulated by CONFIG_RISCV_NDS.
If you want to configure cache on AndeStar V5
AE350 platform. YOu can enable [*] AndeStar V5 ISA support
by make menuconfig.

This approach also provide the expansion when the
vender specific features are going to join in.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>

arch/riscv/Kconfig[diff]
arch/riscv/cpu/ax25/Kconfig[Added - diff]
arch/riscv/cpu/ax25/Makefile[diff]
arch/riscv/cpu/ax25/cache.c[Added - diff]
arch/riscv/cpu/ax25/cpu.c[diff]
arch/riscv/cpu/qemu/cpu.c[diff]
arch/riscv/cpu/start.S[diff]
arch/riscv/include/asm/cache.h[diff]
arch/riscv/lib/cache.c[diff]

9 files changed

tree: 903fe89d39120e2cfaf553f8cdfe0aeb2b5b106c