tree 903fe89d39120e2cfaf553f8cdfe0aeb2b5b106c
parent baaa062e9adaf6b142a266a36efda127b9bc3e94
author Rick Chen <rick@andestech.com> 1541554446 +0800
committer Andes <uboot@andestech.com> 1543211881 +0800

riscv: cache: Implement i/dcache [status, enable, disable]

AndeStar RISC-V(V5) provide mcache_ctl register which
can configure I/D cache as enabled or disabled.

This CSR will be encapsulated by CONFIG_RISCV_NDS.
If you want to configure cache on AndeStar V5
AE350 platform. YOu can enable [*] AndeStar V5 ISA support
by make menuconfig.

This approach also provide the expansion when the
vender specific features are going to join in.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>