Blame - arch/riscv/Kconfig - filogic/uboot

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Bin Meng	6b69775	2018-09-26 06:55:06 -0700	[diff] [blame]	1	menu "RISC-V architecture"
Rick Chen	64d4ead	2017-12-26 13:55:52 +0800	[diff] [blame]	2	depends on RISCV
				3
				4	config SYS_ARCH
				5	default "riscv"
				6
				7	choice
				8	prompt "Target select"
				9	optional
				10
Rick Chen	b66af37	2018-05-29 09:54:40 +0800	[diff] [blame]	11	config TARGET_AX25_AE350
				12	bool "Support ax25-ae350"
Rick Chen	64d4ead	2017-12-26 13:55:52 +0800	[diff] [blame]	13
Bin Meng	8a8694d	2018-09-26 06:55:21 -0700	[diff] [blame]	14	config TARGET_QEMU_VIRT
				15	bool "Support QEMU Virt Board"
				16
Rick Chen	64d4ead	2017-12-26 13:55:52 +0800	[diff] [blame]	17	endchoice
				18
Rick Chen	842d580	2018-11-07 09:34:06 +0800	[diff] [blame]	19	# board-specific options below
Rick Chen	b66af37	2018-05-29 09:54:40 +0800	[diff] [blame]	20	source "board/AndesTech/ax25-ae350/Kconfig"
Bin Meng	8a8694d	2018-09-26 06:55:21 -0700	[diff] [blame]	21	source "board/emulation/qemu-riscv/Kconfig"
Rick Chen	64d4ead	2017-12-26 13:55:52 +0800	[diff] [blame]	22
Rick Chen	842d580	2018-11-07 09:34:06 +0800	[diff] [blame]	23	# platform-specific options below
				24	source "arch/riscv/cpu/ax25/Kconfig"
Bin Meng	8fa4478	2018-12-12 06:12:32 -0800	[diff] [blame]	25	source "arch/riscv/cpu/qemu/Kconfig"
Rick Chen	842d580	2018-11-07 09:34:06 +0800	[diff] [blame]	26
				27	# architecture-specific options below
				28
Rick Chen	64d4ead	2017-12-26 13:55:52 +0800	[diff] [blame]	29	choice
Lukas Auer	54ebfe7	2018-11-22 11:26:12 +0100	[diff] [blame]	30	prompt "Base ISA"
				31	default ARCH_RV32I
Rick Chen	64d4ead	2017-12-26 13:55:52 +0800	[diff] [blame]	32
Lukas Auer	54ebfe7	2018-11-22 11:26:12 +0100	[diff] [blame]	33	config ARCH_RV32I
				34	bool "RV32I"
Rick Chen	64d4ead	2017-12-26 13:55:52 +0800	[diff] [blame]	35	select 32BIT
				36	help
Lukas Auer	54ebfe7	2018-11-22 11:26:12 +0100	[diff] [blame]	37	Choose this option to target the RV32I base integer instruction set.
Rick Chen	64d4ead	2017-12-26 13:55:52 +0800	[diff] [blame]	38
Lukas Auer	54ebfe7	2018-11-22 11:26:12 +0100	[diff] [blame]	39	config ARCH_RV64I
				40	bool "RV64I"
Rick Chen	64d4ead	2017-12-26 13:55:52 +0800	[diff] [blame]	41	select 64BIT
Lukas Auer	7ab1df0	2018-11-22 11:26:13 +0100	[diff] [blame]	42	select PHYS_64BIT
Rick Chen	64d4ead	2017-12-26 13:55:52 +0800	[diff] [blame]	43	help
Lukas Auer	54ebfe7	2018-11-22 11:26:12 +0100	[diff] [blame]	44	Choose this option to target the RV64I base integer instruction set.
Rick Chen	64d4ead	2017-12-26 13:55:52 +0800	[diff] [blame]	45
				46	endchoice
				47
Lukas Auer	ecc5d83	2018-12-12 06:12:23 -0800	[diff] [blame]	48	choice
				49	prompt "Code Model"
				50	default CMODEL_MEDLOW
				51
				52	config CMODEL_MEDLOW
				53	bool "medium low code model"
				54	help
				55	U-Boot and its statically defined symbols must lie within a single 2 GiB
				56	address range and must lie between absolute addresses -2 GiB and +2 GiB.
				57
				58	config CMODEL_MEDANY
				59	bool "medium any code model"
				60	help
				61	U-Boot and its statically defined symbols must be within any single 2 GiB
				62	address range.
				63
				64	endchoice
				65
Anup Patel	2788177	2018-12-12 06:12:29 -0800	[diff] [blame]	66	choice
				67	prompt "Run Mode"
				68	default RISCV_MMODE
				69
				70	config RISCV_MMODE
				71	bool "Machine"
				72	help
				73	Choose this option to build U-Boot for RISC-V M-Mode.
				74
				75	config RISCV_SMODE
				76	bool "Supervisor"
				77	help
				78	Choose this option to build U-Boot for RISC-V S-Mode.
				79
				80	endchoice
				81
Lukas Auer	002012f	2018-11-22 11:26:14 +0100	[diff] [blame]	82	config RISCV_ISA_C
				83	bool "Emit compressed instructions"
				84	default y
				85	help
				86	Adds "C" to the ISA subsets that the toolchain is allowed to emit
				87	when building U-Boot, which results in compressed instructions in the
				88	U-Boot binary.
				89
				90	config RISCV_ISA_A
				91	def_bool y
				92
Rick Chen	64d4ead	2017-12-26 13:55:52 +0800	[diff] [blame]	93	config 32BIT
				94	bool
				95
				96	config 64BIT
				97	bool
				98
Bin Meng	b6ee5e1	2018-12-12 06:12:30 -0800	[diff] [blame]	99	config SIFIVE_CLINT
				100	bool
				101	depends on RISCV_MMODE
				102	select REGMAP
				103	select SYSCON
				104	help
				105	The SiFive CLINT block holds memory-mapped control and status registers
				106	associated with software and timer interrupts.
				107
Anup Patel	f3c8479	2018-12-12 06:12:31 -0800	[diff] [blame]	108	config RISCV_RDTIME
				109	bool
				110	default y if RISCV_SMODE
				111	help
				112	The provides the riscv_get_time() API that is implemented using the
				113	standard rdtime instruction. This is the case for S-mode U-Boot, and
				114	is useful for processors that support rdtime in M-mode too.
				115
Bin Meng	dada2d1	2018-12-12 06:12:33 -0800	[diff] [blame^]	116	config SYS_MALLOC_F_LEN
				117	default 0x1000
				118
Rick Chen	64d4ead	2017-12-26 13:55:52 +0800	[diff] [blame]	119	endmenu