Blame - arch/riscv/Kconfig - filogic/uboot

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Bin Meng	6b69775	2018-09-26 06:55:06 -0700	[diff] [blame]	1	menu "RISC-V architecture"
Rick Chen	64d4ead	2017-12-26 13:55:52 +0800	[diff] [blame]	2	depends on RISCV
				3
				4	config SYS_ARCH
				5	default "riscv"
				6
				7	choice
				8	prompt "Target select"
				9	optional
				10
Rick Chen	b66af37	2018-05-29 09:54:40 +0800	[diff] [blame]	11	config TARGET_AX25_AE350
				12	bool "Support ax25-ae350"
Rick Chen	64d4ead	2017-12-26 13:55:52 +0800	[diff] [blame]	13
Bin Meng	8a8694d	2018-09-26 06:55:21 -0700	[diff] [blame]	14	config TARGET_QEMU_VIRT
				15	bool "Support QEMU Virt Board"
				16
Rick Chen	64d4ead	2017-12-26 13:55:52 +0800	[diff] [blame]	17	endchoice
				18
Rick Chen	842d580	2018-11-07 09:34:06 +0800	[diff] [blame]	19	# board-specific options below
Rick Chen	b66af37	2018-05-29 09:54:40 +0800	[diff] [blame]	20	source "board/AndesTech/ax25-ae350/Kconfig"
Bin Meng	8a8694d	2018-09-26 06:55:21 -0700	[diff] [blame]	21	source "board/emulation/qemu-riscv/Kconfig"
Rick Chen	64d4ead	2017-12-26 13:55:52 +0800	[diff] [blame]	22
Rick Chen	842d580	2018-11-07 09:34:06 +0800	[diff] [blame]	23	# platform-specific options below
				24	source "arch/riscv/cpu/ax25/Kconfig"
				25
				26	# architecture-specific options below
				27
Rick Chen	64d4ead	2017-12-26 13:55:52 +0800	[diff] [blame]	28	choice
Lukas Auer	54ebfe7	2018-11-22 11:26:12 +0100	[diff] [blame]	29	prompt "Base ISA"
				30	default ARCH_RV32I
Rick Chen	64d4ead	2017-12-26 13:55:52 +0800	[diff] [blame]	31
Lukas Auer	54ebfe7	2018-11-22 11:26:12 +0100	[diff] [blame]	32	config ARCH_RV32I
				33	bool "RV32I"
Rick Chen	64d4ead	2017-12-26 13:55:52 +0800	[diff] [blame]	34	select 32BIT
				35	help
Lukas Auer	54ebfe7	2018-11-22 11:26:12 +0100	[diff] [blame]	36	Choose this option to target the RV32I base integer instruction set.
Rick Chen	64d4ead	2017-12-26 13:55:52 +0800	[diff] [blame]	37
Lukas Auer	54ebfe7	2018-11-22 11:26:12 +0100	[diff] [blame]	38	config ARCH_RV64I
				39	bool "RV64I"
Rick Chen	64d4ead	2017-12-26 13:55:52 +0800	[diff] [blame]	40	select 64BIT
Lukas Auer	7ab1df0	2018-11-22 11:26:13 +0100	[diff] [blame]	41	select PHYS_64BIT
Rick Chen	64d4ead	2017-12-26 13:55:52 +0800	[diff] [blame]	42	help
Lukas Auer	54ebfe7	2018-11-22 11:26:12 +0100	[diff] [blame]	43	Choose this option to target the RV64I base integer instruction set.
Rick Chen	64d4ead	2017-12-26 13:55:52 +0800	[diff] [blame]	44
				45	endchoice
				46
Lukas Auer	ecc5d83	2018-12-12 06:12:23 -0800	[diff] [blame^]	47	choice
				48	prompt "Code Model"
				49	default CMODEL_MEDLOW
				50
				51	config CMODEL_MEDLOW
				52	bool "medium low code model"
				53	help
				54	U-Boot and its statically defined symbols must lie within a single 2 GiB
				55	address range and must lie between absolute addresses -2 GiB and +2 GiB.
				56
				57	config CMODEL_MEDANY
				58	bool "medium any code model"
				59	help
				60	U-Boot and its statically defined symbols must be within any single 2 GiB
				61	address range.
				62
				63	endchoice
				64
Lukas Auer	002012f	2018-11-22 11:26:14 +0100	[diff] [blame]	65	config RISCV_ISA_C
				66	bool "Emit compressed instructions"
				67	default y
				68	help
				69	Adds "C" to the ISA subsets that the toolchain is allowed to emit
				70	when building U-Boot, which results in compressed instructions in the
				71	U-Boot binary.
				72
				73	config RISCV_ISA_A
				74	def_bool y
				75
Anup Patel	89b3934	2018-12-03 10:57:40 +0530	[diff] [blame]	76	config RISCV_SMODE
				77	bool "Run in S-Mode"
				78	help
				79	Enable this option to build U-Boot for RISC-V S-Mode
				80
Rick Chen	64d4ead	2017-12-26 13:55:52 +0800	[diff] [blame]	81	config 32BIT
				82	bool
				83
				84	config 64BIT
				85	bool
				86
				87	endmenu