riscv: Rename SiFive CLINT to RISC-V ALINT
As the RISC-V ACLINT specification is defined to be backward compatible
with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V
ALINT in the source tree to be future-proof.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Rick Chen <rick@andestech.com>
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 9fcdd8c..de7d5a9 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -185,22 +185,22 @@
bool
default y if 64BIT
-config SIFIVE_CLINT
+config RISCV_ACLINT
bool
depends on RISCV_MMODE
select REGMAP
select SYSCON
help
- The SiFive CLINT block holds memory-mapped control and status registers
+ The RISC-V ACLINT block holds memory-mapped control and status registers
associated with software and timer interrupts.
-config SPL_SIFIVE_CLINT
+config SPL_RISCV_ACLINT
bool
depends on SPL_RISCV_MMODE
select SPL_REGMAP
select SPL_SYSCON
help
- The SiFive CLINT block holds memory-mapped control and status registers
+ The RISC-V ACLINT block holds memory-mapped control and status registers
associated with software and timer interrupts.
config SIFIVE_CACHE