blob: 9bf44ae3b0bcc3ebce1778d2c2d91eeaea56eb4c [file] [log] [blame]
Simon Glass4cc43bf2021-08-18 21:40:25 -06001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Devicetree file for running sandbox tests
4 *
5 * This includes lots of extra devices used by various tests.
6 *
7 * Note that SPL use the main sandbox.dts file
8 */
9
Simon Glassb2c1cac2014-02-26 15:59:21 -070010/dts-v1/;
11
Eddie James1a55a7a2023-10-24 10:43:51 -050012#include <config.h>
Patrick Delaunay23aee612020-01-13 11:35:13 +010013#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/gpio/sandbox-gpio.h>
Marek Szyprowskiad398592021-02-18 11:33:18 +010015#include <dt-bindings/input/input.h>
Sean Anderson3438e3b2020-09-14 11:01:57 -040016#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +053017#include <dt-bindings/mux/mux.h>
Patrick Delaunay23aee612020-01-13 11:35:13 +010018
Simon Glassb2c1cac2014-02-26 15:59:21 -070019/ {
20 model = "sandbox";
21 compatible = "sandbox";
22 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -060023 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070024
Simon Glassfef72b72014-07-23 06:55:03 -060025 aliases {
26 console = &uart0;
Michael Walle7efcdfd2021-02-25 16:51:11 +010027 ethernet0 = "/eth@10002000";
28 ethernet2 = &swp_0;
29 ethernet3 = &eth_3;
30 ethernet4 = &dsa_eth0;
31 ethernet5 = &eth_5;
Sean Anderson67d93a42022-05-05 13:11:30 -040032 ethernet6 = "/eth@10004000";
33 ethernet7 = &swp_1;
34 ethernet8 = &phy_eth0;
Simon Glass5620cf82018-10-01 12:22:40 -060035 gpio1 = &gpio_a;
36 gpio2 = &gpio_b;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +010037 gpio3 = &gpio_c;
Simon Glass0ccb0972015-01-25 08:27:05 -070038 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -060039 mmc0 = "/mmc0";
40 mmc1 = "/mmc1";
Simon Glassf1eba352022-10-20 18:23:20 -060041 mmc2 = "/mmc2";
42 mmc3 = "/mmc3";
Simon Glassfff928c2023-08-24 13:55:41 -060043 mmc4 = "/mmc4";
44 mmc5 = "/mmc5";
Alexander Gendin038cb022023-10-09 01:24:36 +000045 mmc6 = "/mmc6";
Mattijs Korpershoekd77f8152024-07-10 10:40:06 +020046 mmc7 = "/mmc7";
Bin Meng408e5902018-08-03 01:14:41 -070047 pci0 = &pci0;
48 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -070049 pci2 = &pci2;
Michael Walle7c41a222020-06-02 01:47:09 +020050 remoteproc0 = &rproc_1;
51 remoteproc1 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -060052 rtc0 = &rtc_0;
53 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -060054 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +020055 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -070056 testbus3 = "/some-bus";
57 testfdt0 = "/some-bus/c-test@0";
Simon Glass7d5e4112020-12-16 21:20:26 -070058 testfdt12 = "/some-bus/c-test@1";
Simon Glass0ccb0972015-01-25 08:27:05 -070059 testfdt3 = "/b-test";
60 testfdt5 = "/some-bus/c-test@5";
61 testfdt8 = "/a-test";
Simon Glass791a17f2020-12-16 21:20:27 -070062 testfdtm1 = &testfdtm1;
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +020063 fdt-dummy0 = "/translation-test@8000/dev@0,0";
64 fdt-dummy1 = "/translation-test@8000/dev@1,100";
65 fdt-dummy2 = "/translation-test@8000/dev@2,200";
66 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glass31680482015-03-25 12:23:05 -060067 usb0 = &usb_0;
68 usb1 = &usb_1;
69 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +020070 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +020071 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -060072 };
73
Eddie James1a55a7a2023-10-24 10:43:51 -050074 reserved-memory {
75 #address-cells = <1>;
76 #size-cells = <1>;
77 ranges;
78
79 event_log: tcg_event_log {
80 no-map;
Sughosh Ganu3f768682024-08-26 17:29:32 +053081 reg = <(CFG_SYS_SDRAM_BASE + 0x100000) 0x2000>;
Eddie James1a55a7a2023-10-24 10:43:51 -050082 };
83 };
84
Simon Glass5e135d32022-10-20 18:23:15 -060085 binman: binman {
Philippe Reynes462d1632022-03-28 22:56:53 +020086 };
87
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020088 config {
Simon Glass0034d962021-08-07 07:24:01 -060089 testing-bool;
90 testing-int = <123>;
91 testing-str = "testing";
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020092 environment {
93 from_fdt = "yes";
94 fdt_env_path = "";
95 };
96 };
97
Michal Simek43c42bd2023-08-31 08:59:05 +020098 options {
99 u-boot {
100 compatible = "u-boot,config";
101 bootscr-ram-offset = /bits/ 64 <0x12345678>;
Michal Simek6a7c1ce2023-08-31 09:04:27 +0200102 bootscr-flash-offset = /bits/ 64 <0>;
103 bootscr-flash-size = /bits/ 64 <0x2000>;
Christian Marangi719108e2024-10-01 14:24:43 +0200104 boot-led = "sandbox:green";
105 activity-led = "sandbox:red";
Christian Marangicdc38152024-10-01 14:24:44 +0200106 testing-bool;
107 testing-int = <123>;
108 testing-str = "testing";
Michal Simek43c42bd2023-08-31 08:59:05 +0200109 };
110 };
111
Simon Glassb255efc2022-04-24 23:31:24 -0600112 bootstd {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700113 bootph-verify;
Simon Glassb255efc2022-04-24 23:31:24 -0600114 compatible = "u-boot,boot-std";
115
116 filename-prefixes = "/", "/boot/";
117 bootdev-order = "mmc2", "mmc1";
118
Simon Glassb71d7f72023-05-10 16:34:46 -0600119 extlinux {
120 compatible = "u-boot,extlinux";
Simon Glassb255efc2022-04-24 23:31:24 -0600121 };
122
123 efi {
124 compatible = "u-boot,distro-efi";
125 };
Simon Glassa9289612022-10-20 18:23:14 -0600126
Simon Glassd2bc33ed2023-01-06 08:52:41 -0600127 theme {
128 font-size = <30>;
Simon Glass86f1ac52023-06-01 10:23:00 -0600129 menu-inset = <3>;
130 menuitem-gap-y = <1>;
Simon Glassd2bc33ed2023-01-06 08:52:41 -0600131 };
132
Simon Glass82adc292023-08-14 16:40:30 -0600133 cedit-theme {
134 font-size = <30>;
135 menu-inset = <3>;
136 menuitem-gap-y = <1>;
137 };
138
Simon Glassf1eba352022-10-20 18:23:20 -0600139 /*
140 * This is used for the VBE OS-request tests. A FAT filesystem
141 * created in a partition with the VBE information appearing
Michal Simek33224372023-09-07 14:55:48 +0200142 * before the partition starts
Simon Glassf1eba352022-10-20 18:23:20 -0600143 */
Simon Glassa9289612022-10-20 18:23:14 -0600144 firmware0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700145 bootph-verify;
Simon Glassa9289612022-10-20 18:23:14 -0600146 compatible = "fwupd,vbe-simple";
147 storage = "mmc1";
148 skip-offset = <0x200>;
149 area-start = <0x400>;
150 area-size = <0x1000>;
151 state-offset = <0x400>;
152 state-size = <0x40>;
153 version-offset = <0x800>;
154 version-size = <0x100>;
155 };
Simon Glassf1eba352022-10-20 18:23:20 -0600156
157 /*
158 * This is used for the VBE VPL tests. The MMC device holds the
159 * binman image.bin file. The test progresses through each phase
160 * of U-Boot, loading each in turn from MMC.
161 *
162 * Note that the test enables this node (and mmc3) before
163 * running U-Boot
164 */
165 firmware1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700166 bootph-verify;
Simon Glassf1eba352022-10-20 18:23:20 -0600167 status = "disabled";
168 compatible = "fwupd,vbe-simple";
169 storage = "mmc3";
Simon Glass9bb73e32023-04-02 14:01:24 +1200170 skip-offset = <0x800000>;
Simon Glassf1eba352022-10-20 18:23:20 -0600171 area-start = <0>;
172 area-size = <0xe00000>;
173 state-offset = <0xdffc00>;
174 state-size = <0x40>;
175 version-offset = <0xdffe00>;
176 version-size = <0x100>;
177 };
Simon Glassb255efc2022-04-24 23:31:24 -0600178 };
179
Simon Glass61300722023-06-01 10:23:01 -0600180 cedit: cedit {
181 };
182
Andrew Scull451b8b12022-05-30 10:00:12 +0000183 fuzzing-engine {
184 compatible = "sandbox,fuzzing-engine";
185 };
186
Nandor Han6521e5d2021-06-10 16:56:44 +0300187 reboot-mode0 {
188 compatible = "reboot-mode-gpio";
189 gpios = <&gpio_c 0 GPIO_ACTIVE_HIGH>, <&gpio_c 1 GPIO_ACTIVE_HIGH>;
190 u-boot,env-variable = "bootstatus";
191 mode-test = <0x01>;
192 mode-download = <0x03>;
193 };
194
Nandor Han7e4067a2021-06-10 16:56:45 +0300195 reboot_mode1: reboot-mode@14 {
196 compatible = "reboot-mode-rtc";
197 rtc = <&rtc_0>;
198 reg = <0x30 4>;
199 u-boot,env-variable = "bootstatus";
200 big-endian;
201 mode-test = <0x21969147>;
202 mode-download = <0x51939147>;
203 };
204
Simon Glassed96cde2018-12-10 10:37:33 -0700205 audio: audio-codec {
206 compatible = "sandbox,audio-codec";
207 #sound-dai-cells = <1>;
208 };
209
Philippe Reynes1ee26482020-07-24 18:19:51 +0200210 buttons {
211 compatible = "gpio-keys";
212
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200213 btn1 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200214 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200215 label = "button1";
Dzmitry Sankouski157f2c52023-01-22 18:21:24 +0300216 linux,code = <BTN_1>;
Philippe Reynes1ee26482020-07-24 18:19:51 +0200217 };
218
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200219 btn2 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200220 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200221 label = "button2";
Dzmitry Sankouski157f2c52023-01-22 18:21:24 +0300222 linux,code = <BTN_2>;
Philippe Reynes1ee26482020-07-24 18:19:51 +0200223 };
224 };
225
Marek Szyprowskiad398592021-02-18 11:33:18 +0100226 buttons2 {
227 compatible = "adc-keys";
228 io-channels = <&adc 3>;
229 keyup-threshold-microvolt = <3000000>;
230
231 button-up {
232 label = "button3";
233 linux,code = <KEY_F3>;
234 press-threshold-microvolt = <1500000>;
235 };
236
237 button-down {
238 label = "button4";
239 linux,code = <KEY_F4>;
240 press-threshold-microvolt = <1000000>;
241 };
242
243 button-enter {
244 label = "button5";
245 linux,code = <KEY_F5>;
246 press-threshold-microvolt = <500000>;
247 };
248 };
249
Simon Glassc953aaf2018-12-10 10:37:34 -0700250 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -0600251 reg = <0 0>;
252 compatible = "google,cros-ec-sandbox";
253
254 /*
255 * This describes the flash memory within the EC. Note
256 * that the STM32L flash erases to 0, not 0xff.
257 */
258 flash {
259 image-pos = <0x08000000>;
260 size = <0x20000>;
261 erase-value = <0>;
262
263 /* Information for sandbox */
264 ro {
265 image-pos = <0>;
266 size = <0xf000>;
267 };
268 wp-ro {
269 image-pos = <0xf000>;
270 size = <0x1000>;
Simon Glassbf0a6922021-01-21 13:57:14 -0700271 used = <0x884>;
272 compress = "lz4";
273 uncomp-size = <0xcf8>;
274 hash {
275 algo = "sha256";
276 value = [00 01 02 03 04 05 06 07
277 08 09 0a 0b 0c 0d 0e 0f
278 10 11 12 13 14 15 16 17
279 18 19 1a 1b 1c 1d 1e 1f];
280 };
Simon Glass699c9ca2018-10-01 12:22:08 -0600281 };
282 rw {
283 image-pos = <0x10000>;
284 size = <0x10000>;
285 };
286 };
Alper Nebi Yasak8a8cd4f2021-05-19 19:33:31 +0300287
288 cros_ec_pwm: cros-ec-pwm {
289 compatible = "google,cros-ec-pwm";
290 #pwm-cells = <1>;
291 };
292
Simon Glass699c9ca2018-10-01 12:22:08 -0600293 };
294
Yannick Fertré9712c822019-10-07 15:29:05 +0200295 dsi_host: dsi_host {
296 compatible = "sandbox,dsi-host";
297 };
298
Simon Glassb2c1cac2014-02-26 15:59:21 -0700299 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600300 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700301 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600302 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700303 ping-add = <0>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700304 bootph-all;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100305 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
306 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass16e10402015-01-05 20:05:29 -0700307 <0>, <&gpio_a 12>;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100308 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
309 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
310 <&gpio_b 7 GPIO_IN 3 2 1>,
311 <&gpio_b 8 GPIO_OUT 3 2 1>,
312 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100313 test3-gpios =
314 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
315 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
316 <&gpio_c 2 GPIO_OUT>,
317 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
318 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong643778b2020-05-05 10:43:18 +0200319 <&gpio_c 5 GPIO_IN>,
320 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
321 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530322 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
323 test5-gpios = <&gpio_a 19>;
324
Simon Glass73025392021-10-23 17:26:04 -0600325 bool-value;
Stefan Herbrechtsmeier1b090e62022-06-14 15:21:30 +0200326 int8-value = /bits/ 8 <0x12>;
327 int16-value = /bits/ 16 <0x1234>;
Simon Glass6df01f92018-12-10 10:37:37 -0700328 int-value = <1234>;
329 uint-value = <(-1234)>;
Dario Binacchi421e81e2020-03-29 18:04:40 +0200330 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi81d80b52020-03-29 18:04:41 +0200331 int-array = <5678 9123 4567>;
Michal Simek08a194e2023-08-25 11:37:46 +0200332 int64-array = /bits/ 64 <0x1111222233334444 0x4444333322221111>;
Simon Glassdd0ed902020-07-07 13:11:58 -0600333 str-value = "test string";
Simon Glass515dcff2020-02-06 09:55:00 -0700334 interrupts-extended = <&irq 3 0>;
Simon Glass09642392020-07-07 13:12:11 -0600335 acpi,name = "GHIJ";
Patrick Delaunay8cd28012020-09-25 09:41:16 +0200336 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530337
338 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
339 <&muxcontroller0 2>, <&muxcontroller0 3>,
340 <&muxcontroller1>;
341 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
342 mux-syscon = <&syscon3>;
Dario Binacchi836cc9d2020-12-30 00:16:26 +0100343 display-timings {
344 timing0: 240x320 {
345 clock-frequency = <6500000>;
346 hactive = <240>;
347 vactive = <320>;
348 hfront-porch = <6>;
349 hback-porch = <7>;
350 hsync-len = <1>;
351 vback-porch = <5>;
352 vfront-porch = <8>;
353 vsync-len = <2>;
354 hsync-active = <1>;
355 vsync-active = <0>;
356 de-active = <1>;
357 pixelclk-active = <1>;
358 interlaced;
359 doublescan;
360 doubleclk;
361 };
362 timing1: 480x800 {
363 clock-frequency = <9000000>;
364 hactive = <480>;
365 vactive = <800>;
366 hfront-porch = <10>;
367 hback-porch = <59>;
368 hsync-len = <12>;
369 vback-porch = <15>;
370 vfront-porch = <17>;
371 vsync-len = <16>;
372 hsync-active = <0>;
373 vsync-active = <1>;
374 de-active = <0>;
375 pixelclk-active = <0>;
376 };
377 timing2: 800x480 {
378 clock-frequency = <33500000>;
379 hactive = <800>;
380 vactive = <480>;
381 hback-porch = <89>;
382 hfront-porch = <164>;
383 vback-porch = <23>;
384 vfront-porch = <10>;
385 hsync-len = <11>;
386 vsync-len = <13>;
387 };
388 };
Raphael Gallais-Poua853b922023-05-11 16:36:52 +0200389 panel-timing {
Nikhil M Jainbb9d1312023-01-31 15:35:15 +0530390 clock-frequency = <6500000>;
391 hactive = <240>;
392 vactive = <320>;
393 hfront-porch = <6>;
394 hback-porch = <7>;
395 hsync-len = <1>;
396 vback-porch = <5>;
397 vfront-porch = <8>;
398 vsync-len = <2>;
399 hsync-active = <1>;
400 vsync-active = <0>;
401 de-active = <1>;
402 pixelclk-active = <1>;
403 interlaced;
404 doublescan;
405 doubleclk;
406 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700407 };
408
409 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600410 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700411 compatible = "not,compatible";
412 };
413
414 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600415 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700416 };
417
Simon Glass5620cf82018-10-01 12:22:40 -0600418 backlight: backlight {
419 compatible = "pwm-backlight";
420 enable-gpios = <&gpio_a 1>;
421 power-supply = <&ldo_1>;
422 pwms = <&pwm 0 1000>;
423 default-brightness-level = <5>;
424 brightness-levels = <0 16 32 64 128 170 202 234 255>;
425 };
426
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200427 bind-test {
Patrice Chotard7b7f9392020-07-28 09:13:33 +0200428 compatible = "simple-bus";
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200429 bind-test-child1 {
430 compatible = "sandbox,phy";
431 #phy-cells = <1>;
432 };
433
434 bind-test-child2 {
435 compatible = "simple-bus";
436 };
437 };
438
Simon Glassb2c1cac2014-02-26 15:59:21 -0700439 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600440 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700441 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600442 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700443 ping-add = <3>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530444
445 mux-controls = <&muxcontroller0 0>;
446 mux-control-names = "mux0";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700447 };
448
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200449 phy_provider0: gen_phy@0 {
450 compatible = "sandbox,phy";
451 #phy-cells = <1>;
452 };
453
454 phy_provider1: gen_phy@1 {
455 compatible = "sandbox,phy";
456 #phy-cells = <0>;
457 broken;
458 };
459
developer71092972020-05-02 11:35:12 +0200460 phy_provider2: gen_phy@2 {
461 compatible = "sandbox,phy";
462 #phy-cells = <0>;
463 };
464
Jonas Karlman9f89e682023-08-31 22:16:35 +0000465 phy_provider3: gen_phy@3 {
466 compatible = "sandbox,phy";
467 #phy-cells = <2>;
468 };
469
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200470 gen_phy_user: gen_phy_user {
471 compatible = "simple-bus";
472 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
473 phy-names = "phy1", "phy2", "phy3";
474 };
475
developer71092972020-05-02 11:35:12 +0200476 gen_phy_user1: gen_phy_user1 {
477 compatible = "simple-bus";
478 phys = <&phy_provider0 0>, <&phy_provider2>;
479 phy-names = "phy1", "phy2";
480 };
481
Jonas Karlman9f89e682023-08-31 22:16:35 +0000482 gen_phy_user2: gen_phy_user2 {
483 compatible = "simple-bus";
484 phys = <&phy_provider3 0 0>;
485 phy-names = "phy1";
486 };
487
Simon Glassb2c1cac2014-02-26 15:59:21 -0700488 some-bus {
489 #address-cells = <1>;
490 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600491 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600492 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600493 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700494 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600495 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700496 compatible = "denx,u-boot-fdt-test";
497 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600498 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700499 ping-add = <5>;
500 };
Simon Glass40717422014-07-23 06:55:18 -0600501 c-test@0 {
502 compatible = "denx,u-boot-fdt-test";
503 reg = <0>;
504 ping-expect = <6>;
505 ping-add = <6>;
506 };
507 c-test@1 {
508 compatible = "denx,u-boot-fdt-test";
509 reg = <1>;
510 ping-expect = <7>;
511 ping-add = <7>;
512 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700513 };
514
515 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600516 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600517 ping-expect = <6>;
518 ping-add = <6>;
519 compatible = "google,another-fdt-test";
520 };
521
522 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600523 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600524 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700525 ping-add = <6>;
526 compatible = "google,another-fdt-test";
527 };
528
Simon Glass0ccb0972015-01-25 08:27:05 -0700529 f-test {
530 compatible = "denx,u-boot-fdt-test";
531 };
532
533 g-test {
534 compatible = "denx,u-boot-fdt-test";
535 };
536
Bin Mengd9d24782018-10-10 22:07:01 -0700537 h-test {
538 compatible = "denx,u-boot-fdt-test1";
539 };
540
developercf8bc132020-05-02 11:35:10 +0200541 i-test {
542 compatible = "mediatek,u-boot-fdt-test";
543 #address-cells = <1>;
544 #size-cells = <0>;
545
546 subnode@0 {
547 reg = <0>;
548 };
549
550 subnode@1 {
551 reg = <1>;
552 };
553
554 subnode@2 {
555 reg = <2>;
556 };
557 };
558
Simon Glass204675c2019-12-29 21:19:25 -0700559 devres-test {
560 compatible = "denx,u-boot-devres-test";
561 };
562
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530563 another-test {
564 reg = <0 2>;
565 compatible = "denx,u-boot-fdt-test";
566 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
567 test5-gpios = <&gpio_a 19>;
568 };
569
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100570 mmio-bus@0 {
571 #address-cells = <1>;
572 #size-cells = <1>;
573 compatible = "denx,u-boot-test-bus";
574 dma-ranges = <0x10000000 0x00000000 0x00040000>;
575
576 subnode@0 {
577 compatible = "denx,u-boot-fdt-test";
578 };
579 };
580
581 mmio-bus@1 {
582 #address-cells = <1>;
583 #size-cells = <1>;
584 compatible = "denx,u-boot-test-bus";
Nicolas Saenz Julienne892e9b42021-01-12 13:55:25 +0100585
586 subnode@0 {
587 compatible = "denx,u-boot-fdt-test";
588 };
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100589 };
590
Simon Glass3c601b12020-07-07 13:12:06 -0600591 acpi_test1: acpi-test {
Simon Glass2d67fdf2020-04-08 16:57:34 -0600592 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600593 acpi-ssdt-test-data = "ab";
Simon Glass990cd5b2020-07-07 13:12:08 -0600594 acpi-dsdt-test-data = "hi";
Simon Glassebb2e832020-07-07 13:11:39 -0600595 child {
596 compatible = "denx,u-boot-acpi-test";
597 };
Simon Glass2d67fdf2020-04-08 16:57:34 -0600598 };
599
Simon Glass3c601b12020-07-07 13:12:06 -0600600 acpi_test2: acpi-test2 {
Simon Glass17968c32020-04-26 09:19:46 -0600601 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600602 acpi-ssdt-test-data = "cd";
Simon Glass990cd5b2020-07-07 13:12:08 -0600603 acpi-dsdt-test-data = "jk";
Simon Glass17968c32020-04-26 09:19:46 -0600604 };
605
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200606 clocks {
607 clk_fixed: clk-fixed {
608 compatible = "fixed-clock";
609 #clock-cells = <0>;
610 clock-frequency = <1234>;
611 };
Anup Patel8d28c3c2019-02-25 08:14:55 +0000612
613 clk_fixed_factor: clk-fixed-factor {
614 compatible = "fixed-factor-clock";
615 #clock-cells = <0>;
616 clock-div = <3>;
617 clock-mult = <2>;
618 clocks = <&clk_fixed>;
619 };
Lukasz Majewskiccafcdd2019-06-24 15:50:47 +0200620
621 osc {
622 compatible = "fixed-clock";
623 #clock-cells = <0>;
624 clock-frequency = <20000000>;
625 };
Stephen Warrena9622432016-06-17 09:44:00 -0600626 };
627
628 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600629 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600630 #clock-cells = <1>;
Jean-Jacques Hiblotc1e9c942019-10-22 14:00:07 +0200631 assigned-clocks = <&clk_sandbox 3>;
632 assigned-clock-rates = <321>;
Stephen Warrena9622432016-06-17 09:44:00 -0600633 };
634
635 clk-test {
636 compatible = "sandbox,clk-test";
637 clocks = <&clk_fixed>,
638 <&clk_sandbox 1>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200639 <&clk_sandbox 0>,
Yang Xiwene89289c2023-12-16 02:28:52 +0800640 <&ccf 11>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200641 <&clk_sandbox 3>,
642 <&clk_sandbox 2>;
Yang Xiwene89289c2023-12-16 02:28:52 +0800643 clock-names = "fixed", "i2c", "spi", "i2c_root", "uart2", "uart1";
Simon Glass8cc4d822015-07-06 12:54:24 -0600644 };
645
Ashok Reddy Soma8f03cef2023-08-30 10:31:42 +0200646 clk-test2 {
647 compatible = "sandbox,clk-test";
648 assigned-clock-rates = <321>;
649 };
650
651 clk-test3 {
652 compatible = "sandbox,clk-test";
653 assigned-clocks = <&clk_sandbox 1>;
654 };
655
656 clk-test4 {
657 compatible = "sandbox,clk-test";
658 assigned-clock-rates = <654>, <321>;
659 assigned-clocks = <&clk_sandbox 1>;
660 };
661
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200662 ccf: clk-ccf {
663 compatible = "sandbox,clk-ccf";
Yang Xiwene89289c2023-12-16 02:28:52 +0800664 #clock-cells = <1>;
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200665 };
666
Simon Glass507ab962021-12-04 08:56:31 -0700667 efi-media {
668 compatible = "sandbox,efi-media";
669 };
670
Simon Glass5b968632015-05-22 15:42:15 -0600671 eth@10002000 {
672 compatible = "sandbox,eth";
673 reg = <0x10002000 0x1000>;
Simon Glass5b968632015-05-22 15:42:15 -0600674 };
675
676 eth_5: eth@10003000 {
677 compatible = "sandbox,eth";
678 reg = <0x10003000 0x1000>;
Sean Anderson13652b82022-05-05 13:11:44 -0400679 nvmem-cells = <&eth5_addr>;
680 nvmem-cell-names = "mac-address";
Simon Glass5b968632015-05-22 15:42:15 -0600681 };
682
Bin Meng04a11cb2015-08-27 22:25:53 -0700683 eth_3: sbe5 {
684 compatible = "sandbox,eth";
685 reg = <0x10005000 0x1000>;
Sean Andersone2dc0e62022-05-05 13:11:42 -0400686 nvmem-cells = <&eth3_addr>;
687 nvmem-cell-names = "mac-address";
Bin Meng04a11cb2015-08-27 22:25:53 -0700688 };
689
Simon Glass5b968632015-05-22 15:42:15 -0600690 eth@10004000 {
691 compatible = "sandbox,eth";
692 reg = <0x10004000 0x1000>;
Simon Glass5b968632015-05-22 15:42:15 -0600693 };
694
Marek Behúnf4f1ddc2022-04-07 00:32:57 +0200695 phy_eth0: phy-test-eth {
696 compatible = "sandbox,eth";
697 reg = <0x10007000 0x1000>;
Sean Anderson24b1b8d2022-05-05 13:11:35 -0400698 mac-address = [ 02 00 11 22 33 49 ];
Marek Behúnf4f1ddc2022-04-07 00:32:57 +0200699 phy-handle = <&ethphy1>;
Marek Behúnbc194772022-04-07 00:33:01 +0200700 phy-mode = "2500base-x";
Marek Behúnf4f1ddc2022-04-07 00:32:57 +0200701 };
702
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800703 dsa_eth0: dsa-test-eth {
704 compatible = "sandbox,eth";
705 reg = <0x10006000 0x1000>;
Sean Anderson5768e8b2022-05-05 13:11:43 -0400706 nvmem-cells = <&eth4_addr>;
707 nvmem-cell-names = "mac-address";
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800708 };
709
710 dsa-test {
711 compatible = "sandbox,dsa";
712
713 ports {
714 #address-cells = <1>;
715 #size-cells = <0>;
716 swp_0: port@0 {
717 reg = <0>;
718 label = "lan0";
719 phy-mode = "rgmii-rxid";
720
721 fixed-link {
722 speed = <100>;
723 full-duplex;
724 };
725 };
726
727 swp_1: port@1 {
728 reg = <1>;
729 label = "lan1";
730 phy-mode = "rgmii-txid";
Bin Meng381ed972021-03-14 20:14:58 +0800731 fixed-link = <0 1 100 0 0>;
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800732 };
733
734 port@2 {
735 reg = <2>;
736 ethernet = <&dsa_eth0>;
737
738 fixed-link {
739 speed = <1000>;
740 full-duplex;
741 };
742 };
743 };
744 };
745
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700746 firmware {
747 sandbox_firmware: sandbox-firmware {
748 compatible = "sandbox,firmware";
749 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200750
Etienne Carriere09665cb2022-02-21 09:22:39 +0100751 scmi {
Etienne Carriere02fd1262020-09-09 18:44:00 +0200752 compatible = "sandbox,scmi-agent";
753 #address-cells = <1>;
754 #size-cells = <0>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200755
AKASHI Takahiro535a7bd2023-10-16 14:39:45 +0900756 pwrdom_scmi: protocol@11 {
757 reg = <0x11>;
758 #power-domain-cells = <1>;
759 };
760
Etienne Carriere09665cb2022-02-21 09:22:39 +0100761 clk_scmi: protocol@14 {
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200762 reg = <0x14>;
763 #clock-cells = <1>;
AKASHI Takahirocc4ecda2023-10-11 19:06:59 +0900764 linaro,sandbox-channel-id = <0x14>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200765 };
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200766
Etienne Carriere09665cb2022-02-21 09:22:39 +0100767 reset_scmi: protocol@16 {
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200768 reg = <0x16>;
769 #reset-cells = <1>;
770 };
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100771
772 protocol@17 {
773 reg = <0x17>;
774
775 regulators {
776 #address-cells = <1>;
777 #size-cells = <0>;
778
Etienne Carriere09665cb2022-02-21 09:22:39 +0100779 regul0_scmi: reg@0 {
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100780 reg = <0>;
781 regulator-name = "sandbox-voltd0";
782 regulator-min-microvolt = <1100000>;
783 regulator-max-microvolt = <3300000>;
784 };
Etienne Carriere09665cb2022-02-21 09:22:39 +0100785 regul1_scmi: reg@1 {
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100786 reg = <0x1>;
787 regulator-name = "sandbox-voltd1";
788 regulator-min-microvolt = <1800000>;
789 };
790 };
791 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200792 };
Alexey Romanov9dc617d2023-09-21 11:13:36 +0300793
794 sm: secure-monitor {
795 compatible = "sandbox,sm";
796 };
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700797 };
798
Alexander Dahl6ac319d2022-09-30 14:04:30 +0200799 fpga {
800 compatible = "sandbox,fpga";
801 };
802
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100803 pinctrl-gpio {
804 compatible = "sandbox,pinctrl-gpio";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700805
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100806 gpio_a: base-gpios {
807 compatible = "sandbox,gpio";
808 gpio-controller;
809 #gpio-cells = <1>;
810 gpio-bank-name = "a";
811 sandbox,gpio-count = <20>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200812 hog_input_active_low {
813 gpio-hog;
814 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200815 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200816 };
817 hog_input_active_high {
818 gpio-hog;
819 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200820 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200821 };
822 hog_output_low {
823 gpio-hog;
824 output-low;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200825 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200826 };
827 hog_output_high {
828 gpio-hog;
829 output-high;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200830 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200831 };
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100832 };
833
834 gpio_b: extra-gpios {
835 compatible = "sandbox,gpio";
836 gpio-controller;
837 #gpio-cells = <5>;
838 gpio-bank-name = "b";
839 sandbox,gpio-count = <10>;
840 };
Simon Glass25348a42014-10-13 23:42:11 -0600841
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100842 gpio_c: pinmux-gpios {
843 compatible = "sandbox,gpio";
844 gpio-controller;
845 #gpio-cells = <2>;
846 gpio-bank-name = "c";
847 sandbox,gpio-count = <10>;
848 };
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100849 };
850
Simon Glass7df766e2014-12-10 08:55:55 -0700851 i2c@0 {
852 #address-cells = <1>;
853 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600854 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700855 compatible = "sandbox,i2c";
856 clock-frequency = <100000>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200857 pinctrl-names = "default";
858 pinctrl-0 = <&pinmux_i2c0_pins>;
859
Simon Glass7df766e2014-12-10 08:55:55 -0700860 eeprom@2c {
Sean Andersone2dc0e62022-05-05 13:11:42 -0400861 #address-cells = <1>;
862 #size-cells = <1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700863 reg = <0x2c>;
864 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700865 sandbox,emul = <&emul_eeprom>;
Michal Simek4f18f922020-05-28 11:48:55 +0200866 partitions {
867 compatible = "fixed-partitions";
868 #address-cells = <1>;
869 #size-cells = <1>;
870 bootcount_i2c: bootcount@10 {
871 reg = <10 2>;
872 };
873 };
Sean Andersone2dc0e62022-05-05 13:11:42 -0400874
875 eth3_addr: mac-address@24 {
876 reg = <24 6>;
877 };
Simon Glass7df766e2014-12-10 08:55:55 -0700878 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200879
Simon Glass336b2952015-05-22 15:42:17 -0600880 rtc_0: rtc@43 {
Sean Anderson5768e8b2022-05-05 13:11:43 -0400881 #address-cells = <1>;
882 #size-cells = <1>;
Simon Glass336b2952015-05-22 15:42:17 -0600883 reg = <0x43>;
884 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700885 sandbox,emul = <&emul0>;
Sean Anderson5768e8b2022-05-05 13:11:43 -0400886
887 eth4_addr: mac-address@40 {
888 reg = <0x40 6>;
889 };
Simon Glass336b2952015-05-22 15:42:17 -0600890 };
891
892 rtc_1: rtc@61 {
893 reg = <0x61>;
894 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700895 sandbox,emul = <&emul1>;
896 };
897
898 i2c_emul: emul {
899 reg = <0xff>;
900 compatible = "sandbox,i2c-emul-parent";
901 emul_eeprom: emul-eeprom {
902 compatible = "sandbox,i2c-eeprom";
903 sandbox,filename = "i2c.bin";
904 sandbox,size = <256>;
905 };
906 emul0: emul0 {
Simon Glass98af3742021-02-03 06:01:17 -0700907 compatible = "sandbox,i2c-rtc-emul";
Simon Glass17b56f62018-11-18 08:14:34 -0700908 };
909 emul1: emull {
Simon Glass98af3742021-02-03 06:01:17 -0700910 compatible = "sandbox,i2c-rtc-emul";
Simon Glass336b2952015-05-22 15:42:17 -0600911 };
912 };
913
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200914 sandbox_pmic: sandbox_pmic {
915 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700916 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200917 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200918
919 mc34708: pmic@41 {
920 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700921 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200922 };
Simon Glass7df766e2014-12-10 08:55:55 -0700923 };
924
Philipp Tomsich1fc53302018-12-14 21:14:29 +0100925 bootcount@0 {
926 compatible = "u-boot,bootcount-rtc";
927 rtc = <&rtc_1>;
928 offset = <0x13>;
929 };
930
Michal Simek4f18f922020-05-28 11:48:55 +0200931 bootcount {
932 compatible = "u-boot,bootcount-i2c-eeprom";
933 i2c-eeprom = <&bootcount_i2c>;
934 };
935
Nandor Han88895812021-06-10 15:40:38 +0300936 bootcount_4@0 {
937 compatible = "u-boot,bootcount-syscon";
938 syscon = <&syscon0>;
939 reg = <0x0 0x04>, <0x0 0x04>;
940 reg-names = "syscon_reg", "offset";
941 };
942
943 bootcount_2@0 {
944 compatible = "u-boot,bootcount-syscon";
945 syscon = <&syscon0>;
946 reg = <0x0 0x04>, <0x0 0x02> ;
947 reg-names = "syscon_reg", "offset";
948 };
949
Marek Szyprowskiad398592021-02-18 11:33:18 +0100950 adc: adc@0 {
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100951 compatible = "sandbox,adc";
Marek Szyprowskiad398592021-02-18 11:33:18 +0100952 #io-channel-cells = <1>;
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100953 vdd-supply = <&buck2>;
954 vss-microvolts = <0>;
955 };
956
Mark Kettenis67748ee2021-10-23 16:58:02 +0200957 iommu: iommu@0 {
958 compatible = "sandbox,iommu";
959 #iommu-cells = <0>;
960 };
961
Simon Glass515dcff2020-02-06 09:55:00 -0700962 irq: irq {
Simon Glass54028bc2019-12-06 21:41:59 -0700963 compatible = "sandbox,irq";
Simon Glass515dcff2020-02-06 09:55:00 -0700964 interrupt-controller;
965 #interrupt-cells = <2>;
Simon Glass54028bc2019-12-06 21:41:59 -0700966 };
967
Simon Glass90b6fef2016-01-18 19:52:26 -0700968 lcd {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700969 bootph-all;
Simon Glass90b6fef2016-01-18 19:52:26 -0700970 compatible = "sandbox,lcd-sdl";
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200971 pinctrl-names = "default";
972 pinctrl-0 = <&pinmux_lcd_pins>;
Simon Glass90b6fef2016-01-18 19:52:26 -0700973 xres = <1366>;
974 yres = <768>;
975 };
976
Simon Glassd783eb32015-07-06 12:54:34 -0600977 leds {
978 compatible = "gpio-leds";
979
980 iracibble {
981 gpios = <&gpio_a 1 0>;
982 label = "sandbox:red";
983 };
984
985 martinet {
986 gpios = <&gpio_a 2 0>;
987 label = "sandbox:green";
988 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200989
990 default_on {
991 gpios = <&gpio_a 5 0>;
992 label = "sandbox:default_on";
993 default-state = "on";
994 };
995
996 default_off {
997 gpios = <&gpio_a 6 0>;
Sean Andersonfbf8d652020-09-14 11:02:03 -0400998 /* label intentionally omitted */
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200999 default-state = "off";
1000 };
Simon Glassd783eb32015-07-06 12:54:34 -06001001 };
1002
Paul Doelle709f0372022-07-04 09:00:25 +00001003 wdt-gpio-toggle {
Simon Glasse0f8cd22023-08-10 09:53:13 -06001004 gpios = <&gpio_a 8 0>;
Rasmus Villemoes2b673872021-08-19 11:57:05 +02001005 compatible = "linux,wdt-gpio";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +02001006 hw_margin_ms = <100>;
Paul Doelle709f0372022-07-04 09:00:25 +00001007 hw_algo = "toggle";
1008 always-running;
1009 };
1010
1011 wdt-gpio-level {
1012 gpios = <&gpio_a 7 0>;
1013 compatible = "linux,wdt-gpio";
1014 hw_margin_ms = <100>;
1015 hw_algo = "level";
Rasmus Villemoes2b673872021-08-19 11:57:05 +02001016 always-running;
1017 };
1018
Stephen Warren62f2c902016-05-16 17:41:37 -06001019 mbox: mbox {
1020 compatible = "sandbox,mbox";
1021 #mbox-cells = <1>;
1022 };
1023
1024 mbox-test {
1025 compatible = "sandbox,mbox-test";
1026 mboxes = <&mbox 100>, <&mbox 1>;
1027 mbox-names = "other", "test";
1028 };
1029
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001030 cpus {
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +02001031 #address-cells = <1>;
1032 #size-cells = <0>;
Sean Anderson79d3bba2020-09-28 10:52:23 -04001033 timebase-frequency = <2000000>;
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +02001034 cpu1: cpu@1 {
1035 device_type = "cpu";
1036 reg = <0x1>;
Sean Anderson79d3bba2020-09-28 10:52:23 -04001037 timebase-frequency = <3000000>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001038 compatible = "sandbox,cpu_sandbox";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001039 bootph-all;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001040 };
Mario Sixdea5df72018-08-06 10:23:44 +02001041
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +02001042 cpu2: cpu@2 {
1043 device_type = "cpu";
1044 reg = <0x2>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001045 compatible = "sandbox,cpu_sandbox";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001046 bootph-all;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001047 };
Mario Sixdea5df72018-08-06 10:23:44 +02001048
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +02001049 cpu3: cpu@3 {
1050 device_type = "cpu";
1051 reg = <0x3>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001052 compatible = "sandbox,cpu_sandbox";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001053 bootph-all;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001054 };
Mario Sixdea5df72018-08-06 10:23:44 +02001055 };
1056
Dave Gerlach75dbdfc2020-07-15 23:39:58 -05001057 chipid: chipid {
1058 compatible = "sandbox,soc";
1059 };
1060
Simon Glassc953aaf2018-12-10 10:37:34 -07001061 i2s: i2s {
1062 compatible = "sandbox,i2s";
1063 #sound-dai-cells = <1>;
Simon Glass4d5814c2019-02-16 20:24:56 -07001064 sandbox,silent; /* Don't emit sounds while testing */
Simon Glassc953aaf2018-12-10 10:37:34 -07001065 };
1066
Jean-Jacques Hiblotdb97c7f2019-07-05 09:33:57 +02001067 nop-test_0 {
1068 compatible = "sandbox,nop_sandbox1";
1069 nop-test_1 {
1070 compatible = "sandbox,nop_sandbox2";
1071 bind = "True";
1072 };
1073 nop-test_2 {
1074 compatible = "sandbox,nop_sandbox2";
1075 bind = "False";
1076 };
1077 };
1078
Roger Quadrosb0679a72022-10-20 16:30:46 +03001079 memory-controller {
1080 compatible = "sandbox,memory";
1081 };
1082
Mario Sixa8ce0ee2018-07-31 14:24:14 +02001083 misc-test {
Sean Anderson13652b82022-05-05 13:11:44 -04001084 #address-cells = <1>;
1085 #size-cells = <1>;
Mario Sixa8ce0ee2018-07-31 14:24:14 +02001086 compatible = "sandbox,misc_sandbox";
Sean Anderson13652b82022-05-05 13:11:44 -04001087
1088 eth5_addr: mac-address@10 {
1089 reg = <0x10 6>;
1090 };
Mario Sixa8ce0ee2018-07-31 14:24:14 +02001091 };
1092
Simon Glasse4fef742017-04-23 20:02:07 -06001093 mmc2 {
1094 compatible = "sandbox,mmc";
Simon Glass965cd402021-07-05 16:32:58 -06001095 non-removable;
Simon Glasse4fef742017-04-23 20:02:07 -06001096 };
1097
Simon Glassb255efc2022-04-24 23:31:24 -06001098 /* This is used for the bootdev tests */
Simon Glasse4fef742017-04-23 20:02:07 -06001099 mmc1 {
1100 compatible = "sandbox,mmc";
Simon Glassb255efc2022-04-24 23:31:24 -06001101 filename = "mmc1.img";
Simon Glasse4fef742017-04-23 20:02:07 -06001102 };
1103
Simon Glassb255efc2022-04-24 23:31:24 -06001104 /* This is used for the fastboot tests */
Sughosh Ganu77079e72022-10-21 18:16:05 +05301105 mmc0: mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -06001106 compatible = "sandbox,mmc";
1107 };
1108
Simon Glassf1eba352022-10-20 18:23:20 -06001109 /* This is used for VBE VPL tests */
1110 mmc3 {
1111 status = "disabled";
1112 compatible = "sandbox,mmc";
1113 filename = "image.bin";
1114 non-removable;
1115 };
1116
Simon Glassd2bc33ed2023-01-06 08:52:41 -06001117 /* This is used for bootstd bootmenu tests */
1118 mmc4 {
1119 status = "disabled";
1120 compatible = "sandbox,mmc";
1121 filename = "mmc4.img";
1122 };
1123
Simon Glassfff928c2023-08-24 13:55:41 -06001124 /* This is used for ChromiumOS tests */
1125 mmc5 {
1126 status = "disabled";
1127 compatible = "sandbox,mmc";
1128 filename = "mmc5.img";
1129 };
1130
Alexander Gendin038cb022023-10-09 01:24:36 +00001131 /* This is used for mbr tests */
1132 mmc6 {
1133 status = "disabled";
1134 compatible = "sandbox,mmc";
1135 filename = "mmc6.img";
1136 };
1137
Mattijs Korpershoekd77f8152024-07-10 10:40:06 +02001138 /* This is used for Android tests */
1139 mmc7 {
1140 status = "disabled";
1141 compatible = "sandbox,mmc";
1142 filename = "mmc7.img";
1143 };
1144
Simon Glass53a68b32019-02-16 20:24:50 -07001145 pch {
1146 compatible = "sandbox,pch";
1147 };
1148
Tom Rini4a3ca482020-02-11 12:41:23 -05001149 pci0: pci@0 {
Simon Glass3a6eae62015-03-05 12:25:34 -07001150 compatible = "sandbox,pci";
1151 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001152 bus-range = <0x00 0xff>;
Simon Glass3a6eae62015-03-05 12:25:34 -07001153 #address-cells = <3>;
1154 #size-cells = <2>;
Simon Glass35464f72019-09-25 08:56:08 -06001155 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glass3a6eae62015-03-05 12:25:34 -07001156 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Mark Kettenis5dfd4ec2023-01-21 20:27:57 +01001157 iommu-map = <0x0010 &iommu 0 1>;
1158 iommu-map-mask = <0xfffffff8>;
Bin Mengcbf071b2018-08-03 01:14:39 -07001159 pci@0,0 {
1160 compatible = "pci-generic";
1161 reg = <0x0000 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001162 sandbox,emul = <&swap_case_emul0_0>;
Bin Mengcbf071b2018-08-03 01:14:39 -07001163 };
Alex Margineanf1274432019-06-07 11:24:24 +03001164 pci@1,0 {
1165 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -06001166 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
Simon Glass4289c262023-09-26 08:14:58 -06001167 reg = <0x02000814 0 0 0x80 0
1168 0x01000810 0 0 0xc0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001169 sandbox,emul = <&swap_case_emul0_1>;
Alex Margineanf1274432019-06-07 11:24:24 +03001170 };
Simon Glass937bb472019-12-06 21:41:57 -07001171 p2sb-pci@2,0 {
1172 compatible = "sandbox,p2sb";
1173 reg = <0x02001010 0 0 0 0>;
1174 sandbox,emul = <&p2sb_emul>;
1175
1176 adder {
1177 intel,p2sb-port-id = <3>;
1178 compatible = "sandbox,adder";
1179 };
1180 };
Simon Glass8c501022019-12-06 21:41:54 -07001181 pci@1e,0 {
1182 compatible = "sandbox,pmc";
1183 reg = <0xf000 0 0 0 0>;
1184 sandbox,emul = <&pmc_emul1e>;
1185 acpi-base = <0x400>;
1186 gpe0-dwx-mask = <0xf>;
1187 gpe0-dwx-shift-base = <4>;
1188 gpe0-dw = <6 7 9>;
1189 gpe0-sts = <0x20>;
1190 gpe0-en = <0x30>;
1191 };
Simon Glass3a6eae62015-03-05 12:25:34 -07001192 pci@1f,0 {
1193 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -06001194 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
Simon Glass4289c262023-09-26 08:14:58 -06001195 reg = <0x0100f810 0 0 0x100 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001196 sandbox,emul = <&swap_case_emul0_1f>;
Simon Glass3a6eae62015-03-05 12:25:34 -07001197 };
1198 };
1199
Simon Glassb98ba4c2019-09-25 08:56:10 -06001200 pci-emul0 {
1201 compatible = "sandbox,pci-emul-parent";
1202 swap_case_emul0_0: emul0@0,0 {
1203 compatible = "sandbox,swap-case";
1204 };
1205 swap_case_emul0_1: emul0@1,0 {
1206 compatible = "sandbox,swap-case";
1207 use-ea;
1208 };
1209 swap_case_emul0_1f: emul0@1f,0 {
1210 compatible = "sandbox,swap-case";
1211 };
Simon Glass937bb472019-12-06 21:41:57 -07001212 p2sb_emul: emul@2,0 {
1213 compatible = "sandbox,p2sb-emul";
1214 };
Simon Glass8c501022019-12-06 21:41:54 -07001215 pmc_emul1e: emul@1e,0 {
1216 compatible = "sandbox,pmc-emul";
1217 };
Simon Glassb98ba4c2019-09-25 08:56:10 -06001218 };
1219
Tom Rini4a3ca482020-02-11 12:41:23 -05001220 pci1: pci@1 {
Bin Meng408e5902018-08-03 01:14:41 -07001221 compatible = "sandbox,pci";
1222 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001223 bus-range = <0x00 0xff>;
Bin Meng408e5902018-08-03 01:14:41 -07001224 #address-cells = <3>;
1225 #size-cells = <2>;
Suneel Garapati3ac3aec2019-10-19 17:10:20 -07001226 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
Andrew Scullc7456a42022-04-21 16:11:09 +00001227 0x02000000 0 0x31000000 0x3e000000 0 0x2000 // MEM1
Suneel Garapati3ac3aec2019-10-19 17:10:20 -07001228 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -07001229 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +02001230 0x0c 0x00 0x1234 0x5678
1231 0x10 0x00 0x1234 0x5678>;
1232 pci@10,0 {
1233 reg = <0x8000 0 0 0 0>;
1234 };
Bin Meng408e5902018-08-03 01:14:41 -07001235 };
1236
Tom Rini4a3ca482020-02-11 12:41:23 -05001237 pci2: pci@2 {
Bin Meng510dddb2018-08-03 01:14:50 -07001238 compatible = "sandbox,pci";
1239 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001240 bus-range = <0x00 0xff>;
Bin Meng510dddb2018-08-03 01:14:50 -07001241 #address-cells = <3>;
1242 #size-cells = <2>;
1243 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
1244 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
1245 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
1246 pci@1f,0 {
1247 compatible = "pci-generic";
1248 reg = <0xf800 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001249 sandbox,emul = <&swap_case_emul2_1f>;
1250 };
1251 };
1252
1253 pci-emul2 {
1254 compatible = "sandbox,pci-emul-parent";
1255 swap_case_emul2_1f: emul2@1f,0 {
1256 compatible = "sandbox,swap-case";
Bin Meng510dddb2018-08-03 01:14:50 -07001257 };
1258 };
1259
Ramon Friedc64f19b2019-04-27 11:15:23 +03001260 pci_ep: pci_ep {
1261 compatible = "sandbox,pci_ep";
1262 };
1263
Simon Glass9c433fe2017-04-23 20:10:44 -06001264 probing {
1265 compatible = "simple-bus";
1266 test1 {
1267 compatible = "denx,u-boot-probe-test";
1268 };
1269
1270 test2 {
1271 compatible = "denx,u-boot-probe-test";
1272 };
1273
1274 test3 {
1275 compatible = "denx,u-boot-probe-test";
1276 };
1277
1278 test4 {
1279 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001280 first-syscon = <&syscon0>;
1281 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunayee010432019-03-07 09:57:13 +01001282 third-syscon = <&syscon2>;
Simon Glass9c433fe2017-04-23 20:10:44 -06001283 };
1284 };
1285
Stephen Warren92c67fa2016-07-13 13:45:31 -06001286 pwrdom: power-domain {
1287 compatible = "sandbox,power-domain";
1288 #power-domain-cells = <1>;
1289 };
1290
1291 power-domain-test {
1292 compatible = "sandbox,power-domain-test";
1293 power-domains = <&pwrdom 2>;
1294 };
1295
Simon Glass5620cf82018-10-01 12:22:40 -06001296 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -06001297 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001298 #pwm-cells = <2>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001299 pinctrl-names = "default";
1300 pinctrl-0 = <&pinmux_pwm_pins>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001301 };
1302
1303 pwm2 {
1304 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001305 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001306 };
1307
Simon Glass3d355e62015-07-06 12:54:31 -06001308 ram {
1309 compatible = "sandbox,ram";
1310 };
1311
Simon Glassd860f222015-07-06 12:54:29 -06001312 reset@0 {
1313 compatible = "sandbox,warm-reset";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001314 bootph-some-ram;
Simon Glassd860f222015-07-06 12:54:29 -06001315 };
1316
1317 reset@1 {
1318 compatible = "sandbox,reset";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001319 bootph-some-ram;
Simon Glassd860f222015-07-06 12:54:29 -06001320 };
1321
Stephen Warren6488e642016-06-17 09:43:59 -06001322 resetc: reset-ctl {
1323 compatible = "sandbox,reset-ctl";
1324 #reset-cells = <1>;
1325 };
1326
1327 reset-ctl-test {
1328 compatible = "sandbox,reset-ctl-test";
Neil Armstrong9b4cdef2021-04-20 10:42:25 +02001329 resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>;
1330 reset-names = "other", "test", "test2", "test3";
Stephen Warren6488e642016-06-17 09:43:59 -06001331 };
1332
Sughosh Ganu23e37512019-12-28 23:58:31 +05301333 rng {
1334 compatible = "sandbox,sandbox-rng";
1335 };
1336
Nishanth Menonedf85812015-09-17 15:42:41 -05001337 rproc_1: rproc@1 {
1338 compatible = "sandbox,test-processor";
1339 remoteproc-name = "remoteproc-test-dev1";
1340 };
1341
1342 rproc_2: rproc@2 {
1343 compatible = "sandbox,test-processor";
1344 internal-memory-mapped;
1345 remoteproc-name = "remoteproc-test-dev2";
1346 };
1347
Simon Glass5620cf82018-10-01 12:22:40 -06001348 panel {
1349 compatible = "simple-panel";
1350 backlight = <&backlight 0 100>;
1351 };
1352
Simon Glass509f32e2022-09-21 16:21:47 +02001353 scsi {
1354 compatible = "sandbox,scsi";
1355 sandbox,filepath = "scsi.img";
1356 };
1357
Ramon Fried26ed32e2018-07-02 02:57:59 +03001358 smem@0 {
1359 compatible = "sandbox,smem";
1360 };
1361
Simon Glass76072ac2018-12-10 10:37:36 -07001362 sound {
1363 compatible = "sandbox,sound";
1364 cpu {
1365 sound-dai = <&i2s 0>;
1366 };
1367
1368 codec {
1369 sound-dai = <&audio 0>;
1370 };
1371 };
1372
Simon Glass25348a42014-10-13 23:42:11 -06001373 spi@0 {
1374 #address-cells = <1>;
1375 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -06001376 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -06001377 compatible = "sandbox,spi";
Ovidiu Panaitae734732020-12-14 19:06:47 +02001378 cs-gpios = <0>, <0>, <&gpio_a 0>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001379 pinctrl-names = "default";
1380 pinctrl-0 = <&pinmux_spi0_pins>;
1381
Simon Glass25348a42014-10-13 23:42:11 -06001382 spi.bin@0 {
1383 reg = <0>;
Neil Armstronga009fa72019-02-10 10:16:20 +00001384 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass25348a42014-10-13 23:42:11 -06001385 spi-max-frequency = <40000000>;
1386 sandbox,filename = "spi.bin";
1387 };
Ovidiu Panaitae734732020-12-14 19:06:47 +02001388 spi.bin@1 {
1389 reg = <1>;
1390 compatible = "spansion,m25p16", "jedec,spi-nor";
1391 spi-max-frequency = <50000000>;
1392 sandbox,filename = "spi.bin";
1393 spi-cpol;
1394 spi-cpha;
1395 };
Simon Glass25348a42014-10-13 23:42:11 -06001396 };
1397
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001398 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -06001399 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +02001400 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -06001401 };
1402
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001403 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -06001404 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -06001405 reg = <0x20 5
1406 0x28 6
1407 0x30 7
1408 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -06001409 };
1410
Patrick Delaunayee010432019-03-07 09:57:13 +01001411 syscon2: syscon@2 {
Masahiro Yamada42ab1072018-04-23 13:26:53 +09001412 compatible = "simple-mfd", "syscon";
1413 reg = <0x40 5
1414 0x48 6
1415 0x50 7
1416 0x58 8>;
1417 };
1418
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +05301419 syscon3: syscon@3 {
1420 compatible = "simple-mfd", "syscon";
1421 reg = <0x000100 0x10>;
1422
1423 muxcontroller0: a-mux-controller {
1424 compatible = "mmio-mux";
1425 #mux-control-cells = <1>;
1426
1427 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
1428 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
1429 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
1430 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
1431 u-boot,mux-autoprobe;
1432 };
1433 };
1434
1435 muxcontroller1: emul-mux-controller {
1436 compatible = "mux-emul";
1437 #mux-control-cells = <0>;
1438 u-boot,mux-autoprobe;
1439 idle-state = <0xabcd>;
1440 };
1441
Simon Glass791a17f2020-12-16 21:20:27 -07001442 testfdtm0 {
1443 compatible = "denx,u-boot-fdtm-test";
1444 };
1445
1446 testfdtm1: testfdtm1 {
1447 compatible = "denx,u-boot-fdtm-test";
1448 };
1449
1450 testfdtm2 {
1451 compatible = "denx,u-boot-fdtm-test";
1452 };
1453
Sean Anderson79d3bba2020-09-28 10:52:23 -04001454 timer@0 {
Thomas Chou6f2cfbf2015-12-11 16:27:34 +08001455 compatible = "sandbox,timer";
1456 clock-frequency = <1000000>;
1457 };
1458
Sean Anderson79d3bba2020-09-28 10:52:23 -04001459 timer@1 {
1460 compatible = "sandbox,timer";
1461 sandbox,timebase-frequency-fallback;
1462 };
1463
Miquel Raynal80938c12018-05-15 11:57:27 +02001464 tpm2 {
1465 compatible = "sandbox,tpm2";
Eddie James1a55a7a2023-10-24 10:43:51 -05001466 memory-region = <&event_log>;
Miquel Raynal80938c12018-05-15 11:57:27 +02001467 };
1468
Simon Glasseef107e2023-02-21 06:24:51 -07001469 tpm {
1470 compatible = "google,sandbox-tpm";
1471 };
1472
Simon Glass5b968632015-05-22 15:42:15 -06001473 uart0: serial {
1474 compatible = "sandbox,serial";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001475 bootph-all;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001476 pinctrl-names = "default";
1477 pinctrl-0 = <&pinmux_uart0_pins>;
Joe Hershberger4c197242015-03-22 17:09:15 -05001478 };
1479
Simon Glass31680482015-03-25 12:23:05 -06001480 usb_0: usb@0 {
1481 compatible = "sandbox,usb";
1482 status = "disabled";
1483 hub {
1484 compatible = "sandbox,usb-hub";
1485 #address-cells = <1>;
1486 #size-cells = <0>;
1487 flash-stick {
1488 reg = <0>;
1489 compatible = "sandbox,usb-flash";
1490 };
1491 };
1492 };
1493
1494 usb_1: usb@1 {
1495 compatible = "sandbox,usb";
Mark Kettenis67748ee2021-10-23 16:58:02 +02001496 iommus = <&iommu>;
Simon Glass31680482015-03-25 12:23:05 -06001497 hub {
1498 compatible = "usb-hub";
1499 usb,device-class = <9>;
Michael Walle7c961322020-06-02 01:47:07 +02001500 #address-cells = <1>;
1501 #size-cells = <0>;
Simon Glass31680482015-03-25 12:23:05 -06001502 hub-emul {
1503 compatible = "sandbox,usb-hub";
1504 #address-cells = <1>;
1505 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -07001506 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -06001507 reg = <0>;
1508 compatible = "sandbox,usb-flash";
1509 sandbox,filepath = "testflash.bin";
1510 };
1511
Simon Glass4700fe52015-11-08 23:48:01 -07001512 flash-stick@1 {
1513 reg = <1>;
1514 compatible = "sandbox,usb-flash";
1515 sandbox,filepath = "testflash1.bin";
1516 };
1517
1518 flash-stick@2 {
1519 reg = <2>;
1520 compatible = "sandbox,usb-flash";
1521 sandbox,filepath = "testflash2.bin";
1522 };
1523
Simon Glassc0ccc722015-11-08 23:48:08 -07001524 keyb@3 {
1525 reg = <3>;
1526 compatible = "sandbox,usb-keyb";
1527 };
1528
Simon Glass31680482015-03-25 12:23:05 -06001529 };
Michael Walle7c961322020-06-02 01:47:07 +02001530
1531 usbstor@1 {
1532 reg = <1>;
1533 };
1534 usbstor@3 {
1535 reg = <3>;
1536 };
Simon Glass31680482015-03-25 12:23:05 -06001537 };
1538 };
1539
1540 usb_2: usb@2 {
1541 compatible = "sandbox,usb";
1542 status = "disabled";
1543 };
1544
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001545 spmi: spmi@0 {
1546 compatible = "sandbox,spmi";
1547 #address-cells = <0x1>;
1548 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001549 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001550 pm8916@0 {
1551 compatible = "qcom,spmi-pmic";
1552 reg = <0x0 0x1>;
1553 #address-cells = <0x1>;
1554 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001555 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001556
1557 spmi_gpios: gpios@c000 {
1558 compatible = "qcom,pm8916-gpio";
1559 reg = <0xc000 0x400>;
Caleb Connolly1edc45f2024-01-08 15:30:51 +00001560 gpio-ranges = <&spmi_gpios 0 0 4>;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001561 gpio-controller;
1562 gpio-count = <4>;
1563 #gpio-cells = <2>;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001564 };
1565 };
1566 };
maxims@google.comdaea6d42017-04-17 12:00:21 -07001567
1568 wdt0: wdt@0 {
1569 compatible = "sandbox,wdt";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +02001570 hw_margin_ms = <200>;
maxims@google.comdaea6d42017-04-17 12:00:21 -07001571 };
Rob Clarka471b672018-01-10 11:33:30 +01001572
Mario Six95922152018-08-09 14:51:19 +02001573 axi: axi@0 {
1574 compatible = "sandbox,axi";
1575 #address-cells = <0x1>;
1576 #size-cells = <0x1>;
1577 store@0 {
1578 compatible = "sandbox,sandbox_store";
1579 reg = <0x0 0x400>;
1580 };
1581 };
1582
Rob Clarka471b672018-01-10 11:33:30 +01001583 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -07001584 #address-cells = <1>;
1585 #size-cells = <1>;
Simon Glassf3455962020-01-27 08:49:43 -07001586 setting = "sunrise ohoka";
1587 other-node = "/some-bus/c-test@5";
Simon Glasse09223c2020-01-27 08:49:46 -07001588 int-values = <0x1937 72993>;
Simon Glass3c601b12020-07-07 13:12:06 -06001589 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Algapally Santosh Sagardf178992023-09-21 16:50:43 +05301590 stdout-path = "serial0:115200n8";
Rob Clarka471b672018-01-10 11:33:30 +01001591 chosen-test {
1592 compatible = "denx,u-boot-fdt-test";
1593 reg = <9 1>;
1594 };
1595 };
Mario Six35616ef2018-03-12 14:53:33 +01001596
1597 translation-test@8000 {
1598 compatible = "simple-bus";
1599 reg = <0x8000 0x4000>;
1600
1601 #address-cells = <0x2>;
1602 #size-cells = <0x1>;
1603
1604 ranges = <0 0x0 0x8000 0x1000
1605 1 0x100 0x9000 0x1000
1606 2 0x200 0xA000 0x1000
1607 3 0x300 0xB000 0x1000
1608 >;
1609
Fabien Dessenne22236e02019-05-31 15:11:30 +02001610 dma-ranges = <0 0x000 0x10000000 0x1000
1611 1 0x100 0x20000000 0x1000
1612 >;
1613
Mario Six35616ef2018-03-12 14:53:33 +01001614 dev@0,0 {
1615 compatible = "denx,u-boot-fdt-dummy";
1616 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojasa3181152018-12-03 19:37:09 +01001617 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +01001618 };
1619
1620 dev@1,100 {
1621 compatible = "denx,u-boot-fdt-dummy";
1622 reg = <1 0x100 0x1000>;
1623
1624 };
1625
1626 dev@2,200 {
1627 compatible = "denx,u-boot-fdt-dummy";
1628 reg = <2 0x200 0x1000>;
1629 };
1630
1631
1632 noxlatebus@3,300 {
1633 compatible = "simple-bus";
1634 reg = <3 0x300 0x1000>;
1635
1636 #address-cells = <0x1>;
1637 #size-cells = <0x0>;
1638
1639 dev@42 {
1640 compatible = "denx,u-boot-fdt-dummy";
1641 reg = <0x42>;
1642 };
1643 };
1644 };
Mario Six02ad6fb2018-09-27 09:19:31 +02001645
Dzmitry Sankouski54f4c832023-01-22 18:21:23 +03001646 ofnode-foreach {
1647 compatible = "foreach";
1648
1649 first {
1650 prop1 = <1>;
1651 prop2 = <2>;
1652 };
1653
1654 second {
1655 prop1 = <1>;
1656 prop2 = <2>;
1657 };
1658 };
1659
Mario Six02ad6fb2018-09-27 09:19:31 +02001660 osd {
1661 compatible = "sandbox,sandbox_osd";
1662 };
Tom Rinib93eea72018-09-30 18:16:51 -04001663
Jens Wiklander86afaa62018-09-25 16:40:16 +02001664 sandbox_tee {
1665 compatible = "sandbox,tee";
1666 };
Bin Meng1bb290d2018-10-15 02:21:26 -07001667
1668 sandbox_virtio1 {
1669 compatible = "sandbox,virtio1";
Simon Glass8de5a542023-01-17 10:47:51 -07001670 virtio-type = <4>; /* rng */
Bin Meng1bb290d2018-10-15 02:21:26 -07001671 };
1672
1673 sandbox_virtio2 {
1674 compatible = "sandbox,virtio2";
1675 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001676
Simon Glass8de5a542023-01-17 10:47:51 -07001677 sandbox-virtio-blk {
1678 compatible = "sandbox,virtio1";
1679 virtio-type = <2>; /* block */
1680 };
1681
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001682 sandbox_scmi {
1683 compatible = "sandbox,scmi-devices";
AKASHI Takahiro535a7bd2023-10-16 14:39:45 +09001684 power-domains = <&pwrdom_scmi 2>;
Etienne Carrierebf1f1322022-02-21 09:22:41 +01001685 clocks = <&clk_scmi 2>, <&clk_scmi 0>;
Etienne Carriere09665cb2022-02-21 09:22:39 +01001686 resets = <&reset_scmi 3>;
1687 regul0-supply = <&regul0_scmi>;
1688 regul1-supply = <&regul1_scmi>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001689 };
1690
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001691 pinctrl {
1692 compatible = "sandbox,pinctrl";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001693
Sean Anderson3438e3b2020-09-14 11:01:57 -04001694 pinctrl-names = "default", "alternate";
1695 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1696 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001697
Sean Anderson3438e3b2020-09-14 11:01:57 -04001698 pinctrl_gpios: gpios {
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001699 gpio0 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001700 pins = "P5";
1701 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001702 bias-pull-up;
1703 input-disable;
1704 };
1705 gpio1 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001706 pins = "P6";
1707 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001708 output-high;
1709 drive-open-drain;
1710 };
1711 gpio2 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001712 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001713 bias-pull-down;
1714 input-enable;
1715 };
1716 gpio3 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001717 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001718 bias-disable;
1719 };
1720 };
Sean Anderson3438e3b2020-09-14 11:01:57 -04001721
1722 pinctrl_i2c: i2c {
1723 groups {
1724 groups = "I2C_UART";
1725 function = "I2C";
1726 };
1727
1728 pins {
1729 pins = "P0", "P1";
1730 drive-open-drain;
1731 };
1732 };
1733
1734 pinctrl_i2s: i2s {
1735 groups = "SPI_I2S";
1736 function = "I2S";
1737 };
1738
1739 pinctrl_spi: spi {
1740 groups = "SPI_I2S";
1741 function = "SPI";
1742
1743 cs {
1744 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1745 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1746 };
1747 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001748 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001749
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001750 pinctrl-single-no-width {
1751 compatible = "pinctrl-single";
1752 reg = <0x0000 0x238>;
1753 #pinctrl-cells = <1>;
1754 pinctrl-single,function-mask = <0x7f>;
1755 };
1756
1757 pinctrl-single-pins {
1758 compatible = "pinctrl-single";
1759 reg = <0x0000 0x238>;
1760 #pinctrl-cells = <1>;
1761 pinctrl-single,register-width = <32>;
1762 pinctrl-single,function-mask = <0x7f>;
1763
1764 pinmux_pwm_pins: pinmux_pwm_pins {
1765 pinctrl-single,pins = < 0x48 0x06 >;
1766 };
1767
1768 pinmux_spi0_pins: pinmux_spi0_pins {
1769 pinctrl-single,pins = <
1770 0x190 0x0c
1771 0x194 0x0c
1772 0x198 0x23
1773 0x19c 0x0c
1774 >;
1775 };
1776
1777 pinmux_uart0_pins: pinmux_uart0_pins {
1778 pinctrl-single,pins = <
1779 0x70 0x30
1780 0x74 0x00
1781 >;
1782 };
1783 };
1784
1785 pinctrl-single-bits {
1786 compatible = "pinctrl-single";
1787 reg = <0x0000 0x50>;
1788 #pinctrl-cells = <2>;
1789 pinctrl-single,bit-per-mux;
1790 pinctrl-single,register-width = <32>;
1791 pinctrl-single,function-mask = <0xf>;
1792
1793 pinmux_i2c0_pins: pinmux_i2c0_pins {
1794 pinctrl-single,bits = <
1795 0x10 0x00002200 0x0000ff00
1796 >;
1797 };
1798
1799 pinmux_lcd_pins: pinmux_lcd_pins {
1800 pinctrl-single,bits = <
1801 0x40 0x22222200 0xffffff00
1802 0x44 0x22222222 0xffffffff
1803 0x48 0x00000022 0x000000ff
1804 0x48 0x02000000 0x0f000000
1805 0x4c 0x02000022 0x0f0000ff
1806 >;
1807 };
1808 };
1809
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001810 hwspinlock@0 {
1811 compatible = "sandbox,hwspinlock";
1812 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +01001813
1814 dma: dma {
1815 compatible = "sandbox,dma";
1816 #dma-cells = <1>;
1817
1818 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1819 dma-names = "m2m", "tx0", "rx0";
1820 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001821
Alex Marginean0649be52019-07-12 10:13:53 +03001822 /*
1823 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1824 * end of the test. If parent mdio is removed first, clean-up of the
1825 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1826 * active at the end of the test. That it turn doesn't allow the mdio
1827 * class to be destroyed, triggering an error.
1828 */
1829 mdio-mux-test {
1830 compatible = "sandbox,mdio-mux";
1831 #address-cells = <1>;
1832 #size-cells = <0>;
1833 mdio-parent-bus = <&mdio>;
1834
1835 mdio-ch-test@0 {
1836 reg = <0>;
1837 };
1838 mdio-ch-test@1 {
1839 reg = <1>;
1840 };
1841 };
1842
1843 mdio: mdio-test {
Alex Marginean0daa53a2019-06-03 19:12:28 +03001844 compatible = "sandbox,mdio";
Marek Behúnf4f1ddc2022-04-07 00:32:57 +02001845 #address-cells = <1>;
1846 #size-cells = <0>;
1847
1848 ethphy1: ethernet-phy@1 {
1849 reg = <1>;
1850 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001851 };
Sean Andersonb7860542020-06-24 06:41:12 -04001852
1853 pm-bus-test {
1854 compatible = "simple-pm-bus";
1855 clocks = <&clk_sandbox 4>;
1856 power-domains = <&pwrdom 1>;
1857 };
Sean Anderson0c1f6bf2020-06-24 06:41:14 -04001858
1859 resetc2: syscon-reset {
1860 compatible = "syscon-reset";
1861 #reset-cells = <1>;
1862 regmap = <&syscon0>;
1863 offset = <1>;
1864 mask = <0x27FFFFFF>;
1865 assert-high = <0>;
1866 };
1867
1868 syscon-reset-test {
1869 compatible = "sandbox,misc_sandbox";
1870 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1871 reset-names = "valid", "no_mask", "out_of_range";
1872 };
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301873
Simon Glass458b66a2020-11-05 06:32:05 -07001874 sysinfo {
1875 compatible = "sandbox,sysinfo-sandbox";
1876 };
1877
Sean Anderson1c830672021-04-20 10:50:58 -04001878 sysinfo-gpio {
1879 compatible = "gpio-sysinfo";
1880 gpios = <&gpio_a 15>, <&gpio_a 16>, <&gpio_a 17>;
1881 revisions = <19>, <5>;
1882 names = "rev_a", "foo";
1883 };
1884
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301885 some_regmapped-bus {
1886 #address-cells = <0x1>;
1887 #size-cells = <0x1>;
1888
1889 ranges = <0x0 0x0 0x10>;
1890 compatible = "simple-bus";
1891
1892 regmap-test_0 {
1893 reg = <0 0x10>;
1894 compatible = "sandbox,regmap_test";
1895 };
1896 };
Robert Marko9cf87122022-09-06 13:30:35 +02001897
1898 thermal {
1899 compatible = "sandbox,thermal";
1900 };
Sughosh Ganu77079e72022-10-21 18:16:05 +05301901
1902 fwu-mdata {
1903 compatible = "u-boot,fwu-mdata-gpt";
1904 fwu-mdata-store = <&mmc0>;
1905 };
Abdellatif El Khlifi6b005872023-04-17 10:11:55 +01001906
1907 nvmxip-qspi1@08000000 {
1908 compatible = "nvmxip,qspi";
1909 reg = <0x08000000 0x00200000>;
1910 lba_shift = <9>;
1911 lba = <4096>;
1912 };
1913
1914 nvmxip-qspi2@08200000 {
1915 compatible = "nvmxip,qspi";
1916 reg = <0x08200000 0x00100000>;
1917 lba_shift = <9>;
1918 lba = <2048>;
1919 };
Svyatoslav Ryhel669f5c82023-04-25 10:57:21 +03001920
1921 extcon {
1922 compatible = "sandbox,extcon";
1923 };
Abdellatif El Khlifi4970d5b2023-08-04 14:33:41 +01001924
1925 arm-ffa-emul {
1926 compatible = "sandbox,arm-ffa-emul";
1927
1928 sandbox-arm-ffa {
1929 compatible = "sandbox,arm-ffa";
1930 };
1931 };
Sean Anderson326422b2023-11-04 16:37:52 -04001932
1933 nand-controller {
1934 #address-cells = <1>;
1935 #size-cells = <0>;
1936 compatible = "sandbox,nand";
1937
1938 nand@0 {
1939 reg = <0>;
1940 nand-ecc-mode = "soft";
1941 sandbox,id = [00 e3];
1942 sandbox,erasesize = <(8 * 1024)>;
1943 sandbox,oobsize = <16>;
1944 sandbox,pagesize = <512>;
1945 sandbox,pages = <0x2000>;
1946 sandbox,err-count = <1>;
1947 sandbox,err-step-size = <512>;
1948 };
1949
1950 /* MT29F64G08AKABA */
1951 nand@1 {
1952 reg = <1>;
1953 nand-ecc-mode = "soft_bch";
1954 sandbox,id = [2C 48 00 26 89 00 00 00];
1955 sandbox,onfi = [
1956 4f 4e 46 49 0e 00 5a 00
1957 ff 01 00 00 00 00 03 00
1958 00 00 00 00 00 00 00 00
1959 00 00 00 00 00 00 00 00
1960 4d 49 43 52 4f 4e 20 20
1961 20 20 20 20 4d 54 32 39
1962 46 36 34 47 30 38 41 4b
1963 41 42 41 43 35 20 20 20
1964 2c 00 00 00 00 00 00 00
1965 00 00 00 00 00 00 00 00
1966 00 10 00 00 e0 00 00 02
1967 00 00 1c 00 80 00 00 00
1968 00 10 00 00 02 23 01 50
1969 00 01 05 01 00 00 04 00
1970 04 01 1e 00 00 00 00 00
1971 00 00 00 00 00 00 00 00
1972 0e 1f 00 1f 00 f4 01 ac
1973 0d 19 00 c8 00 00 00 00
1974 00 00 00 00 00 00 0a 07
1975 19 00 00 00 00 00 00 00
1976 00 00 00 00 01 00 01 00
1977 00 00 04 10 01 81 04 02
1978 02 01 1e 90 00 00 00 00
1979 00 00 00 00 00 00 00 00
1980 00 00 00 00 00 00 00 00
1981 00 00 00 00 00 00 00 00
1982 00 00 00 00 00 00 00 00
1983 00 00 00 00 00 00 00 00
1984 00 00 00 00 00 00 00 00
1985 00 00 00 00 00 00 00 00
1986 00 00 00 00 00 00 00 00
1987 00 00 00 00 00 03 20 7d
1988 ];
1989 sandbox,erasesize = <(512 * 1024)>;
1990 sandbox,oobsize = <224>;
1991 sandbox,pagesize = <4096>;
1992 sandbox,pages = <0x200000>;
1993 sandbox,err-count = <3>;
1994 sandbox,err-step-size = <512>;
1995 };
1996 };
Simon Glassb2c1cac2014-02-26 15:59:21 -07001997};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +02001998
1999#include "sandbox_pmic.dtsi"
Heinrich Schuchardte24fdef2021-02-18 13:01:35 +01002000#include "cros-ec-keyboard.dtsi"
Simon Glass5e135d32022-10-20 18:23:15 -06002001
2002#ifdef CONFIG_SANDBOX_VPL
2003#include "sandbox_vpl.dtsi"
2004#endif
Simon Glass61300722023-06-01 10:23:01 -06002005
Sughosh Ganu05137922024-03-27 16:19:00 +05302006#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)
2007#include "sandbox_capsule.dtsi"
2008#endif
2009
Simon Glass61300722023-06-01 10:23:01 -06002010#include "cedit.dtsi"