Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1 | /* |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 2 | * Copyright 2008-2014 Freescale Semiconductor, Inc. |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 3 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 4 | * SPDX-License-Identifier: GPL-2.0+ |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | /* |
| 8 | * Generic driver for Freescale DDR/DDR2/DDR3 memory controller. |
| 9 | * Based on code from spd_sdram.c |
| 10 | * Author: James Yang [at freescale.com] |
| 11 | */ |
| 12 | |
| 13 | #include <common.h> |
York Sun | f062659 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 14 | #include <fsl_ddr_sdram.h> |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 15 | |
York Sun | f062659 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 16 | #include <fsl_ddr.h> |
York Sun | a21803d | 2013-11-18 10:29:32 -0800 | [diff] [blame] | 17 | #include <fsl_immap.h> |
York Sun | f062659 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 18 | #include <asm/io.h> |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 19 | |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 20 | /* |
| 21 | * Determine Rtt value. |
| 22 | * |
| 23 | * This should likely be either board or controller specific. |
| 24 | * |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 25 | * Rtt(nominal) - DDR2: |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 26 | * 0 = Rtt disabled |
| 27 | * 1 = 75 ohm |
| 28 | * 2 = 150 ohm |
| 29 | * 3 = 50 ohm |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 30 | * Rtt(nominal) - DDR3: |
| 31 | * 0 = Rtt disabled |
| 32 | * 1 = 60 ohm |
| 33 | * 2 = 120 ohm |
| 34 | * 3 = 40 ohm |
| 35 | * 4 = 20 ohm |
| 36 | * 5 = 30 ohm |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 37 | * |
| 38 | * FIXME: Apparently 8641 needs a value of 2 |
| 39 | * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572 |
| 40 | * |
| 41 | * FIXME: There was some effort down this line earlier: |
| 42 | * |
| 43 | * unsigned int i; |
| 44 | * for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) { |
| 45 | * if (popts->dimmslot[i].num_valid_cs |
| 46 | * && (popts->cs_local_opts[2*i].odt_rd_cfg |
| 47 | * || popts->cs_local_opts[2*i].odt_wr_cfg)) { |
| 48 | * rtt = 2; |
| 49 | * break; |
| 50 | * } |
| 51 | * } |
| 52 | */ |
| 53 | static inline int fsl_ddr_get_rtt(void) |
| 54 | { |
| 55 | int rtt; |
| 56 | |
York Sun | f062659 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 57 | #if defined(CONFIG_SYS_FSL_DDR1) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 58 | rtt = 0; |
York Sun | f062659 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 59 | #elif defined(CONFIG_SYS_FSL_DDR2) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 60 | rtt = 3; |
| 61 | #else |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 62 | rtt = 0; |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 63 | #endif |
| 64 | |
| 65 | return rtt; |
| 66 | } |
| 67 | |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 68 | #ifdef CONFIG_SYS_FSL_DDR4 |
| 69 | /* |
| 70 | * compute CAS write latency according to DDR4 spec |
| 71 | * CWL = 9 for <= 1600MT/s |
| 72 | * 10 for <= 1866MT/s |
| 73 | * 11 for <= 2133MT/s |
| 74 | * 12 for <= 2400MT/s |
| 75 | * 14 for <= 2667MT/s |
| 76 | * 16 for <= 2933MT/s |
| 77 | * 18 for higher |
| 78 | */ |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 79 | static inline unsigned int compute_cas_write_latency( |
| 80 | const unsigned int ctrl_num) |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 81 | { |
| 82 | unsigned int cwl; |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 83 | const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 84 | if (mclk_ps >= 1250) |
| 85 | cwl = 9; |
| 86 | else if (mclk_ps >= 1070) |
| 87 | cwl = 10; |
| 88 | else if (mclk_ps >= 935) |
| 89 | cwl = 11; |
| 90 | else if (mclk_ps >= 833) |
| 91 | cwl = 12; |
| 92 | else if (mclk_ps >= 750) |
| 93 | cwl = 14; |
| 94 | else if (mclk_ps >= 681) |
| 95 | cwl = 16; |
| 96 | else |
| 97 | cwl = 18; |
| 98 | |
| 99 | return cwl; |
| 100 | } |
| 101 | #else |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 102 | /* |
| 103 | * compute the CAS write latency according to DDR3 spec |
| 104 | * CWL = 5 if tCK >= 2.5ns |
| 105 | * 6 if 2.5ns > tCK >= 1.875ns |
| 106 | * 7 if 1.875ns > tCK >= 1.5ns |
| 107 | * 8 if 1.5ns > tCK >= 1.25ns |
York Sun | 7a16d64 | 2011-08-24 09:40:25 -0700 | [diff] [blame] | 108 | * 9 if 1.25ns > tCK >= 1.07ns |
| 109 | * 10 if 1.07ns > tCK >= 0.935ns |
| 110 | * 11 if 0.935ns > tCK >= 0.833ns |
| 111 | * 12 if 0.833ns > tCK >= 0.75ns |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 112 | */ |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 113 | static inline unsigned int compute_cas_write_latency( |
| 114 | const unsigned int ctrl_num) |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 115 | { |
| 116 | unsigned int cwl; |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 117 | const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 118 | |
| 119 | if (mclk_ps >= 2500) |
| 120 | cwl = 5; |
| 121 | else if (mclk_ps >= 1875) |
| 122 | cwl = 6; |
| 123 | else if (mclk_ps >= 1500) |
| 124 | cwl = 7; |
| 125 | else if (mclk_ps >= 1250) |
| 126 | cwl = 8; |
York Sun | 7a16d64 | 2011-08-24 09:40:25 -0700 | [diff] [blame] | 127 | else if (mclk_ps >= 1070) |
| 128 | cwl = 9; |
| 129 | else if (mclk_ps >= 935) |
| 130 | cwl = 10; |
| 131 | else if (mclk_ps >= 833) |
| 132 | cwl = 11; |
| 133 | else if (mclk_ps >= 750) |
| 134 | cwl = 12; |
| 135 | else { |
| 136 | cwl = 12; |
| 137 | printf("Warning: CWL is out of range\n"); |
| 138 | } |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 139 | return cwl; |
| 140 | } |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 141 | #endif |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 142 | |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 143 | /* Chip Select Configuration (CSn_CONFIG) */ |
york | f4f93c6 | 2010-07-02 22:25:53 +0000 | [diff] [blame] | 144 | static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr, |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 145 | const memctl_options_t *popts, |
| 146 | const dimm_params_t *dimm_params) |
| 147 | { |
| 148 | unsigned int cs_n_en = 0; /* Chip Select enable */ |
| 149 | unsigned int intlv_en = 0; /* Memory controller interleave enable */ |
| 150 | unsigned int intlv_ctl = 0; /* Interleaving control */ |
| 151 | unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */ |
| 152 | unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */ |
| 153 | unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */ |
| 154 | unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */ |
| 155 | unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */ |
| 156 | unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */ |
york | f4f93c6 | 2010-07-02 22:25:53 +0000 | [diff] [blame] | 157 | int go_config = 0; |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 158 | #ifdef CONFIG_SYS_FSL_DDR4 |
| 159 | unsigned int bg_bits_cs_n = 0; /* Num of bank group bits */ |
| 160 | #else |
| 161 | unsigned int n_banks_per_sdram_device; |
| 162 | #endif |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 163 | |
| 164 | /* Compute CS_CONFIG only for existing ranks of each DIMM. */ |
york | f4f93c6 | 2010-07-02 22:25:53 +0000 | [diff] [blame] | 165 | switch (i) { |
| 166 | case 0: |
| 167 | if (dimm_params[dimm_number].n_ranks > 0) { |
| 168 | go_config = 1; |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 169 | /* These fields only available in CS0_CONFIG */ |
York Sun | e8dc17b | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 170 | if (!popts->memctl_interleaving) |
| 171 | break; |
| 172 | switch (popts->memctl_interleaving_mode) { |
York Sun | c459ae6 | 2014-02-10 13:59:44 -0800 | [diff] [blame] | 173 | case FSL_DDR_256B_INTERLEAVING: |
York Sun | e8dc17b | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 174 | case FSL_DDR_CACHE_LINE_INTERLEAVING: |
| 175 | case FSL_DDR_PAGE_INTERLEAVING: |
| 176 | case FSL_DDR_BANK_INTERLEAVING: |
| 177 | case FSL_DDR_SUPERBANK_INTERLEAVING: |
| 178 | intlv_en = popts->memctl_interleaving; |
| 179 | intlv_ctl = popts->memctl_interleaving_mode; |
| 180 | break; |
| 181 | default: |
| 182 | break; |
| 183 | } |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 184 | } |
york | f4f93c6 | 2010-07-02 22:25:53 +0000 | [diff] [blame] | 185 | break; |
| 186 | case 1: |
| 187 | if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \ |
| 188 | (dimm_number == 1 && dimm_params[1].n_ranks > 0)) |
| 189 | go_config = 1; |
| 190 | break; |
| 191 | case 2: |
| 192 | if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \ |
York Sun | 15f874a | 2011-08-26 11:32:40 -0700 | [diff] [blame] | 193 | (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0)) |
york | f4f93c6 | 2010-07-02 22:25:53 +0000 | [diff] [blame] | 194 | go_config = 1; |
| 195 | break; |
| 196 | case 3: |
| 197 | if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \ |
| 198 | (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \ |
| 199 | (dimm_number == 3 && dimm_params[3].n_ranks > 0)) |
| 200 | go_config = 1; |
| 201 | break; |
| 202 | default: |
| 203 | break; |
| 204 | } |
| 205 | if (go_config) { |
york | f4f93c6 | 2010-07-02 22:25:53 +0000 | [diff] [blame] | 206 | cs_n_en = 1; |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 207 | ap_n_en = popts->cs_local_opts[i].auto_precharge; |
| 208 | odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg; |
| 209 | odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg; |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 210 | #ifdef CONFIG_SYS_FSL_DDR4 |
| 211 | ba_bits_cs_n = dimm_params[dimm_number].bank_addr_bits; |
| 212 | bg_bits_cs_n = dimm_params[dimm_number].bank_group_bits; |
| 213 | #else |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 214 | n_banks_per_sdram_device |
york | f4f93c6 | 2010-07-02 22:25:53 +0000 | [diff] [blame] | 215 | = dimm_params[dimm_number].n_banks_per_sdram_device; |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 216 | ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2; |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 217 | #endif |
york | f4f93c6 | 2010-07-02 22:25:53 +0000 | [diff] [blame] | 218 | row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12; |
| 219 | col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8; |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 220 | } |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 221 | ddr->cs[i].config = (0 |
| 222 | | ((cs_n_en & 0x1) << 31) |
| 223 | | ((intlv_en & 0x3) << 29) |
Haiying Wang | 272b596 | 2008-10-03 12:36:39 -0400 | [diff] [blame] | 224 | | ((intlv_ctl & 0xf) << 24) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 225 | | ((ap_n_en & 0x1) << 23) |
| 226 | |
| 227 | /* XXX: some implementation only have 1 bit starting at left */ |
| 228 | | ((odt_rd_cfg & 0x7) << 20) |
| 229 | |
| 230 | /* XXX: Some implementation only have 1 bit starting at left */ |
| 231 | | ((odt_wr_cfg & 0x7) << 16) |
| 232 | |
| 233 | | ((ba_bits_cs_n & 0x3) << 14) |
| 234 | | ((row_bits_cs_n & 0x7) << 8) |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 235 | #ifdef CONFIG_SYS_FSL_DDR4 |
| 236 | | ((bg_bits_cs_n & 0x3) << 4) |
| 237 | #endif |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 238 | | ((col_bits_cs_n & 0x7) << 0) |
| 239 | ); |
Haiying Wang | d90e040 | 2008-10-03 12:37:26 -0400 | [diff] [blame] | 240 | debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config); |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 241 | } |
| 242 | |
| 243 | /* Chip Select Configuration 2 (CSn_CONFIG_2) */ |
| 244 | /* FIXME: 8572 */ |
| 245 | static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr) |
| 246 | { |
| 247 | unsigned int pasr_cfg = 0; /* Partial array self refresh config */ |
| 248 | |
| 249 | ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24); |
Haiying Wang | d90e040 | 2008-10-03 12:37:26 -0400 | [diff] [blame] | 250 | debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2); |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 251 | } |
| 252 | |
| 253 | /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */ |
| 254 | |
York Sun | f062659 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 255 | #if !defined(CONFIG_SYS_FSL_DDR1) |
York Sun | fbce88c | 2014-11-07 12:14:36 -0800 | [diff] [blame] | 256 | /* |
| 257 | * Check DIMM configuration, return 2 if quad-rank or two dual-rank |
| 258 | * Return 1 if other two slots configuration. Return 0 if single slot. |
| 259 | */ |
York Sun | 98df4d1 | 2012-10-08 07:44:23 +0000 | [diff] [blame] | 260 | static inline int avoid_odt_overlap(const dimm_params_t *dimm_params) |
| 261 | { |
| 262 | #if CONFIG_DIMM_SLOTS_PER_CTLR == 1 |
| 263 | if (dimm_params[0].n_ranks == 4) |
York Sun | fbce88c | 2014-11-07 12:14:36 -0800 | [diff] [blame] | 264 | return 2; |
York Sun | 98df4d1 | 2012-10-08 07:44:23 +0000 | [diff] [blame] | 265 | #endif |
| 266 | |
| 267 | #if CONFIG_DIMM_SLOTS_PER_CTLR == 2 |
| 268 | if ((dimm_params[0].n_ranks == 2) && |
| 269 | (dimm_params[1].n_ranks == 2)) |
York Sun | fbce88c | 2014-11-07 12:14:36 -0800 | [diff] [blame] | 270 | return 2; |
York Sun | 98df4d1 | 2012-10-08 07:44:23 +0000 | [diff] [blame] | 271 | |
| 272 | #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE |
| 273 | if (dimm_params[0].n_ranks == 4) |
York Sun | fbce88c | 2014-11-07 12:14:36 -0800 | [diff] [blame] | 274 | return 2; |
York Sun | 98df4d1 | 2012-10-08 07:44:23 +0000 | [diff] [blame] | 275 | #endif |
York Sun | fbce88c | 2014-11-07 12:14:36 -0800 | [diff] [blame] | 276 | |
| 277 | if ((dimm_params[0].n_ranks != 0) && |
| 278 | (dimm_params[2].n_ranks != 0)) |
| 279 | return 1; |
York Sun | 98df4d1 | 2012-10-08 07:44:23 +0000 | [diff] [blame] | 280 | #endif |
| 281 | return 0; |
| 282 | } |
| 283 | |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 284 | /* |
| 285 | * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0) |
| 286 | * |
| 287 | * Avoid writing for DDR I. The new PQ38 DDR controller |
| 288 | * dreams up non-zero default values to be backwards compatible. |
| 289 | */ |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 290 | static void set_timing_cfg_0(const unsigned int ctrl_num, |
| 291 | fsl_ddr_cfg_regs_t *ddr, |
York Sun | 98df4d1 | 2012-10-08 07:44:23 +0000 | [diff] [blame] | 292 | const memctl_options_t *popts, |
| 293 | const dimm_params_t *dimm_params) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 294 | { |
| 295 | unsigned char trwt_mclk = 0; /* Read-to-write turnaround */ |
| 296 | unsigned char twrt_mclk = 0; /* Write-to-read turnaround */ |
| 297 | /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */ |
| 298 | unsigned char trrt_mclk = 0; /* Read-to-read turnaround */ |
| 299 | unsigned char twwt_mclk = 0; /* Write-to-write turnaround */ |
| 300 | |
| 301 | /* Active powerdown exit timing (tXARD and tXARDS). */ |
| 302 | unsigned char act_pd_exit_mclk; |
| 303 | /* Precharge powerdown exit timing (tXP). */ |
| 304 | unsigned char pre_pd_exit_mclk; |
york | 1714e49 | 2010-07-02 22:25:56 +0000 | [diff] [blame] | 305 | /* ODT powerdown exit timing (tAXPD). */ |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 306 | unsigned char taxpd_mclk = 0; |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 307 | /* Mode register set cycle time (tMRD). */ |
| 308 | unsigned char tmrd_mclk; |
York Sun | c1bf24f | 2014-08-21 16:13:22 -0700 | [diff] [blame] | 309 | #if defined(CONFIG_SYS_FSL_DDR4) || defined(CONFIG_SYS_FSL_DDR3) |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 310 | const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); |
York Sun | c1bf24f | 2014-08-21 16:13:22 -0700 | [diff] [blame] | 311 | #endif |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 312 | |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 313 | #ifdef CONFIG_SYS_FSL_DDR4 |
| 314 | /* tXP=max(4nCK, 6ns) */ |
Masahiro Yamada | db20464 | 2014-11-07 03:03:31 +0900 | [diff] [blame] | 315 | int txp = max((int)mclk_ps * 4, 6000); /* unit=ps */ |
York Sun | 55eb5fa | 2015-03-19 09:30:26 -0700 | [diff] [blame] | 316 | unsigned int data_rate = get_ddr_freq(ctrl_num); |
| 317 | |
| 318 | /* for faster clock, need more time for data setup */ |
| 319 | trwt_mclk = (data_rate/1000000 > 1900) ? 3 : 2; |
York Sun | 77594b3 | 2015-11-04 10:03:21 -0800 | [diff] [blame] | 320 | |
| 321 | /* |
| 322 | * for single quad-rank DIMM and two-slot DIMMs |
| 323 | * to avoid ODT overlap |
| 324 | */ |
| 325 | switch (avoid_odt_overlap(dimm_params)) { |
| 326 | case 2: |
| 327 | twrt_mclk = 2; |
| 328 | twwt_mclk = 2; |
| 329 | trrt_mclk = 2; |
| 330 | break; |
| 331 | default: |
| 332 | twrt_mclk = 1; |
| 333 | twwt_mclk = 1; |
| 334 | trrt_mclk = 0; |
| 335 | break; |
| 336 | } |
| 337 | |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 338 | act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp); |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 339 | pre_pd_exit_mclk = act_pd_exit_mclk; |
| 340 | /* |
| 341 | * MRS_CYC = max(tMRD, tMOD) |
| 342 | * tMRD = 8nCK, tMOD = max(24nCK, 15ns) |
| 343 | */ |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 344 | tmrd_mclk = max(24U, picos_to_mclk(ctrl_num, 15000)); |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 345 | #elif defined(CONFIG_SYS_FSL_DDR3) |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 346 | unsigned int data_rate = get_ddr_freq(ctrl_num); |
York Sun | c1bf24f | 2014-08-21 16:13:22 -0700 | [diff] [blame] | 347 | int txp; |
York Sun | 1b07ef1 | 2014-12-02 11:18:09 -0800 | [diff] [blame] | 348 | unsigned int ip_rev; |
York Sun | fbce88c | 2014-11-07 12:14:36 -0800 | [diff] [blame] | 349 | int odt_overlap; |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 350 | /* |
| 351 | * (tXARD and tXARDS). Empirical? |
| 352 | * The DDR3 spec has not tXARD, |
| 353 | * we use the tXP instead of it. |
York Sun | c1bf24f | 2014-08-21 16:13:22 -0700 | [diff] [blame] | 354 | * tXP=max(3nCK, 7.5ns) for DDR3-800, 1066 |
| 355 | * max(3nCK, 6ns) for DDR3-1333, 1600, 1866, 2133 |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 356 | * spec has not the tAXPD, we use |
york | 1714e49 | 2010-07-02 22:25:56 +0000 | [diff] [blame] | 357 | * tAXPD=1, need design to confirm. |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 358 | */ |
Masahiro Yamada | db20464 | 2014-11-07 03:03:31 +0900 | [diff] [blame] | 359 | txp = max((int)mclk_ps * 3, (mclk_ps > 1540 ? 7500 : 6000)); |
York Sun | c1bf24f | 2014-08-21 16:13:22 -0700 | [diff] [blame] | 360 | |
York Sun | 55eb5fa | 2015-03-19 09:30:26 -0700 | [diff] [blame] | 361 | ip_rev = fsl_ddr_get_version(ctrl_num); |
York Sun | 1b07ef1 | 2014-12-02 11:18:09 -0800 | [diff] [blame] | 362 | if (ip_rev >= 0x40700) { |
| 363 | /* |
| 364 | * MRS_CYC = max(tMRD, tMOD) |
| 365 | * tMRD = 4nCK (8nCK for RDIMM) |
| 366 | * tMOD = max(12nCK, 15ns) |
| 367 | */ |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 368 | tmrd_mclk = max((unsigned int)12, |
| 369 | picos_to_mclk(ctrl_num, 15000)); |
York Sun | 1b07ef1 | 2014-12-02 11:18:09 -0800 | [diff] [blame] | 370 | } else { |
| 371 | /* |
| 372 | * MRS_CYC = tMRD |
| 373 | * tMRD = 4nCK (8nCK for RDIMM) |
| 374 | */ |
| 375 | if (popts->registered_dimm_en) |
| 376 | tmrd_mclk = 8; |
| 377 | else |
| 378 | tmrd_mclk = 4; |
| 379 | } |
| 380 | |
Dave Liu | 8107926 | 2009-12-08 11:56:48 +0800 | [diff] [blame] | 381 | /* set the turnaround time */ |
York Sun | 98df4d1 | 2012-10-08 07:44:23 +0000 | [diff] [blame] | 382 | |
| 383 | /* |
York Sun | fbce88c | 2014-11-07 12:14:36 -0800 | [diff] [blame] | 384 | * for single quad-rank DIMM and two-slot DIMMs |
York Sun | 98df4d1 | 2012-10-08 07:44:23 +0000 | [diff] [blame] | 385 | * to avoid ODT overlap |
| 386 | */ |
York Sun | fbce88c | 2014-11-07 12:14:36 -0800 | [diff] [blame] | 387 | odt_overlap = avoid_odt_overlap(dimm_params); |
| 388 | switch (odt_overlap) { |
| 389 | case 2: |
York Sun | 98df4d1 | 2012-10-08 07:44:23 +0000 | [diff] [blame] | 390 | twwt_mclk = 2; |
| 391 | trrt_mclk = 1; |
York Sun | fbce88c | 2014-11-07 12:14:36 -0800 | [diff] [blame] | 392 | break; |
| 393 | case 1: |
| 394 | twwt_mclk = 1; |
| 395 | trrt_mclk = 0; |
| 396 | break; |
| 397 | default: |
| 398 | break; |
York Sun | 98df4d1 | 2012-10-08 07:44:23 +0000 | [diff] [blame] | 399 | } |
York Sun | fbce88c | 2014-11-07 12:14:36 -0800 | [diff] [blame] | 400 | |
York Sun | 98df4d1 | 2012-10-08 07:44:23 +0000 | [diff] [blame] | 401 | /* for faster clock, need more time for data setup */ |
| 402 | trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1; |
| 403 | |
York Sun | 27f83be | 2011-02-10 10:13:10 -0800 | [diff] [blame] | 404 | if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving)) |
| 405 | twrt_mclk = 1; |
York Sun | ba0c2eb | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 406 | |
| 407 | if (popts->dynamic_power == 0) { /* powerdown is not used */ |
| 408 | act_pd_exit_mclk = 1; |
| 409 | pre_pd_exit_mclk = 1; |
| 410 | taxpd_mclk = 1; |
| 411 | } else { |
| 412 | /* act_pd_exit_mclk = tXARD, see above */ |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 413 | act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp); |
York Sun | ba0c2eb | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 414 | /* Mode register MR0[A12] is '1' - fast exit */ |
| 415 | pre_pd_exit_mclk = act_pd_exit_mclk; |
| 416 | taxpd_mclk = 1; |
| 417 | } |
York Sun | f062659 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 418 | #else /* CONFIG_SYS_FSL_DDR2 */ |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 419 | /* |
| 420 | * (tXARD and tXARDS). Empirical? |
| 421 | * tXARD = 2 for DDR2 |
| 422 | * tXP=2 |
| 423 | * tAXPD=8 |
| 424 | */ |
| 425 | act_pd_exit_mclk = 2; |
| 426 | pre_pd_exit_mclk = 2; |
| 427 | taxpd_mclk = 8; |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 428 | tmrd_mclk = 2; |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 429 | #endif |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 430 | |
York Sun | f8691fc | 2011-05-27 13:44:28 +0800 | [diff] [blame] | 431 | if (popts->trwt_override) |
| 432 | trwt_mclk = popts->trwt; |
| 433 | |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 434 | ddr->timing_cfg_0 = (0 |
| 435 | | ((trwt_mclk & 0x3) << 30) /* RWT */ |
| 436 | | ((twrt_mclk & 0x3) << 28) /* WRT */ |
| 437 | | ((trrt_mclk & 0x3) << 26) /* RRT */ |
| 438 | | ((twwt_mclk & 0x3) << 24) /* WWT */ |
York Sun | 63c91cd | 2013-06-03 12:39:06 -0700 | [diff] [blame] | 439 | | ((act_pd_exit_mclk & 0xf) << 20) /* ACT_PD_EXIT */ |
Dave Liu | 4758d53 | 2008-11-21 16:31:29 +0800 | [diff] [blame] | 440 | | ((pre_pd_exit_mclk & 0xF) << 16) /* PRE_PD_EXIT */ |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 441 | | ((taxpd_mclk & 0xf) << 8) /* ODT_PD_EXIT */ |
York Sun | 63c91cd | 2013-06-03 12:39:06 -0700 | [diff] [blame] | 442 | | ((tmrd_mclk & 0x1f) << 0) /* MRS_CYC */ |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 443 | ); |
| 444 | debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0); |
| 445 | } |
York Sun | fbce88c | 2014-11-07 12:14:36 -0800 | [diff] [blame] | 446 | #endif /* !defined(CONFIG_SYS_FSL_DDR1) */ |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 447 | |
| 448 | /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */ |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 449 | static void set_timing_cfg_3(const unsigned int ctrl_num, |
| 450 | fsl_ddr_cfg_regs_t *ddr, |
| 451 | const memctl_options_t *popts, |
| 452 | const common_timing_params_t *common_dimm, |
| 453 | unsigned int cas_latency, |
| 454 | unsigned int additive_latency) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 455 | { |
York Sun | cd077cf | 2012-08-17 08:22:40 +0000 | [diff] [blame] | 456 | /* Extended precharge to activate interval (tRP) */ |
| 457 | unsigned int ext_pretoact = 0; |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 458 | /* Extended Activate to precharge interval (tRAS) */ |
| 459 | unsigned int ext_acttopre = 0; |
York Sun | cd077cf | 2012-08-17 08:22:40 +0000 | [diff] [blame] | 460 | /* Extended activate to read/write interval (tRCD) */ |
| 461 | unsigned int ext_acttorw = 0; |
| 462 | /* Extended refresh recovery time (tRFC) */ |
| 463 | unsigned int ext_refrec; |
| 464 | /* Extended MCAS latency from READ cmd */ |
| 465 | unsigned int ext_caslat = 0; |
York Sun | 63c91cd | 2013-06-03 12:39:06 -0700 | [diff] [blame] | 466 | /* Extended additive latency */ |
| 467 | unsigned int ext_add_lat = 0; |
York Sun | cd077cf | 2012-08-17 08:22:40 +0000 | [diff] [blame] | 468 | /* Extended last data to precharge interval (tWR) */ |
| 469 | unsigned int ext_wrrec = 0; |
| 470 | /* Control Adjust */ |
| 471 | unsigned int cntl_adj = 0; |
Dave Liu | 5c1bb51 | 2008-11-21 16:31:22 +0800 | [diff] [blame] | 472 | |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 473 | ext_pretoact = picos_to_mclk(ctrl_num, common_dimm->trp_ps) >> 4; |
| 474 | ext_acttopre = picos_to_mclk(ctrl_num, common_dimm->tras_ps) >> 4; |
| 475 | ext_acttorw = picos_to_mclk(ctrl_num, common_dimm->trcd_ps) >> 4; |
York Sun | cd077cf | 2012-08-17 08:22:40 +0000 | [diff] [blame] | 476 | ext_caslat = (2 * cas_latency - 1) >> 4; |
York Sun | 63c91cd | 2013-06-03 12:39:06 -0700 | [diff] [blame] | 477 | ext_add_lat = additive_latency >> 4; |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 478 | #ifdef CONFIG_SYS_FSL_DDR4 |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 479 | ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8) >> 4; |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 480 | #else |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 481 | ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8) >> 4; |
York Sun | cd077cf | 2012-08-17 08:22:40 +0000 | [diff] [blame] | 482 | /* ext_wrrec only deals with 16 clock and above, or 14 with OTF */ |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 483 | #endif |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 484 | ext_wrrec = (picos_to_mclk(ctrl_num, common_dimm->twr_ps) + |
Priyanka Jain | 4a71741 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 485 | (popts->otf_burst_chop_en ? 2 : 0)) >> 4; |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 486 | |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 487 | ddr->timing_cfg_3 = (0 |
York Sun | cd077cf | 2012-08-17 08:22:40 +0000 | [diff] [blame] | 488 | | ((ext_pretoact & 0x1) << 28) |
James Yang | 26681f5 | 2013-07-22 09:35:26 -0700 | [diff] [blame] | 489 | | ((ext_acttopre & 0x3) << 24) |
York Sun | cd077cf | 2012-08-17 08:22:40 +0000 | [diff] [blame] | 490 | | ((ext_acttorw & 0x1) << 22) |
| 491 | | ((ext_refrec & 0x1F) << 16) |
| 492 | | ((ext_caslat & 0x3) << 12) |
York Sun | 63c91cd | 2013-06-03 12:39:06 -0700 | [diff] [blame] | 493 | | ((ext_add_lat & 0x1) << 10) |
York Sun | cd077cf | 2012-08-17 08:22:40 +0000 | [diff] [blame] | 494 | | ((ext_wrrec & 0x1) << 8) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 495 | | ((cntl_adj & 0x7) << 0) |
| 496 | ); |
Haiying Wang | d90e040 | 2008-10-03 12:37:26 -0400 | [diff] [blame] | 497 | debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3); |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 498 | } |
| 499 | |
| 500 | /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */ |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 501 | static void set_timing_cfg_1(const unsigned int ctrl_num, |
| 502 | fsl_ddr_cfg_regs_t *ddr, |
| 503 | const memctl_options_t *popts, |
| 504 | const common_timing_params_t *common_dimm, |
| 505 | unsigned int cas_latency) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 506 | { |
| 507 | /* Precharge-to-activate interval (tRP) */ |
| 508 | unsigned char pretoact_mclk; |
| 509 | /* Activate to precharge interval (tRAS) */ |
| 510 | unsigned char acttopre_mclk; |
| 511 | /* Activate to read/write interval (tRCD) */ |
| 512 | unsigned char acttorw_mclk; |
| 513 | /* CASLAT */ |
| 514 | unsigned char caslat_ctrl; |
| 515 | /* Refresh recovery time (tRFC) ; trfc_low */ |
| 516 | unsigned char refrec_ctrl; |
| 517 | /* Last data to precharge minimum interval (tWR) */ |
| 518 | unsigned char wrrec_mclk; |
| 519 | /* Activate-to-activate interval (tRRD) */ |
| 520 | unsigned char acttoact_mclk; |
| 521 | /* Last write data pair to read command issue interval (tWTR) */ |
| 522 | unsigned char wrtord_mclk; |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 523 | #ifdef CONFIG_SYS_FSL_DDR4 |
| 524 | /* DDR4 supports 10, 12, 14, 16, 18, 20, 24 */ |
| 525 | static const u8 wrrec_table[] = { |
| 526 | 10, 10, 10, 10, 10, |
| 527 | 10, 10, 10, 10, 10, |
| 528 | 12, 12, 14, 14, 16, |
| 529 | 16, 18, 18, 20, 20, |
| 530 | 24, 24, 24, 24}; |
| 531 | #else |
York Sun | 3673f2c | 2011-03-02 14:24:11 -0800 | [diff] [blame] | 532 | /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */ |
| 533 | static const u8 wrrec_table[] = { |
| 534 | 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0}; |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 535 | #endif |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 536 | |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 537 | pretoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trp_ps); |
| 538 | acttopre_mclk = picos_to_mclk(ctrl_num, common_dimm->tras_ps); |
| 539 | acttorw_mclk = picos_to_mclk(ctrl_num, common_dimm->trcd_ps); |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 540 | |
| 541 | /* |
| 542 | * Translate CAS Latency to a DDR controller field value: |
| 543 | * |
| 544 | * CAS Lat DDR I DDR II Ctrl |
| 545 | * Clocks SPD Bit SPD Bit Value |
| 546 | * ------- ------- ------- ----- |
| 547 | * 1.0 0 0001 |
| 548 | * 1.5 1 0010 |
| 549 | * 2.0 2 2 0011 |
| 550 | * 2.5 3 0100 |
| 551 | * 3.0 4 3 0101 |
| 552 | * 3.5 5 0110 |
| 553 | * 4.0 4 0111 |
| 554 | * 4.5 1000 |
| 555 | * 5.0 5 1001 |
| 556 | */ |
York Sun | f062659 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 557 | #if defined(CONFIG_SYS_FSL_DDR1) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 558 | caslat_ctrl = (cas_latency + 1) & 0x07; |
York Sun | f062659 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 559 | #elif defined(CONFIG_SYS_FSL_DDR2) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 560 | caslat_ctrl = 2 * cas_latency - 1; |
| 561 | #else |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 562 | /* |
| 563 | * if the CAS latency more than 8 cycle, |
| 564 | * we need set extend bit for it at |
| 565 | * TIMING_CFG_3[EXT_CASLAT] |
| 566 | */ |
York Sun | 55eb5fa | 2015-03-19 09:30:26 -0700 | [diff] [blame] | 567 | if (fsl_ddr_get_version(ctrl_num) <= 0x40400) |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 568 | caslat_ctrl = 2 * cas_latency - 1; |
| 569 | else |
| 570 | caslat_ctrl = (cas_latency - 1) << 1; |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 571 | #endif |
| 572 | |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 573 | #ifdef CONFIG_SYS_FSL_DDR4 |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 574 | refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8; |
| 575 | wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps); |
| 576 | acttoact_mclk = max(picos_to_mclk(ctrl_num, common_dimm->trrds_ps), 4U); |
| 577 | wrtord_mclk = max(2U, picos_to_mclk(ctrl_num, 2500)); |
York Sun | edbeee1 | 2014-04-01 14:20:49 -0700 | [diff] [blame] | 578 | if ((wrrec_mclk < 1) || (wrrec_mclk > 24)) |
| 579 | printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk); |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 580 | else |
| 581 | wrrec_mclk = wrrec_table[wrrec_mclk - 1]; |
| 582 | #else |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 583 | refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8; |
| 584 | wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps); |
| 585 | acttoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trrd_ps); |
| 586 | wrtord_mclk = picos_to_mclk(ctrl_num, common_dimm->twtr_ps); |
York Sun | edbeee1 | 2014-04-01 14:20:49 -0700 | [diff] [blame] | 587 | if ((wrrec_mclk < 1) || (wrrec_mclk > 16)) |
| 588 | printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk); |
York Sun | cd077cf | 2012-08-17 08:22:40 +0000 | [diff] [blame] | 589 | else |
| 590 | wrrec_mclk = wrrec_table[wrrec_mclk - 1]; |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 591 | #endif |
Priyanka Jain | 4a71741 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 592 | if (popts->otf_burst_chop_en) |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 593 | wrrec_mclk += 2; |
| 594 | |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 595 | /* |
| 596 | * JEDEC has min requirement for tRRD |
| 597 | */ |
York Sun | f062659 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 598 | #if defined(CONFIG_SYS_FSL_DDR3) |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 599 | if (acttoact_mclk < 4) |
| 600 | acttoact_mclk = 4; |
| 601 | #endif |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 602 | /* |
| 603 | * JEDEC has some min requirements for tWTR |
| 604 | */ |
York Sun | f062659 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 605 | #if defined(CONFIG_SYS_FSL_DDR2) |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 606 | if (wrtord_mclk < 2) |
| 607 | wrtord_mclk = 2; |
York Sun | f062659 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 608 | #elif defined(CONFIG_SYS_FSL_DDR3) |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 609 | if (wrtord_mclk < 4) |
| 610 | wrtord_mclk = 4; |
| 611 | #endif |
Priyanka Jain | 4a71741 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 612 | if (popts->otf_burst_chop_en) |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 613 | wrtord_mclk += 2; |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 614 | |
| 615 | ddr->timing_cfg_1 = (0 |
Dave Liu | 5c1bb51 | 2008-11-21 16:31:22 +0800 | [diff] [blame] | 616 | | ((pretoact_mclk & 0x0F) << 28) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 617 | | ((acttopre_mclk & 0x0F) << 24) |
Dave Liu | 5c1bb51 | 2008-11-21 16:31:22 +0800 | [diff] [blame] | 618 | | ((acttorw_mclk & 0xF) << 20) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 619 | | ((caslat_ctrl & 0xF) << 16) |
| 620 | | ((refrec_ctrl & 0xF) << 12) |
Dave Liu | 5c1bb51 | 2008-11-21 16:31:22 +0800 | [diff] [blame] | 621 | | ((wrrec_mclk & 0x0F) << 8) |
York Sun | 7d69ea3 | 2012-10-08 07:44:22 +0000 | [diff] [blame] | 622 | | ((acttoact_mclk & 0x0F) << 4) |
| 623 | | ((wrtord_mclk & 0x0F) << 0) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 624 | ); |
Haiying Wang | d90e040 | 2008-10-03 12:37:26 -0400 | [diff] [blame] | 625 | debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1); |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 626 | } |
| 627 | |
| 628 | /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */ |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 629 | static void set_timing_cfg_2(const unsigned int ctrl_num, |
| 630 | fsl_ddr_cfg_regs_t *ddr, |
| 631 | const memctl_options_t *popts, |
| 632 | const common_timing_params_t *common_dimm, |
| 633 | unsigned int cas_latency, |
| 634 | unsigned int additive_latency) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 635 | { |
| 636 | /* Additive latency */ |
| 637 | unsigned char add_lat_mclk; |
| 638 | /* CAS-to-preamble override */ |
| 639 | unsigned short cpo; |
| 640 | /* Write latency */ |
| 641 | unsigned char wr_lat; |
| 642 | /* Read to precharge (tRTP) */ |
| 643 | unsigned char rd_to_pre; |
| 644 | /* Write command to write data strobe timing adjustment */ |
| 645 | unsigned char wr_data_delay; |
| 646 | /* Minimum CKE pulse width (tCKE) */ |
| 647 | unsigned char cke_pls; |
| 648 | /* Window for four activates (tFAW) */ |
| 649 | unsigned short four_act; |
York Sun | c1bf24f | 2014-08-21 16:13:22 -0700 | [diff] [blame] | 650 | #ifdef CONFIG_SYS_FSL_DDR3 |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 651 | const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); |
York Sun | c1bf24f | 2014-08-21 16:13:22 -0700 | [diff] [blame] | 652 | #endif |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 653 | |
| 654 | /* FIXME add check that this must be less than acttorw_mclk */ |
| 655 | add_lat_mclk = additive_latency; |
| 656 | cpo = popts->cpo_override; |
| 657 | |
York Sun | f062659 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 658 | #if defined(CONFIG_SYS_FSL_DDR1) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 659 | /* |
| 660 | * This is a lie. It should really be 1, but if it is |
| 661 | * set to 1, bits overlap into the old controller's |
| 662 | * otherwise unused ACSM field. If we leave it 0, then |
| 663 | * the HW will magically treat it as 1 for DDR 1. Oh Yea. |
| 664 | */ |
| 665 | wr_lat = 0; |
York Sun | f062659 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 666 | #elif defined(CONFIG_SYS_FSL_DDR2) |
Dave Liu | 82aa953 | 2009-03-14 12:48:19 +0800 | [diff] [blame] | 667 | wr_lat = cas_latency - 1; |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 668 | #else |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 669 | wr_lat = compute_cas_write_latency(ctrl_num); |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 670 | #endif |
| 671 | |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 672 | #ifdef CONFIG_SYS_FSL_DDR4 |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 673 | rd_to_pre = picos_to_mclk(ctrl_num, 7500); |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 674 | #else |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 675 | rd_to_pre = picos_to_mclk(ctrl_num, common_dimm->trtp_ps); |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 676 | #endif |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 677 | /* |
| 678 | * JEDEC has some min requirements for tRTP |
| 679 | */ |
York Sun | f062659 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 680 | #if defined(CONFIG_SYS_FSL_DDR2) |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 681 | if (rd_to_pre < 2) |
| 682 | rd_to_pre = 2; |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 683 | #elif defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 684 | if (rd_to_pre < 4) |
| 685 | rd_to_pre = 4; |
Dave Liu | 82aa953 | 2009-03-14 12:48:19 +0800 | [diff] [blame] | 686 | #endif |
Priyanka Jain | 4a71741 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 687 | if (popts->otf_burst_chop_en) |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 688 | rd_to_pre += 2; /* according to UM */ |
| 689 | |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 690 | wr_data_delay = popts->write_data_delay; |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 691 | #ifdef CONFIG_SYS_FSL_DDR4 |
| 692 | cpo = 0; |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 693 | cke_pls = max(3U, picos_to_mclk(ctrl_num, 5000)); |
York Sun | c1bf24f | 2014-08-21 16:13:22 -0700 | [diff] [blame] | 694 | #elif defined(CONFIG_SYS_FSL_DDR3) |
| 695 | /* |
| 696 | * cke pulse = max(3nCK, 7.5ns) for DDR3-800 |
| 697 | * max(3nCK, 5.625ns) for DDR3-1066, 1333 |
| 698 | * max(3nCK, 5ns) for DDR3-1600, 1866, 2133 |
| 699 | */ |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 700 | cke_pls = max(3U, picos_to_mclk(ctrl_num, mclk_ps > 1870 ? 7500 : |
| 701 | (mclk_ps > 1245 ? 5625 : 5000))); |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 702 | #else |
York Sun | c1bf24f | 2014-08-21 16:13:22 -0700 | [diff] [blame] | 703 | cke_pls = FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR; |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 704 | #endif |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 705 | four_act = picos_to_mclk(ctrl_num, |
| 706 | popts->tfaw_window_four_activates_ps); |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 707 | |
| 708 | ddr->timing_cfg_2 = (0 |
Dave Liu | 4758d53 | 2008-11-21 16:31:29 +0800 | [diff] [blame] | 709 | | ((add_lat_mclk & 0xf) << 28) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 710 | | ((cpo & 0x1f) << 23) |
Dave Liu | 4758d53 | 2008-11-21 16:31:29 +0800 | [diff] [blame] | 711 | | ((wr_lat & 0xf) << 19) |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 712 | | ((wr_lat & 0x10) << 14) |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 713 | | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT) |
| 714 | | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 715 | | ((cke_pls & 0x7) << 6) |
Dave Liu | 4758d53 | 2008-11-21 16:31:29 +0800 | [diff] [blame] | 716 | | ((four_act & 0x3f) << 0) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 717 | ); |
Haiying Wang | d90e040 | 2008-10-03 12:37:26 -0400 | [diff] [blame] | 718 | debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2); |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 719 | } |
| 720 | |
york | de87932 | 2010-07-02 22:25:55 +0000 | [diff] [blame] | 721 | /* DDR SDRAM Register Control Word */ |
| 722 | static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr, |
York Sun | ba0c2eb | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 723 | const memctl_options_t *popts, |
york | de87932 | 2010-07-02 22:25:55 +0000 | [diff] [blame] | 724 | const common_timing_params_t *common_dimm) |
| 725 | { |
Priyanka Jain | 4a71741 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 726 | if (common_dimm->all_dimms_registered && |
| 727 | !common_dimm->all_dimms_unbuffered) { |
York Sun | ba0c2eb | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 728 | if (popts->rcw_override) { |
| 729 | ddr->ddr_sdram_rcw_1 = popts->rcw_1; |
| 730 | ddr->ddr_sdram_rcw_2 = popts->rcw_2; |
| 731 | } else { |
| 732 | ddr->ddr_sdram_rcw_1 = |
| 733 | common_dimm->rcw[0] << 28 | \ |
| 734 | common_dimm->rcw[1] << 24 | \ |
| 735 | common_dimm->rcw[2] << 20 | \ |
| 736 | common_dimm->rcw[3] << 16 | \ |
| 737 | common_dimm->rcw[4] << 12 | \ |
| 738 | common_dimm->rcw[5] << 8 | \ |
| 739 | common_dimm->rcw[6] << 4 | \ |
| 740 | common_dimm->rcw[7]; |
| 741 | ddr->ddr_sdram_rcw_2 = |
| 742 | common_dimm->rcw[8] << 28 | \ |
| 743 | common_dimm->rcw[9] << 24 | \ |
| 744 | common_dimm->rcw[10] << 20 | \ |
| 745 | common_dimm->rcw[11] << 16 | \ |
| 746 | common_dimm->rcw[12] << 12 | \ |
| 747 | common_dimm->rcw[13] << 8 | \ |
| 748 | common_dimm->rcw[14] << 4 | \ |
| 749 | common_dimm->rcw[15]; |
| 750 | } |
york | de87932 | 2010-07-02 22:25:55 +0000 | [diff] [blame] | 751 | debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1); |
| 752 | debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2); |
| 753 | } |
| 754 | } |
| 755 | |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 756 | /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */ |
| 757 | static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, |
| 758 | const memctl_options_t *popts, |
| 759 | const common_timing_params_t *common_dimm) |
| 760 | { |
| 761 | unsigned int mem_en; /* DDR SDRAM interface logic enable */ |
| 762 | unsigned int sren; /* Self refresh enable (during sleep) */ |
| 763 | unsigned int ecc_en; /* ECC enable. */ |
| 764 | unsigned int rd_en; /* Registered DIMM enable */ |
| 765 | unsigned int sdram_type; /* Type of SDRAM */ |
| 766 | unsigned int dyn_pwr; /* Dynamic power management mode */ |
| 767 | unsigned int dbw; /* DRAM dta bus width */ |
Dave Liu | 4758d53 | 2008-11-21 16:31:29 +0800 | [diff] [blame] | 768 | unsigned int eight_be = 0; /* 8-beat burst enable, DDR2 is zero */ |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 769 | unsigned int ncap = 0; /* Non-concurrent auto-precharge */ |
Priyanka Jain | 4a71741 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 770 | unsigned int threet_en; /* Enable 3T timing */ |
| 771 | unsigned int twot_en; /* Enable 2T timing */ |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 772 | unsigned int ba_intlv_ctl; /* Bank (CS) interleaving control */ |
| 773 | unsigned int x32_en = 0; /* x32 enable */ |
| 774 | unsigned int pchb8 = 0; /* precharge bit 8 enable */ |
| 775 | unsigned int hse; /* Global half strength override */ |
York Sun | 5d6c626 | 2014-09-05 13:52:41 +0800 | [diff] [blame] | 776 | unsigned int acc_ecc_en = 0; /* Accumulated ECC enable */ |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 777 | unsigned int mem_halt = 0; /* memory controller halt */ |
| 778 | unsigned int bi = 0; /* Bypass initialization */ |
| 779 | |
| 780 | mem_en = 1; |
| 781 | sren = popts->self_refresh_in_sleep; |
Priyanka Jain | 4a71741 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 782 | if (common_dimm->all_dimms_ecc_capable) { |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 783 | /* Allow setting of ECC only if all DIMMs are ECC. */ |
Priyanka Jain | 4a71741 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 784 | ecc_en = popts->ecc_mode; |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 785 | } else { |
| 786 | ecc_en = 0; |
| 787 | } |
| 788 | |
Priyanka Jain | 4a71741 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 789 | if (common_dimm->all_dimms_registered && |
| 790 | !common_dimm->all_dimms_unbuffered) { |
York Sun | ba0c2eb | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 791 | rd_en = 1; |
Priyanka Jain | 4a71741 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 792 | twot_en = 0; |
York Sun | ba0c2eb | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 793 | } else { |
| 794 | rd_en = 0; |
Priyanka Jain | 4a71741 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 795 | twot_en = popts->twot_en; |
York Sun | ba0c2eb | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 796 | } |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 797 | |
| 798 | sdram_type = CONFIG_FSL_SDRAM_TYPE; |
| 799 | |
| 800 | dyn_pwr = popts->dynamic_power; |
| 801 | dbw = popts->data_bus_width; |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 802 | /* 8-beat burst enable DDR-III case |
| 803 | * we must clear it when use the on-the-fly mode, |
| 804 | * must set it when use the 32-bits bus mode. |
| 805 | */ |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 806 | if ((sdram_type == SDRAM_TYPE_DDR3) || |
| 807 | (sdram_type == SDRAM_TYPE_DDR4)) { |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 808 | if (popts->burst_length == DDR_BL8) |
| 809 | eight_be = 1; |
| 810 | if (popts->burst_length == DDR_OTF) |
| 811 | eight_be = 0; |
| 812 | if (dbw == 0x1) |
| 813 | eight_be = 1; |
| 814 | } |
| 815 | |
Priyanka Jain | 4a71741 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 816 | threet_en = popts->threet_en; |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 817 | ba_intlv_ctl = popts->ba_intlv_ctl; |
| 818 | hse = popts->half_strength_driver_enable; |
| 819 | |
York Sun | 5d6c626 | 2014-09-05 13:52:41 +0800 | [diff] [blame] | 820 | /* set when ddr bus width < 64 */ |
| 821 | acc_ecc_en = (dbw != 0 && ecc_en == 1) ? 1 : 0; |
| 822 | |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 823 | ddr->ddr_sdram_cfg = (0 |
| 824 | | ((mem_en & 0x1) << 31) |
| 825 | | ((sren & 0x1) << 30) |
| 826 | | ((ecc_en & 0x1) << 29) |
| 827 | | ((rd_en & 0x1) << 28) |
| 828 | | ((sdram_type & 0x7) << 24) |
| 829 | | ((dyn_pwr & 0x1) << 21) |
| 830 | | ((dbw & 0x3) << 19) |
| 831 | | ((eight_be & 0x1) << 18) |
| 832 | | ((ncap & 0x1) << 17) |
Priyanka Jain | 4a71741 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 833 | | ((threet_en & 0x1) << 16) |
| 834 | | ((twot_en & 0x1) << 15) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 835 | | ((ba_intlv_ctl & 0x7F) << 8) |
| 836 | | ((x32_en & 0x1) << 5) |
| 837 | | ((pchb8 & 0x1) << 4) |
| 838 | | ((hse & 0x1) << 3) |
York Sun | 5d6c626 | 2014-09-05 13:52:41 +0800 | [diff] [blame] | 839 | | ((acc_ecc_en & 0x1) << 2) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 840 | | ((mem_halt & 0x1) << 1) |
| 841 | | ((bi & 0x1) << 0) |
| 842 | ); |
Haiying Wang | d90e040 | 2008-10-03 12:37:26 -0400 | [diff] [blame] | 843 | debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg); |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 844 | } |
| 845 | |
| 846 | /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */ |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 847 | static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num, |
| 848 | fsl_ddr_cfg_regs_t *ddr, |
York Sun | ba0c2eb | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 849 | const memctl_options_t *popts, |
| 850 | const unsigned int unq_mrs_en) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 851 | { |
| 852 | unsigned int frc_sr = 0; /* Force self refresh */ |
| 853 | unsigned int sr_ie = 0; /* Self-refresh interrupt enable */ |
York Sun | 15f874a | 2011-08-26 11:32:40 -0700 | [diff] [blame] | 854 | unsigned int odt_cfg = 0; /* ODT configuration */ |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 855 | unsigned int num_pr; /* Number of posted refreshes */ |
York Sun | 7d69ea3 | 2012-10-08 07:44:22 +0000 | [diff] [blame] | 856 | unsigned int slow = 0; /* DDR will be run less than 1250 */ |
York Sun | 4889c98 | 2013-06-25 11:37:47 -0700 | [diff] [blame] | 857 | unsigned int x4_en = 0; /* x4 DRAM enable */ |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 858 | unsigned int obc_cfg; /* On-The-Fly Burst Chop Cfg */ |
| 859 | unsigned int ap_en; /* Address Parity Enable */ |
| 860 | unsigned int d_init; /* DRAM data initialization */ |
| 861 | unsigned int rcw_en = 0; /* Register Control Word Enable */ |
| 862 | unsigned int md_en = 0; /* Mirrored DIMM Enable */ |
york | f4f93c6 | 2010-07-02 22:25:53 +0000 | [diff] [blame] | 863 | unsigned int qd_en = 0; /* quad-rank DIMM Enable */ |
York Sun | 15f874a | 2011-08-26 11:32:40 -0700 | [diff] [blame] | 864 | int i; |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 865 | #ifndef CONFIG_SYS_FSL_DDR4 |
| 866 | unsigned int dll_rst_dis = 1; /* DLL reset disable */ |
| 867 | unsigned int dqs_cfg; /* DQS configuration */ |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 868 | |
Priyanka Jain | 4a71741 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 869 | dqs_cfg = popts->dqs_config; |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 870 | #endif |
York Sun | 15f874a | 2011-08-26 11:32:40 -0700 | [diff] [blame] | 871 | for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { |
| 872 | if (popts->cs_local_opts[i].odt_rd_cfg |
| 873 | || popts->cs_local_opts[i].odt_wr_cfg) { |
| 874 | odt_cfg = SDRAM_CFG2_ODT_ONLY_READ; |
| 875 | break; |
| 876 | } |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 877 | } |
Joakim Tjernlund | 6dc192d | 2015-10-14 16:32:00 +0200 | [diff] [blame] | 878 | sr_ie = popts->self_refresh_interrupt_en; |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 879 | num_pr = 1; /* Make this configurable */ |
| 880 | |
| 881 | /* |
| 882 | * 8572 manual says |
| 883 | * {TIMING_CFG_1[PRETOACT] |
| 884 | * + [DDR_SDRAM_CFG_2[NUM_PR] |
| 885 | * * ({EXT_REFREC || REFREC} + 8 + 2)]} |
| 886 | * << DDR_SDRAM_INTERVAL[REFINT] |
| 887 | */ |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 888 | #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) |
Priyanka Jain | 4a71741 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 889 | obc_cfg = popts->otf_burst_chop_en; |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 890 | #else |
| 891 | obc_cfg = 0; |
| 892 | #endif |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 893 | |
York Sun | 7d69ea3 | 2012-10-08 07:44:22 +0000 | [diff] [blame] | 894 | #if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7) |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 895 | slow = get_ddr_freq(ctrl_num) < 1249000000; |
York Sun | 7d69ea3 | 2012-10-08 07:44:22 +0000 | [diff] [blame] | 896 | #endif |
| 897 | |
Shengzhou Liu | 5219944 | 2016-03-10 17:36:56 +0800 | [diff] [blame] | 898 | if (popts->registered_dimm_en) |
York Sun | ba0c2eb | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 899 | rcw_en = 1; |
Shengzhou Liu | 5219944 | 2016-03-10 17:36:56 +0800 | [diff] [blame] | 900 | |
| 901 | /* DDR4 can have address parity for UDIMM and discrete */ |
| 902 | if ((CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) && |
| 903 | (!popts->registered_dimm_en)) { |
York Sun | ba0c2eb | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 904 | ap_en = 0; |
Shengzhou Liu | 5219944 | 2016-03-10 17:36:56 +0800 | [diff] [blame] | 905 | } else { |
| 906 | ap_en = popts->ap_en; |
York Sun | ba0c2eb | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 907 | } |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 908 | |
York Sun | 4889c98 | 2013-06-25 11:37:47 -0700 | [diff] [blame] | 909 | x4_en = popts->x4_en ? 1 : 0; |
| 910 | |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 911 | #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) |
| 912 | /* Use the DDR controller to auto initialize memory. */ |
Priyanka Jain | 4a71741 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 913 | d_init = popts->ecc_init_using_memctl; |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 914 | ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE; |
| 915 | debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init); |
| 916 | #else |
| 917 | /* Memory will be initialized via DMA, or not at all. */ |
| 918 | d_init = 0; |
| 919 | #endif |
| 920 | |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 921 | #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 922 | md_en = popts->mirrored_dimm; |
| 923 | #endif |
york | f4f93c6 | 2010-07-02 22:25:53 +0000 | [diff] [blame] | 924 | qd_en = popts->quad_rank_present ? 1 : 0; |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 925 | ddr->ddr_sdram_cfg_2 = (0 |
| 926 | | ((frc_sr & 0x1) << 31) |
| 927 | | ((sr_ie & 0x1) << 30) |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 928 | #ifndef CONFIG_SYS_FSL_DDR4 |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 929 | | ((dll_rst_dis & 0x1) << 29) |
| 930 | | ((dqs_cfg & 0x3) << 26) |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 931 | #endif |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 932 | | ((odt_cfg & 0x3) << 21) |
| 933 | | ((num_pr & 0xf) << 12) |
York Sun | 7d69ea3 | 2012-10-08 07:44:22 +0000 | [diff] [blame] | 934 | | ((slow & 1) << 11) |
York Sun | 4889c98 | 2013-06-25 11:37:47 -0700 | [diff] [blame] | 935 | | (x4_en << 10) |
york | f4f93c6 | 2010-07-02 22:25:53 +0000 | [diff] [blame] | 936 | | (qd_en << 9) |
York Sun | ba0c2eb | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 937 | | (unq_mrs_en << 8) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 938 | | ((obc_cfg & 0x1) << 6) |
| 939 | | ((ap_en & 0x1) << 5) |
| 940 | | ((d_init & 0x1) << 4) |
| 941 | | ((rcw_en & 0x1) << 2) |
| 942 | | ((md_en & 0x1) << 0) |
| 943 | ); |
Haiying Wang | d90e040 | 2008-10-03 12:37:26 -0400 | [diff] [blame] | 944 | debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2); |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 945 | } |
| 946 | |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 947 | #ifdef CONFIG_SYS_FSL_DDR4 |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 948 | /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */ |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 949 | static void set_ddr_sdram_mode_2(const unsigned int ctrl_num, |
| 950 | fsl_ddr_cfg_regs_t *ddr, |
York Sun | ba0c2eb | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 951 | const memctl_options_t *popts, |
Valentin Longchamp | 0b81093 | 2013-10-18 11:47:20 +0200 | [diff] [blame] | 952 | const common_timing_params_t *common_dimm, |
York Sun | ba0c2eb | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 953 | const unsigned int unq_mrs_en) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 954 | { |
| 955 | unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */ |
| 956 | unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */ |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 957 | int i; |
| 958 | unsigned int wr_crc = 0; /* Disable */ |
| 959 | unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */ |
| 960 | unsigned int srt = 0; /* self-refresh temerature, normal range */ |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 961 | unsigned int cwl = compute_cas_write_latency(ctrl_num) - 9; |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 962 | unsigned int mpr = 0; /* serial */ |
| 963 | unsigned int wc_lat; |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 964 | const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 965 | |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 966 | if (popts->rtt_override) |
| 967 | rtt_wr = popts->rtt_wr_override_value; |
| 968 | else |
| 969 | rtt_wr = popts->cs_local_opts[0].odt_rtt_wr; |
| 970 | |
| 971 | if (common_dimm->extended_op_srt) |
| 972 | srt = common_dimm->extended_op_srt; |
| 973 | |
| 974 | esdmode2 = (0 |
| 975 | | ((wr_crc & 0x1) << 12) |
| 976 | | ((rtt_wr & 0x3) << 9) |
| 977 | | ((srt & 0x3) << 6) |
| 978 | | ((cwl & 0x7) << 3)); |
| 979 | |
| 980 | if (mclk_ps >= 1250) |
| 981 | wc_lat = 0; |
| 982 | else if (mclk_ps >= 833) |
| 983 | wc_lat = 1; |
| 984 | else |
| 985 | wc_lat = 2; |
| 986 | |
| 987 | esdmode3 = (0 |
| 988 | | ((mpr & 0x3) << 11) |
| 989 | | ((wc_lat & 0x3) << 9)); |
| 990 | |
| 991 | ddr->ddr_sdram_mode_2 = (0 |
| 992 | | ((esdmode2 & 0xFFFF) << 16) |
| 993 | | ((esdmode3 & 0xFFFF) << 0) |
| 994 | ); |
| 995 | debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2); |
| 996 | |
| 997 | if (unq_mrs_en) { /* unique mode registers are supported */ |
| 998 | for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { |
| 999 | if (popts->rtt_override) |
| 1000 | rtt_wr = popts->rtt_wr_override_value; |
| 1001 | else |
| 1002 | rtt_wr = popts->cs_local_opts[i].odt_rtt_wr; |
| 1003 | |
| 1004 | esdmode2 &= 0xF9FF; /* clear bit 10, 9 */ |
| 1005 | esdmode2 |= (rtt_wr & 0x3) << 9; |
| 1006 | switch (i) { |
| 1007 | case 1: |
| 1008 | ddr->ddr_sdram_mode_4 = (0 |
| 1009 | | ((esdmode2 & 0xFFFF) << 16) |
| 1010 | | ((esdmode3 & 0xFFFF) << 0) |
| 1011 | ); |
| 1012 | break; |
| 1013 | case 2: |
| 1014 | ddr->ddr_sdram_mode_6 = (0 |
| 1015 | | ((esdmode2 & 0xFFFF) << 16) |
| 1016 | | ((esdmode3 & 0xFFFF) << 0) |
| 1017 | ); |
| 1018 | break; |
| 1019 | case 3: |
| 1020 | ddr->ddr_sdram_mode_8 = (0 |
| 1021 | | ((esdmode2 & 0xFFFF) << 16) |
| 1022 | | ((esdmode3 & 0xFFFF) << 0) |
| 1023 | ); |
| 1024 | break; |
| 1025 | } |
| 1026 | } |
| 1027 | debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n", |
| 1028 | ddr->ddr_sdram_mode_4); |
| 1029 | debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n", |
| 1030 | ddr->ddr_sdram_mode_6); |
| 1031 | debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n", |
| 1032 | ddr->ddr_sdram_mode_8); |
| 1033 | } |
| 1034 | } |
| 1035 | #elif defined(CONFIG_SYS_FSL_DDR3) |
| 1036 | /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */ |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 1037 | static void set_ddr_sdram_mode_2(const unsigned int ctrl_num, |
| 1038 | fsl_ddr_cfg_regs_t *ddr, |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 1039 | const memctl_options_t *popts, |
| 1040 | const common_timing_params_t *common_dimm, |
| 1041 | const unsigned int unq_mrs_en) |
| 1042 | { |
| 1043 | unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */ |
| 1044 | unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */ |
Kumar Gala | 65b5be2 | 2011-01-20 01:53:15 -0600 | [diff] [blame] | 1045 | int i; |
Dave Liu | 2d0f125 | 2009-12-16 10:24:38 -0600 | [diff] [blame] | 1046 | unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */ |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1047 | unsigned int srt = 0; /* self-refresh temerature, normal range */ |
| 1048 | unsigned int asr = 0; /* auto self-refresh disable */ |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 1049 | unsigned int cwl = compute_cas_write_latency(ctrl_num) - 5; |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1050 | unsigned int pasr = 0; /* partial array self refresh disable */ |
| 1051 | |
Dave Liu | 2d0f125 | 2009-12-16 10:24:38 -0600 | [diff] [blame] | 1052 | if (popts->rtt_override) |
| 1053 | rtt_wr = popts->rtt_wr_override_value; |
York Sun | ba0c2eb | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 1054 | else |
| 1055 | rtt_wr = popts->cs_local_opts[0].odt_rtt_wr; |
Valentin Longchamp | 0b81093 | 2013-10-18 11:47:20 +0200 | [diff] [blame] | 1056 | |
| 1057 | if (common_dimm->extended_op_srt) |
| 1058 | srt = common_dimm->extended_op_srt; |
| 1059 | |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1060 | esdmode2 = (0 |
| 1061 | | ((rtt_wr & 0x3) << 9) |
| 1062 | | ((srt & 0x1) << 7) |
| 1063 | | ((asr & 0x1) << 6) |
| 1064 | | ((cwl & 0x7) << 3) |
| 1065 | | ((pasr & 0x7) << 0)); |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1066 | ddr->ddr_sdram_mode_2 = (0 |
| 1067 | | ((esdmode2 & 0xFFFF) << 16) |
| 1068 | | ((esdmode3 & 0xFFFF) << 0) |
| 1069 | ); |
Haiying Wang | d90e040 | 2008-10-03 12:37:26 -0400 | [diff] [blame] | 1070 | debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2); |
York Sun | ba0c2eb | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 1071 | |
York Sun | ba0c2eb | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 1072 | if (unq_mrs_en) { /* unique mode registers are supported */ |
Kumar Gala | d5bbe66 | 2011-11-09 10:05:10 -0600 | [diff] [blame] | 1073 | for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { |
York Sun | ba0c2eb | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 1074 | if (popts->rtt_override) |
| 1075 | rtt_wr = popts->rtt_wr_override_value; |
| 1076 | else |
| 1077 | rtt_wr = popts->cs_local_opts[i].odt_rtt_wr; |
| 1078 | |
| 1079 | esdmode2 &= 0xF9FF; /* clear bit 10, 9 */ |
| 1080 | esdmode2 |= (rtt_wr & 0x3) << 9; |
| 1081 | switch (i) { |
| 1082 | case 1: |
| 1083 | ddr->ddr_sdram_mode_4 = (0 |
| 1084 | | ((esdmode2 & 0xFFFF) << 16) |
| 1085 | | ((esdmode3 & 0xFFFF) << 0) |
| 1086 | ); |
| 1087 | break; |
| 1088 | case 2: |
| 1089 | ddr->ddr_sdram_mode_6 = (0 |
| 1090 | | ((esdmode2 & 0xFFFF) << 16) |
| 1091 | | ((esdmode3 & 0xFFFF) << 0) |
| 1092 | ); |
| 1093 | break; |
| 1094 | case 3: |
| 1095 | ddr->ddr_sdram_mode_8 = (0 |
| 1096 | | ((esdmode2 & 0xFFFF) << 16) |
| 1097 | | ((esdmode3 & 0xFFFF) << 0) |
| 1098 | ); |
| 1099 | break; |
| 1100 | } |
| 1101 | } |
| 1102 | debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n", |
| 1103 | ddr->ddr_sdram_mode_4); |
| 1104 | debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n", |
| 1105 | ddr->ddr_sdram_mode_6); |
| 1106 | debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n", |
| 1107 | ddr->ddr_sdram_mode_8); |
| 1108 | } |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 1109 | } |
| 1110 | |
| 1111 | #else /* for DDR2 and DDR1 */ |
| 1112 | /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */ |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 1113 | static void set_ddr_sdram_mode_2(const unsigned int ctrl_num, |
| 1114 | fsl_ddr_cfg_regs_t *ddr, |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 1115 | const memctl_options_t *popts, |
| 1116 | const common_timing_params_t *common_dimm, |
| 1117 | const unsigned int unq_mrs_en) |
| 1118 | { |
| 1119 | unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */ |
| 1120 | unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */ |
| 1121 | |
| 1122 | ddr->ddr_sdram_mode_2 = (0 |
| 1123 | | ((esdmode2 & 0xFFFF) << 16) |
| 1124 | | ((esdmode3 & 0xFFFF) << 0) |
| 1125 | ); |
| 1126 | debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2); |
| 1127 | } |
York Sun | ba0c2eb | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 1128 | #endif |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 1129 | |
| 1130 | #ifdef CONFIG_SYS_FSL_DDR4 |
| 1131 | /* DDR SDRAM Mode configuration 9 (DDR_SDRAM_MODE_9) */ |
| 1132 | static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr, |
| 1133 | const memctl_options_t *popts, |
| 1134 | const common_timing_params_t *common_dimm, |
| 1135 | const unsigned int unq_mrs_en) |
| 1136 | { |
| 1137 | int i; |
| 1138 | unsigned short esdmode4 = 0; /* Extended SDRAM mode 4 */ |
| 1139 | unsigned short esdmode5; /* Extended SDRAM mode 5 */ |
York Sun | fc63b28 | 2015-03-19 09:30:27 -0700 | [diff] [blame] | 1140 | int rtt_park = 0; |
York Sun | d192126 | 2015-11-04 10:03:19 -0800 | [diff] [blame] | 1141 | bool four_cs = false; |
Shengzhou Liu | 5219944 | 2016-03-10 17:36:56 +0800 | [diff] [blame] | 1142 | const unsigned int mclk_ps = get_memory_clk_period_ps(0); |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 1143 | |
York Sun | d192126 | 2015-11-04 10:03:19 -0800 | [diff] [blame] | 1144 | #if CONFIG_CHIP_SELECTS_PER_CTRL == 4 |
| 1145 | if ((ddr->cs[0].config & SDRAM_CS_CONFIG_EN) && |
| 1146 | (ddr->cs[1].config & SDRAM_CS_CONFIG_EN) && |
| 1147 | (ddr->cs[2].config & SDRAM_CS_CONFIG_EN) && |
| 1148 | (ddr->cs[3].config & SDRAM_CS_CONFIG_EN)) |
| 1149 | four_cs = true; |
| 1150 | #endif |
York Sun | fc63b28 | 2015-03-19 09:30:27 -0700 | [diff] [blame] | 1151 | if (ddr->cs[0].config & SDRAM_CS_CONFIG_EN) { |
| 1152 | esdmode5 = 0x00000500; /* Data mask enable, RTT_PARK CS0 */ |
York Sun | d192126 | 2015-11-04 10:03:19 -0800 | [diff] [blame] | 1153 | rtt_park = four_cs ? 0 : 1; |
York Sun | fc63b28 | 2015-03-19 09:30:27 -0700 | [diff] [blame] | 1154 | } else { |
| 1155 | esdmode5 = 0x00000400; /* Data mask enabled */ |
| 1156 | } |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 1157 | |
Shengzhou Liu | 5219944 | 2016-03-10 17:36:56 +0800 | [diff] [blame] | 1158 | /* set command/address parity latency */ |
| 1159 | if (ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) { |
| 1160 | if (mclk_ps >= 935) { |
| 1161 | /* for DDR4-1600/1866/2133 */ |
| 1162 | esdmode5 |= DDR_MR5_CA_PARITY_LAT_4_CLK; |
| 1163 | } else if (mclk_ps >= 833) { |
| 1164 | /* for DDR4-2400 */ |
| 1165 | esdmode5 |= DDR_MR5_CA_PARITY_LAT_5_CLK; |
| 1166 | } else { |
| 1167 | printf("parity: mclk_ps = %d not supported\n", mclk_ps); |
| 1168 | } |
| 1169 | } |
| 1170 | |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 1171 | ddr->ddr_sdram_mode_9 = (0 |
| 1172 | | ((esdmode4 & 0xffff) << 16) |
| 1173 | | ((esdmode5 & 0xffff) << 0) |
| 1174 | ); |
York Sun | 55eb5fa | 2015-03-19 09:30:26 -0700 | [diff] [blame] | 1175 | |
York Sun | d192126 | 2015-11-04 10:03:19 -0800 | [diff] [blame] | 1176 | /* Normally only the first enabled CS use 0x500, others use 0x400 |
| 1177 | * But when four chip-selects are all enabled, all mode registers |
| 1178 | * need 0x500 to park. |
| 1179 | */ |
York Sun | 55eb5fa | 2015-03-19 09:30:26 -0700 | [diff] [blame] | 1180 | |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 1181 | debug("FSLDDR: ddr_sdram_mode_9) = 0x%08x\n", ddr->ddr_sdram_mode_9); |
| 1182 | if (unq_mrs_en) { /* unique mode registers are supported */ |
| 1183 | for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { |
York Sun | fc63b28 | 2015-03-19 09:30:27 -0700 | [diff] [blame] | 1184 | if (!rtt_park && |
| 1185 | (ddr->cs[i].config & SDRAM_CS_CONFIG_EN)) { |
| 1186 | esdmode5 |= 0x00000500; /* RTT_PARK */ |
York Sun | d192126 | 2015-11-04 10:03:19 -0800 | [diff] [blame] | 1187 | rtt_park = four_cs ? 0 : 1; |
York Sun | fc63b28 | 2015-03-19 09:30:27 -0700 | [diff] [blame] | 1188 | } else { |
| 1189 | esdmode5 = 0x00000400; |
| 1190 | } |
Shengzhou Liu | 5219944 | 2016-03-10 17:36:56 +0800 | [diff] [blame] | 1191 | |
| 1192 | if (ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) { |
| 1193 | if (mclk_ps >= 935) { |
| 1194 | /* for DDR4-1600/1866/2133 */ |
| 1195 | esdmode5 |= DDR_MR5_CA_PARITY_LAT_4_CLK; |
| 1196 | } else if (mclk_ps >= 833) { |
| 1197 | /* for DDR4-2400 */ |
| 1198 | esdmode5 |= DDR_MR5_CA_PARITY_LAT_5_CLK; |
| 1199 | } else { |
| 1200 | printf("parity: mclk_ps = %d not supported\n", |
| 1201 | mclk_ps); |
| 1202 | } |
| 1203 | } |
| 1204 | |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 1205 | switch (i) { |
| 1206 | case 1: |
| 1207 | ddr->ddr_sdram_mode_11 = (0 |
| 1208 | | ((esdmode4 & 0xFFFF) << 16) |
| 1209 | | ((esdmode5 & 0xFFFF) << 0) |
| 1210 | ); |
| 1211 | break; |
| 1212 | case 2: |
| 1213 | ddr->ddr_sdram_mode_13 = (0 |
| 1214 | | ((esdmode4 & 0xFFFF) << 16) |
| 1215 | | ((esdmode5 & 0xFFFF) << 0) |
| 1216 | ); |
| 1217 | break; |
| 1218 | case 3: |
| 1219 | ddr->ddr_sdram_mode_15 = (0 |
| 1220 | | ((esdmode4 & 0xFFFF) << 16) |
| 1221 | | ((esdmode5 & 0xFFFF) << 0) |
| 1222 | ); |
| 1223 | break; |
| 1224 | } |
| 1225 | } |
| 1226 | debug("FSLDDR: ddr_sdram_mode_11 = 0x%08x\n", |
| 1227 | ddr->ddr_sdram_mode_11); |
| 1228 | debug("FSLDDR: ddr_sdram_mode_13 = 0x%08x\n", |
| 1229 | ddr->ddr_sdram_mode_13); |
| 1230 | debug("FSLDDR: ddr_sdram_mode_15 = 0x%08x\n", |
| 1231 | ddr->ddr_sdram_mode_15); |
| 1232 | } |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1233 | } |
| 1234 | |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 1235 | /* DDR SDRAM Mode configuration 10 (DDR_SDRAM_MODE_10) */ |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 1236 | static void set_ddr_sdram_mode_10(const unsigned int ctrl_num, |
| 1237 | fsl_ddr_cfg_regs_t *ddr, |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 1238 | const memctl_options_t *popts, |
| 1239 | const common_timing_params_t *common_dimm, |
| 1240 | const unsigned int unq_mrs_en) |
| 1241 | { |
| 1242 | int i; |
| 1243 | unsigned short esdmode6 = 0; /* Extended SDRAM mode 6 */ |
| 1244 | unsigned short esdmode7 = 0; /* Extended SDRAM mode 7 */ |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 1245 | unsigned int tccdl_min = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps); |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 1246 | |
| 1247 | esdmode6 = ((tccdl_min - 4) & 0x7) << 10; |
| 1248 | |
York Sun | d4d97ef | 2015-11-04 10:03:18 -0800 | [diff] [blame] | 1249 | if (popts->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2) |
| 1250 | esdmode6 |= 1 << 6; /* Range 2 */ |
| 1251 | |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 1252 | ddr->ddr_sdram_mode_10 = (0 |
| 1253 | | ((esdmode6 & 0xffff) << 16) |
| 1254 | | ((esdmode7 & 0xffff) << 0) |
| 1255 | ); |
| 1256 | debug("FSLDDR: ddr_sdram_mode_10) = 0x%08x\n", ddr->ddr_sdram_mode_10); |
| 1257 | if (unq_mrs_en) { /* unique mode registers are supported */ |
| 1258 | for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { |
| 1259 | switch (i) { |
| 1260 | case 1: |
| 1261 | ddr->ddr_sdram_mode_12 = (0 |
| 1262 | | ((esdmode6 & 0xFFFF) << 16) |
| 1263 | | ((esdmode7 & 0xFFFF) << 0) |
| 1264 | ); |
| 1265 | break; |
| 1266 | case 2: |
| 1267 | ddr->ddr_sdram_mode_14 = (0 |
| 1268 | | ((esdmode6 & 0xFFFF) << 16) |
| 1269 | | ((esdmode7 & 0xFFFF) << 0) |
| 1270 | ); |
| 1271 | break; |
| 1272 | case 3: |
| 1273 | ddr->ddr_sdram_mode_16 = (0 |
| 1274 | | ((esdmode6 & 0xFFFF) << 16) |
| 1275 | | ((esdmode7 & 0xFFFF) << 0) |
| 1276 | ); |
| 1277 | break; |
| 1278 | } |
| 1279 | } |
| 1280 | debug("FSLDDR: ddr_sdram_mode_12 = 0x%08x\n", |
| 1281 | ddr->ddr_sdram_mode_12); |
| 1282 | debug("FSLDDR: ddr_sdram_mode_14 = 0x%08x\n", |
| 1283 | ddr->ddr_sdram_mode_14); |
| 1284 | debug("FSLDDR: ddr_sdram_mode_16 = 0x%08x\n", |
| 1285 | ddr->ddr_sdram_mode_16); |
| 1286 | } |
| 1287 | } |
| 1288 | |
| 1289 | #endif |
| 1290 | |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1291 | /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */ |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 1292 | static void set_ddr_sdram_interval(const unsigned int ctrl_num, |
| 1293 | fsl_ddr_cfg_regs_t *ddr, |
| 1294 | const memctl_options_t *popts, |
| 1295 | const common_timing_params_t *common_dimm) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1296 | { |
| 1297 | unsigned int refint; /* Refresh interval */ |
| 1298 | unsigned int bstopre; /* Precharge interval */ |
| 1299 | |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 1300 | refint = picos_to_mclk(ctrl_num, common_dimm->refresh_rate_ps); |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1301 | |
| 1302 | bstopre = popts->bstopre; |
| 1303 | |
| 1304 | /* refint field used 0x3FFF in earlier controllers */ |
| 1305 | ddr->ddr_sdram_interval = (0 |
| 1306 | | ((refint & 0xFFFF) << 16) |
| 1307 | | ((bstopre & 0x3FFF) << 0) |
| 1308 | ); |
Haiying Wang | d90e040 | 2008-10-03 12:37:26 -0400 | [diff] [blame] | 1309 | debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval); |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1310 | } |
| 1311 | |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 1312 | #ifdef CONFIG_SYS_FSL_DDR4 |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1313 | /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */ |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 1314 | static void set_ddr_sdram_mode(const unsigned int ctrl_num, |
| 1315 | fsl_ddr_cfg_regs_t *ddr, |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1316 | const memctl_options_t *popts, |
| 1317 | const common_timing_params_t *common_dimm, |
| 1318 | unsigned int cas_latency, |
York Sun | ba0c2eb | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 1319 | unsigned int additive_latency, |
| 1320 | const unsigned int unq_mrs_en) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1321 | { |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 1322 | int i; |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1323 | unsigned short esdmode; /* Extended SDRAM mode */ |
| 1324 | unsigned short sdmode; /* SDRAM mode */ |
| 1325 | |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1326 | /* Mode Register - MR1 */ |
| 1327 | unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */ |
| 1328 | unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */ |
| 1329 | unsigned int rtt; |
| 1330 | unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */ |
| 1331 | unsigned int al = 0; /* Posted CAS# additive latency (AL) */ |
York Sun | ba0c2eb | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 1332 | unsigned int dic = 0; /* Output driver impedance, 40ohm */ |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 1333 | unsigned int dll_en = 1; /* DLL Enable 1=Enable (Normal), |
| 1334 | 0=Disable (Test/Debug) */ |
| 1335 | |
| 1336 | /* Mode Register - MR0 */ |
| 1337 | unsigned int wr = 0; /* Write Recovery */ |
| 1338 | unsigned int dll_rst; /* DLL Reset */ |
| 1339 | unsigned int mode; /* Normal=0 or Test=1 */ |
| 1340 | unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */ |
| 1341 | /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */ |
| 1342 | unsigned int bt; |
| 1343 | unsigned int bl; /* BL: Burst Length */ |
| 1344 | |
| 1345 | unsigned int wr_mclk; |
| 1346 | /* DDR4 support WR 10, 12, 14, 16, 18, 20, 24 */ |
| 1347 | static const u8 wr_table[] = { |
| 1348 | 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 6}; |
| 1349 | /* DDR4 support CAS 9, 10, 11, 12, 13, 14, 15, 16, 18, 20, 22, 24 */ |
| 1350 | static const u8 cas_latency_table[] = { |
| 1351 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 8, |
| 1352 | 9, 9, 10, 10, 11, 11}; |
| 1353 | |
| 1354 | if (popts->rtt_override) |
| 1355 | rtt = popts->rtt_override_value; |
| 1356 | else |
| 1357 | rtt = popts->cs_local_opts[0].odt_rtt_norm; |
| 1358 | |
| 1359 | if (additive_latency == (cas_latency - 1)) |
| 1360 | al = 1; |
| 1361 | if (additive_latency == (cas_latency - 2)) |
| 1362 | al = 2; |
| 1363 | |
| 1364 | if (popts->quad_rank_present) |
| 1365 | dic = 1; /* output driver impedance 240/7 ohm */ |
| 1366 | |
| 1367 | /* |
| 1368 | * The esdmode value will also be used for writing |
| 1369 | * MR1 during write leveling for DDR3, although the |
| 1370 | * bits specifically related to the write leveling |
| 1371 | * scheme will be handled automatically by the DDR |
| 1372 | * controller. so we set the wrlvl_en = 0 here. |
| 1373 | */ |
| 1374 | esdmode = (0 |
| 1375 | | ((qoff & 0x1) << 12) |
| 1376 | | ((tdqs_en & 0x1) << 11) |
| 1377 | | ((rtt & 0x7) << 8) |
| 1378 | | ((wrlvl_en & 0x1) << 7) |
| 1379 | | ((al & 0x3) << 3) |
| 1380 | | ((dic & 0x3) << 1) /* DIC field is split */ |
| 1381 | | ((dll_en & 0x1) << 0) |
| 1382 | ); |
| 1383 | |
| 1384 | /* |
| 1385 | * DLL control for precharge PD |
| 1386 | * 0=slow exit DLL off (tXPDLL) |
| 1387 | * 1=fast exit DLL on (tXP) |
| 1388 | */ |
| 1389 | |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 1390 | wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps); |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 1391 | if (wr_mclk <= 24) { |
| 1392 | wr = wr_table[wr_mclk - 10]; |
| 1393 | } else { |
| 1394 | printf("Error: unsupported write recovery for mode register wr_mclk = %d\n", |
| 1395 | wr_mclk); |
| 1396 | } |
| 1397 | |
| 1398 | dll_rst = 0; /* dll no reset */ |
| 1399 | mode = 0; /* normal mode */ |
| 1400 | |
| 1401 | /* look up table to get the cas latency bits */ |
| 1402 | if (cas_latency >= 9 && cas_latency <= 24) |
| 1403 | caslat = cas_latency_table[cas_latency - 9]; |
| 1404 | else |
| 1405 | printf("Error: unsupported cas latency for mode register\n"); |
| 1406 | |
| 1407 | bt = 0; /* Nibble sequential */ |
| 1408 | |
| 1409 | switch (popts->burst_length) { |
| 1410 | case DDR_BL8: |
| 1411 | bl = 0; |
| 1412 | break; |
| 1413 | case DDR_OTF: |
| 1414 | bl = 1; |
| 1415 | break; |
| 1416 | case DDR_BC4: |
| 1417 | bl = 2; |
| 1418 | break; |
| 1419 | default: |
| 1420 | printf("Error: invalid burst length of %u specified. ", |
| 1421 | popts->burst_length); |
| 1422 | puts("Defaulting to on-the-fly BC4 or BL8 beats.\n"); |
| 1423 | bl = 1; |
| 1424 | break; |
| 1425 | } |
| 1426 | |
| 1427 | sdmode = (0 |
| 1428 | | ((wr & 0x7) << 9) |
| 1429 | | ((dll_rst & 0x1) << 8) |
| 1430 | | ((mode & 0x1) << 7) |
| 1431 | | (((caslat >> 1) & 0x7) << 4) |
| 1432 | | ((bt & 0x1) << 3) |
| 1433 | | ((caslat & 1) << 2) |
| 1434 | | ((bl & 0x3) << 0) |
| 1435 | ); |
| 1436 | |
| 1437 | ddr->ddr_sdram_mode = (0 |
| 1438 | | ((esdmode & 0xFFFF) << 16) |
| 1439 | | ((sdmode & 0xFFFF) << 0) |
| 1440 | ); |
| 1441 | |
| 1442 | debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode); |
| 1443 | |
| 1444 | if (unq_mrs_en) { /* unique mode registers are supported */ |
| 1445 | for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { |
| 1446 | if (popts->rtt_override) |
| 1447 | rtt = popts->rtt_override_value; |
| 1448 | else |
| 1449 | rtt = popts->cs_local_opts[i].odt_rtt_norm; |
| 1450 | |
| 1451 | esdmode &= 0xF8FF; /* clear bit 10,9,8 for rtt */ |
| 1452 | esdmode |= (rtt & 0x7) << 8; |
| 1453 | switch (i) { |
| 1454 | case 1: |
| 1455 | ddr->ddr_sdram_mode_3 = (0 |
| 1456 | | ((esdmode & 0xFFFF) << 16) |
| 1457 | | ((sdmode & 0xFFFF) << 0) |
| 1458 | ); |
| 1459 | break; |
| 1460 | case 2: |
| 1461 | ddr->ddr_sdram_mode_5 = (0 |
| 1462 | | ((esdmode & 0xFFFF) << 16) |
| 1463 | | ((sdmode & 0xFFFF) << 0) |
| 1464 | ); |
| 1465 | break; |
| 1466 | case 3: |
| 1467 | ddr->ddr_sdram_mode_7 = (0 |
| 1468 | | ((esdmode & 0xFFFF) << 16) |
| 1469 | | ((sdmode & 0xFFFF) << 0) |
| 1470 | ); |
| 1471 | break; |
| 1472 | } |
| 1473 | } |
| 1474 | debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n", |
| 1475 | ddr->ddr_sdram_mode_3); |
| 1476 | debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n", |
| 1477 | ddr->ddr_sdram_mode_5); |
| 1478 | debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n", |
| 1479 | ddr->ddr_sdram_mode_5); |
| 1480 | } |
| 1481 | } |
| 1482 | |
| 1483 | #elif defined(CONFIG_SYS_FSL_DDR3) |
| 1484 | /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */ |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 1485 | static void set_ddr_sdram_mode(const unsigned int ctrl_num, |
| 1486 | fsl_ddr_cfg_regs_t *ddr, |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 1487 | const memctl_options_t *popts, |
| 1488 | const common_timing_params_t *common_dimm, |
| 1489 | unsigned int cas_latency, |
| 1490 | unsigned int additive_latency, |
| 1491 | const unsigned int unq_mrs_en) |
| 1492 | { |
| 1493 | int i; |
| 1494 | unsigned short esdmode; /* Extended SDRAM mode */ |
| 1495 | unsigned short sdmode; /* SDRAM mode */ |
| 1496 | |
| 1497 | /* Mode Register - MR1 */ |
| 1498 | unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */ |
| 1499 | unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */ |
| 1500 | unsigned int rtt; |
| 1501 | unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */ |
| 1502 | unsigned int al = 0; /* Posted CAS# additive latency (AL) */ |
| 1503 | unsigned int dic = 0; /* Output driver impedance, 40ohm */ |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1504 | unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal), |
| 1505 | 1=Disable (Test/Debug) */ |
| 1506 | |
| 1507 | /* Mode Register - MR0 */ |
| 1508 | unsigned int dll_on; /* DLL control for precharge PD, 0=off, 1=on */ |
York Sun | bad8209 | 2012-08-17 08:22:38 +0000 | [diff] [blame] | 1509 | unsigned int wr = 0; /* Write Recovery */ |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1510 | unsigned int dll_rst; /* DLL Reset */ |
| 1511 | unsigned int mode; /* Normal=0 or Test=1 */ |
| 1512 | unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */ |
| 1513 | /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */ |
| 1514 | unsigned int bt; |
| 1515 | unsigned int bl; /* BL: Burst Length */ |
| 1516 | |
| 1517 | unsigned int wr_mclk; |
York Sun | 3673f2c | 2011-03-02 14:24:11 -0800 | [diff] [blame] | 1518 | /* |
| 1519 | * DDR_SDRAM_MODE doesn't support 9,11,13,15 |
| 1520 | * Please refer JEDEC Standard No. 79-3E for Mode Register MR0 |
| 1521 | * for this table |
| 1522 | */ |
| 1523 | static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0}; |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1524 | |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1525 | if (popts->rtt_override) |
| 1526 | rtt = popts->rtt_override_value; |
York Sun | ba0c2eb | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 1527 | else |
| 1528 | rtt = popts->cs_local_opts[0].odt_rtt_norm; |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1529 | |
| 1530 | if (additive_latency == (cas_latency - 1)) |
| 1531 | al = 1; |
| 1532 | if (additive_latency == (cas_latency - 2)) |
| 1533 | al = 2; |
| 1534 | |
York Sun | ba0c2eb | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 1535 | if (popts->quad_rank_present) |
| 1536 | dic = 1; /* output driver impedance 240/7 ohm */ |
| 1537 | |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1538 | /* |
| 1539 | * The esdmode value will also be used for writing |
| 1540 | * MR1 during write leveling for DDR3, although the |
| 1541 | * bits specifically related to the write leveling |
| 1542 | * scheme will be handled automatically by the DDR |
| 1543 | * controller. so we set the wrlvl_en = 0 here. |
| 1544 | */ |
| 1545 | esdmode = (0 |
| 1546 | | ((qoff & 0x1) << 12) |
| 1547 | | ((tdqs_en & 0x1) << 11) |
Kumar Gala | 14f2eb1 | 2009-09-10 14:54:55 -0500 | [diff] [blame] | 1548 | | ((rtt & 0x4) << 7) /* rtt field is split */ |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1549 | | ((wrlvl_en & 0x1) << 7) |
Kumar Gala | 14f2eb1 | 2009-09-10 14:54:55 -0500 | [diff] [blame] | 1550 | | ((rtt & 0x2) << 5) /* rtt field is split */ |
| 1551 | | ((dic & 0x2) << 4) /* DIC field is split */ |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1552 | | ((al & 0x3) << 3) |
Kumar Gala | 14f2eb1 | 2009-09-10 14:54:55 -0500 | [diff] [blame] | 1553 | | ((rtt & 0x1) << 2) /* rtt field is split */ |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1554 | | ((dic & 0x1) << 1) /* DIC field is split */ |
| 1555 | | ((dll_en & 0x1) << 0) |
| 1556 | ); |
| 1557 | |
| 1558 | /* |
| 1559 | * DLL control for precharge PD |
| 1560 | * 0=slow exit DLL off (tXPDLL) |
| 1561 | * 1=fast exit DLL on (tXP) |
| 1562 | */ |
| 1563 | dll_on = 1; |
York Sun | 3673f2c | 2011-03-02 14:24:11 -0800 | [diff] [blame] | 1564 | |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 1565 | wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps); |
York Sun | bad8209 | 2012-08-17 08:22:38 +0000 | [diff] [blame] | 1566 | if (wr_mclk <= 16) { |
| 1567 | wr = wr_table[wr_mclk - 5]; |
| 1568 | } else { |
| 1569 | printf("Error: unsupported write recovery for mode register " |
| 1570 | "wr_mclk = %d\n", wr_mclk); |
| 1571 | } |
York Sun | 3673f2c | 2011-03-02 14:24:11 -0800 | [diff] [blame] | 1572 | |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1573 | dll_rst = 0; /* dll no reset */ |
| 1574 | mode = 0; /* normal mode */ |
| 1575 | |
| 1576 | /* look up table to get the cas latency bits */ |
York Sun | bad8209 | 2012-08-17 08:22:38 +0000 | [diff] [blame] | 1577 | if (cas_latency >= 5 && cas_latency <= 16) { |
| 1578 | unsigned char cas_latency_table[] = { |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1579 | 0x2, /* 5 clocks */ |
| 1580 | 0x4, /* 6 clocks */ |
| 1581 | 0x6, /* 7 clocks */ |
| 1582 | 0x8, /* 8 clocks */ |
| 1583 | 0xa, /* 9 clocks */ |
| 1584 | 0xc, /* 10 clocks */ |
York Sun | bad8209 | 2012-08-17 08:22:38 +0000 | [diff] [blame] | 1585 | 0xe, /* 11 clocks */ |
| 1586 | 0x1, /* 12 clocks */ |
| 1587 | 0x3, /* 13 clocks */ |
| 1588 | 0x5, /* 14 clocks */ |
| 1589 | 0x7, /* 15 clocks */ |
| 1590 | 0x9, /* 16 clocks */ |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1591 | }; |
| 1592 | caslat = cas_latency_table[cas_latency - 5]; |
York Sun | bad8209 | 2012-08-17 08:22:38 +0000 | [diff] [blame] | 1593 | } else { |
| 1594 | printf("Error: unsupported cas latency for mode register\n"); |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1595 | } |
York Sun | bad8209 | 2012-08-17 08:22:38 +0000 | [diff] [blame] | 1596 | |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1597 | bt = 0; /* Nibble sequential */ |
| 1598 | |
| 1599 | switch (popts->burst_length) { |
| 1600 | case DDR_BL8: |
| 1601 | bl = 0; |
| 1602 | break; |
| 1603 | case DDR_OTF: |
| 1604 | bl = 1; |
| 1605 | break; |
| 1606 | case DDR_BC4: |
| 1607 | bl = 2; |
| 1608 | break; |
| 1609 | default: |
| 1610 | printf("Error: invalid burst length of %u specified. " |
| 1611 | " Defaulting to on-the-fly BC4 or BL8 beats.\n", |
| 1612 | popts->burst_length); |
| 1613 | bl = 1; |
| 1614 | break; |
| 1615 | } |
| 1616 | |
| 1617 | sdmode = (0 |
| 1618 | | ((dll_on & 0x1) << 12) |
| 1619 | | ((wr & 0x7) << 9) |
| 1620 | | ((dll_rst & 0x1) << 8) |
| 1621 | | ((mode & 0x1) << 7) |
| 1622 | | (((caslat >> 1) & 0x7) << 4) |
| 1623 | | ((bt & 0x1) << 3) |
York Sun | bad8209 | 2012-08-17 08:22:38 +0000 | [diff] [blame] | 1624 | | ((caslat & 1) << 2) |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1625 | | ((bl & 0x3) << 0) |
| 1626 | ); |
| 1627 | |
| 1628 | ddr->ddr_sdram_mode = (0 |
| 1629 | | ((esdmode & 0xFFFF) << 16) |
| 1630 | | ((sdmode & 0xFFFF) << 0) |
| 1631 | ); |
| 1632 | |
| 1633 | debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode); |
York Sun | ba0c2eb | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 1634 | |
| 1635 | if (unq_mrs_en) { /* unique mode registers are supported */ |
Kumar Gala | d5bbe66 | 2011-11-09 10:05:10 -0600 | [diff] [blame] | 1636 | for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { |
York Sun | ba0c2eb | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 1637 | if (popts->rtt_override) |
| 1638 | rtt = popts->rtt_override_value; |
| 1639 | else |
| 1640 | rtt = popts->cs_local_opts[i].odt_rtt_norm; |
| 1641 | |
| 1642 | esdmode &= 0xFDBB; /* clear bit 9,6,2 */ |
| 1643 | esdmode |= (0 |
| 1644 | | ((rtt & 0x4) << 7) /* rtt field is split */ |
| 1645 | | ((rtt & 0x2) << 5) /* rtt field is split */ |
| 1646 | | ((rtt & 0x1) << 2) /* rtt field is split */ |
| 1647 | ); |
| 1648 | switch (i) { |
| 1649 | case 1: |
| 1650 | ddr->ddr_sdram_mode_3 = (0 |
| 1651 | | ((esdmode & 0xFFFF) << 16) |
| 1652 | | ((sdmode & 0xFFFF) << 0) |
| 1653 | ); |
| 1654 | break; |
| 1655 | case 2: |
| 1656 | ddr->ddr_sdram_mode_5 = (0 |
| 1657 | | ((esdmode & 0xFFFF) << 16) |
| 1658 | | ((sdmode & 0xFFFF) << 0) |
| 1659 | ); |
| 1660 | break; |
| 1661 | case 3: |
| 1662 | ddr->ddr_sdram_mode_7 = (0 |
| 1663 | | ((esdmode & 0xFFFF) << 16) |
| 1664 | | ((sdmode & 0xFFFF) << 0) |
| 1665 | ); |
| 1666 | break; |
| 1667 | } |
| 1668 | } |
| 1669 | debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n", |
| 1670 | ddr->ddr_sdram_mode_3); |
| 1671 | debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n", |
| 1672 | ddr->ddr_sdram_mode_5); |
| 1673 | debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n", |
| 1674 | ddr->ddr_sdram_mode_5); |
| 1675 | } |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1676 | } |
| 1677 | |
York Sun | f062659 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 1678 | #else /* !CONFIG_SYS_FSL_DDR3 */ |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1679 | |
| 1680 | /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */ |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 1681 | static void set_ddr_sdram_mode(const unsigned int ctrl_num, |
| 1682 | fsl_ddr_cfg_regs_t *ddr, |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1683 | const memctl_options_t *popts, |
| 1684 | const common_timing_params_t *common_dimm, |
| 1685 | unsigned int cas_latency, |
York Sun | ba0c2eb | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 1686 | unsigned int additive_latency, |
| 1687 | const unsigned int unq_mrs_en) |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1688 | { |
| 1689 | unsigned short esdmode; /* Extended SDRAM mode */ |
| 1690 | unsigned short sdmode; /* SDRAM mode */ |
| 1691 | |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1692 | /* |
| 1693 | * FIXME: This ought to be pre-calculated in a |
| 1694 | * technology-specific routine, |
| 1695 | * e.g. compute_DDR2_mode_register(), and then the |
| 1696 | * sdmode and esdmode passed in as part of common_dimm. |
| 1697 | */ |
| 1698 | |
| 1699 | /* Extended Mode Register */ |
| 1700 | unsigned int mrs = 0; /* Mode Register Set */ |
| 1701 | unsigned int outputs = 0; /* 0=Enabled, 1=Disabled */ |
| 1702 | unsigned int rdqs_en = 0; /* RDQS Enable: 0=no, 1=yes */ |
| 1703 | unsigned int dqs_en = 0; /* DQS# Enable: 0=enable, 1=disable */ |
| 1704 | unsigned int ocd = 0; /* 0x0=OCD not supported, |
| 1705 | 0x7=OCD default state */ |
| 1706 | unsigned int rtt; |
| 1707 | unsigned int al; /* Posted CAS# additive latency (AL) */ |
| 1708 | unsigned int ods = 0; /* Output Drive Strength: |
| 1709 | 0 = Full strength (18ohm) |
| 1710 | 1 = Reduced strength (4ohm) */ |
| 1711 | unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal), |
| 1712 | 1=Disable (Test/Debug) */ |
| 1713 | |
| 1714 | /* Mode Register (MR) */ |
| 1715 | unsigned int mr; /* Mode Register Definition */ |
| 1716 | unsigned int pd; /* Power-Down Mode */ |
| 1717 | unsigned int wr; /* Write Recovery */ |
| 1718 | unsigned int dll_res; /* DLL Reset */ |
| 1719 | unsigned int mode; /* Normal=0 or Test=1 */ |
Kumar Gala | 35ad58d | 2008-09-05 14:40:29 -0500 | [diff] [blame] | 1720 | unsigned int caslat = 0;/* CAS# latency */ |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1721 | /* BT: Burst Type (0=Sequential, 1=Interleaved) */ |
| 1722 | unsigned int bt; |
| 1723 | unsigned int bl; /* BL: Burst Length */ |
| 1724 | |
Priyanka Jain | 4a71741 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 1725 | dqs_en = !popts->dqs_config; |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1726 | rtt = fsl_ddr_get_rtt(); |
| 1727 | |
| 1728 | al = additive_latency; |
| 1729 | |
| 1730 | esdmode = (0 |
| 1731 | | ((mrs & 0x3) << 14) |
| 1732 | | ((outputs & 0x1) << 12) |
| 1733 | | ((rdqs_en & 0x1) << 11) |
| 1734 | | ((dqs_en & 0x1) << 10) |
| 1735 | | ((ocd & 0x7) << 7) |
| 1736 | | ((rtt & 0x2) << 5) /* rtt field is split */ |
| 1737 | | ((al & 0x7) << 3) |
| 1738 | | ((rtt & 0x1) << 2) /* rtt field is split */ |
| 1739 | | ((ods & 0x1) << 1) |
| 1740 | | ((dll_en & 0x1) << 0) |
| 1741 | ); |
| 1742 | |
| 1743 | mr = 0; /* FIXME: CHECKME */ |
| 1744 | |
| 1745 | /* |
| 1746 | * 0 = Fast Exit (Normal) |
| 1747 | * 1 = Slow Exit (Low Power) |
| 1748 | */ |
| 1749 | pd = 0; |
| 1750 | |
York Sun | f062659 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 1751 | #if defined(CONFIG_SYS_FSL_DDR1) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1752 | wr = 0; /* Historical */ |
York Sun | f062659 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 1753 | #elif defined(CONFIG_SYS_FSL_DDR2) |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 1754 | wr = picos_to_mclk(ctrl_num, common_dimm->twr_ps); |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1755 | #endif |
| 1756 | dll_res = 0; |
| 1757 | mode = 0; |
| 1758 | |
York Sun | f062659 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 1759 | #if defined(CONFIG_SYS_FSL_DDR1) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1760 | if (1 <= cas_latency && cas_latency <= 4) { |
| 1761 | unsigned char mode_caslat_table[4] = { |
| 1762 | 0x5, /* 1.5 clocks */ |
| 1763 | 0x2, /* 2.0 clocks */ |
| 1764 | 0x6, /* 2.5 clocks */ |
| 1765 | 0x3 /* 3.0 clocks */ |
| 1766 | }; |
Kumar Gala | 35ad58d | 2008-09-05 14:40:29 -0500 | [diff] [blame] | 1767 | caslat = mode_caslat_table[cas_latency - 1]; |
| 1768 | } else { |
| 1769 | printf("Warning: unknown cas_latency %d\n", cas_latency); |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1770 | } |
York Sun | f062659 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 1771 | #elif defined(CONFIG_SYS_FSL_DDR2) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1772 | caslat = cas_latency; |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1773 | #endif |
| 1774 | bt = 0; |
| 1775 | |
| 1776 | switch (popts->burst_length) { |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1777 | case DDR_BL4: |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1778 | bl = 2; |
| 1779 | break; |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1780 | case DDR_BL8: |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1781 | bl = 3; |
| 1782 | break; |
| 1783 | default: |
| 1784 | printf("Error: invalid burst length of %u specified. " |
| 1785 | " Defaulting to 4 beats.\n", |
| 1786 | popts->burst_length); |
| 1787 | bl = 2; |
| 1788 | break; |
| 1789 | } |
| 1790 | |
| 1791 | sdmode = (0 |
| 1792 | | ((mr & 0x3) << 14) |
| 1793 | | ((pd & 0x1) << 12) |
| 1794 | | ((wr & 0x7) << 9) |
| 1795 | | ((dll_res & 0x1) << 8) |
| 1796 | | ((mode & 0x1) << 7) |
| 1797 | | ((caslat & 0x7) << 4) |
| 1798 | | ((bt & 0x1) << 3) |
| 1799 | | ((bl & 0x7) << 0) |
| 1800 | ); |
| 1801 | |
| 1802 | ddr->ddr_sdram_mode = (0 |
| 1803 | | ((esdmode & 0xFFFF) << 16) |
| 1804 | | ((sdmode & 0xFFFF) << 0) |
| 1805 | ); |
Haiying Wang | d90e040 | 2008-10-03 12:37:26 -0400 | [diff] [blame] | 1806 | debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode); |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1807 | } |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1808 | #endif |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1809 | |
| 1810 | /* DDR SDRAM Data Initialization (DDR_DATA_INIT) */ |
| 1811 | static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr) |
| 1812 | { |
| 1813 | unsigned int init_value; /* Initialization value */ |
| 1814 | |
Anatolij Gustschin | 021b7ae | 2013-01-21 23:50:27 +0000 | [diff] [blame] | 1815 | #ifdef CONFIG_MEM_INIT_VALUE |
| 1816 | init_value = CONFIG_MEM_INIT_VALUE; |
| 1817 | #else |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1818 | init_value = 0xDEADBEEF; |
Anatolij Gustschin | 021b7ae | 2013-01-21 23:50:27 +0000 | [diff] [blame] | 1819 | #endif |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1820 | ddr->ddr_data_init = init_value; |
| 1821 | } |
| 1822 | |
| 1823 | /* |
| 1824 | * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL) |
| 1825 | * The old controller on the 8540/60 doesn't have this register. |
| 1826 | * Hope it's OK to set it (to 0) anyway. |
| 1827 | */ |
| 1828 | static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr, |
| 1829 | const memctl_options_t *popts) |
| 1830 | { |
| 1831 | unsigned int clk_adjust; /* Clock adjust */ |
Curt Brune | 6aff153 | 2015-02-13 10:57:11 -0800 | [diff] [blame] | 1832 | unsigned int ss_en = 0; /* Source synchronous enable */ |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1833 | |
Curt Brune | 6aff153 | 2015-02-13 10:57:11 -0800 | [diff] [blame] | 1834 | #if defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) |
| 1835 | /* Per FSL Application Note: AN2805 */ |
| 1836 | ss_en = 1; |
| 1837 | #endif |
Shengzhou Liu | 3b33dd2 | 2016-05-04 10:20:21 +0800 | [diff] [blame^] | 1838 | if (fsl_ddr_get_version(0) >= 0x40701) { |
| 1839 | /* clk_adjust in 5-bits on T-series and LS-series */ |
| 1840 | clk_adjust = (popts->clk_adjust & 0x1F) << 22; |
| 1841 | } else { |
| 1842 | /* clk_adjust in 4-bits on earlier MPC85xx and P-series */ |
| 1843 | clk_adjust = (popts->clk_adjust & 0xF) << 23; |
| 1844 | } |
| 1845 | |
Curt Brune | 6aff153 | 2015-02-13 10:57:11 -0800 | [diff] [blame] | 1846 | ddr->ddr_sdram_clk_cntl = (0 |
| 1847 | | ((ss_en & 0x1) << 31) |
Shengzhou Liu | 3b33dd2 | 2016-05-04 10:20:21 +0800 | [diff] [blame^] | 1848 | | clk_adjust |
Curt Brune | 6aff153 | 2015-02-13 10:57:11 -0800 | [diff] [blame] | 1849 | ); |
york | de87932 | 2010-07-02 22:25:55 +0000 | [diff] [blame] | 1850 | debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl); |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1851 | } |
| 1852 | |
| 1853 | /* DDR Initialization Address (DDR_INIT_ADDR) */ |
| 1854 | static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr) |
| 1855 | { |
| 1856 | unsigned int init_addr = 0; /* Initialization address */ |
| 1857 | |
| 1858 | ddr->ddr_init_addr = init_addr; |
| 1859 | } |
| 1860 | |
| 1861 | /* DDR Initialization Address (DDR_INIT_EXT_ADDR) */ |
| 1862 | static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr) |
| 1863 | { |
| 1864 | unsigned int uia = 0; /* Use initialization address */ |
| 1865 | unsigned int init_ext_addr = 0; /* Initialization address */ |
| 1866 | |
| 1867 | ddr->ddr_init_ext_addr = (0 |
| 1868 | | ((uia & 0x1) << 31) |
| 1869 | | (init_ext_addr & 0xF) |
| 1870 | ); |
| 1871 | } |
| 1872 | |
| 1873 | /* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */ |
Dave Liu | 3525e1a | 2010-03-05 12:22:00 +0800 | [diff] [blame] | 1874 | static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr, |
| 1875 | const memctl_options_t *popts) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1876 | { |
| 1877 | unsigned int rwt = 0; /* Read-to-write turnaround for same CS */ |
| 1878 | unsigned int wrt = 0; /* Write-to-read turnaround for same CS */ |
| 1879 | unsigned int rrt = 0; /* Read-to-read turnaround for same CS */ |
| 1880 | unsigned int wwt = 0; /* Write-to-write turnaround for same CS */ |
York Sun | 77594b3 | 2015-11-04 10:03:21 -0800 | [diff] [blame] | 1881 | unsigned int trwt_mclk = 0; /* ext_rwt */ |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1882 | unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */ |
| 1883 | |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 1884 | #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) |
Dave Liu | 3525e1a | 2010-03-05 12:22:00 +0800 | [diff] [blame] | 1885 | if (popts->burst_length == DDR_BL8) { |
| 1886 | /* We set BL/2 for fixed BL8 */ |
| 1887 | rrt = 0; /* BL/2 clocks */ |
| 1888 | wwt = 0; /* BL/2 clocks */ |
| 1889 | } else { |
| 1890 | /* We need to set BL/2 + 2 to BC4 and OTF */ |
| 1891 | rrt = 2; /* BL/2 + 2 clocks */ |
| 1892 | wwt = 2; /* BL/2 + 2 clocks */ |
| 1893 | } |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 1894 | #endif |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 1895 | #ifdef CONFIG_SYS_FSL_DDR4 |
| 1896 | dll_lock = 2; /* tDLLK = 1024 clocks */ |
| 1897 | #elif defined(CONFIG_SYS_FSL_DDR3) |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1898 | dll_lock = 1; /* tDLLK = 512 clocks from spec */ |
| 1899 | #endif |
York Sun | 77594b3 | 2015-11-04 10:03:21 -0800 | [diff] [blame] | 1900 | |
| 1901 | if (popts->trwt_override) |
| 1902 | trwt_mclk = popts->trwt; |
| 1903 | |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1904 | ddr->timing_cfg_4 = (0 |
| 1905 | | ((rwt & 0xf) << 28) |
| 1906 | | ((wrt & 0xf) << 24) |
| 1907 | | ((rrt & 0xf) << 20) |
| 1908 | | ((wwt & 0xf) << 16) |
York Sun | 77594b3 | 2015-11-04 10:03:21 -0800 | [diff] [blame] | 1909 | | ((trwt_mclk & 0xc) << 12) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1910 | | (dll_lock & 0x3) |
| 1911 | ); |
Haiying Wang | d90e040 | 2008-10-03 12:37:26 -0400 | [diff] [blame] | 1912 | debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4); |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1913 | } |
| 1914 | |
| 1915 | /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */ |
York Sun | ba0c2eb | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 1916 | static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1917 | { |
| 1918 | unsigned int rodt_on = 0; /* Read to ODT on */ |
| 1919 | unsigned int rodt_off = 0; /* Read to ODT off */ |
| 1920 | unsigned int wodt_on = 0; /* Write to ODT on */ |
| 1921 | unsigned int wodt_off = 0; /* Write to ODT off */ |
| 1922 | |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 1923 | #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) |
| 1924 | unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) + |
| 1925 | ((ddr->timing_cfg_2 & 0x00040000) >> 14); |
York Sun | ba0c2eb | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 1926 | /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */ |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 1927 | if (cas_latency >= wr_lat) |
| 1928 | rodt_on = cas_latency - wr_lat + 1; |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1929 | rodt_off = 4; /* 4 clocks */ |
york | 1714e49 | 2010-07-02 22:25:56 +0000 | [diff] [blame] | 1930 | wodt_on = 1; /* 1 clocks */ |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1931 | wodt_off = 4; /* 4 clocks */ |
| 1932 | #endif |
| 1933 | |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1934 | ddr->timing_cfg_5 = (0 |
Dave Liu | 4758d53 | 2008-11-21 16:31:29 +0800 | [diff] [blame] | 1935 | | ((rodt_on & 0x1f) << 24) |
| 1936 | | ((rodt_off & 0x7) << 20) |
| 1937 | | ((wodt_on & 0x1f) << 12) |
| 1938 | | ((wodt_off & 0x7) << 8) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1939 | ); |
Haiying Wang | d90e040 | 2008-10-03 12:37:26 -0400 | [diff] [blame] | 1940 | debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5); |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1941 | } |
| 1942 | |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 1943 | #ifdef CONFIG_SYS_FSL_DDR4 |
| 1944 | static void set_timing_cfg_6(fsl_ddr_cfg_regs_t *ddr) |
| 1945 | { |
| 1946 | unsigned int hs_caslat = 0; |
| 1947 | unsigned int hs_wrlat = 0; |
| 1948 | unsigned int hs_wrrec = 0; |
| 1949 | unsigned int hs_clkadj = 0; |
| 1950 | unsigned int hs_wrlvl_start = 0; |
| 1951 | |
| 1952 | ddr->timing_cfg_6 = (0 |
| 1953 | | ((hs_caslat & 0x1f) << 24) |
| 1954 | | ((hs_wrlat & 0x1f) << 19) |
| 1955 | | ((hs_wrrec & 0x1f) << 12) |
| 1956 | | ((hs_clkadj & 0x1f) << 6) |
| 1957 | | ((hs_wrlvl_start & 0x1f) << 0) |
| 1958 | ); |
| 1959 | debug("FSLDDR: timing_cfg_6 = 0x%08x\n", ddr->timing_cfg_6); |
| 1960 | } |
| 1961 | |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 1962 | static void set_timing_cfg_7(const unsigned int ctrl_num, |
| 1963 | fsl_ddr_cfg_regs_t *ddr, |
| 1964 | const common_timing_params_t *common_dimm) |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 1965 | { |
| 1966 | unsigned int txpr, tcksre, tcksrx; |
Shengzhou Liu | 5219944 | 2016-03-10 17:36:56 +0800 | [diff] [blame] | 1967 | unsigned int cke_rst, cksre, cksrx, par_lat = 0, cs_to_cmd; |
| 1968 | const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 1969 | |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 1970 | txpr = max(5U, picos_to_mclk(ctrl_num, common_dimm->trfc1_ps + 10000)); |
| 1971 | tcksre = max(5U, picos_to_mclk(ctrl_num, 10000)); |
| 1972 | tcksrx = max(5U, picos_to_mclk(ctrl_num, 10000)); |
Shengzhou Liu | 5219944 | 2016-03-10 17:36:56 +0800 | [diff] [blame] | 1973 | |
| 1974 | if (ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) { |
| 1975 | if (mclk_ps >= 935) { |
| 1976 | /* parity latency 4 clocks in case of 1600/1866/2133 */ |
| 1977 | par_lat = 4; |
| 1978 | } else if (mclk_ps >= 833) { |
| 1979 | /* parity latency 5 clocks for DDR4-2400 */ |
| 1980 | par_lat = 5; |
| 1981 | } else { |
| 1982 | printf("parity: mclk_ps = %d not supported\n", mclk_ps); |
| 1983 | } |
| 1984 | } |
| 1985 | |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 1986 | cs_to_cmd = 0; |
| 1987 | |
| 1988 | if (txpr <= 200) |
| 1989 | cke_rst = 0; |
| 1990 | else if (txpr <= 256) |
| 1991 | cke_rst = 1; |
| 1992 | else if (txpr <= 512) |
| 1993 | cke_rst = 2; |
| 1994 | else |
| 1995 | cke_rst = 3; |
| 1996 | |
| 1997 | if (tcksre <= 19) |
| 1998 | cksre = tcksre - 5; |
| 1999 | else |
| 2000 | cksre = 15; |
| 2001 | |
| 2002 | if (tcksrx <= 19) |
| 2003 | cksrx = tcksrx - 5; |
| 2004 | else |
| 2005 | cksrx = 15; |
| 2006 | |
| 2007 | ddr->timing_cfg_7 = (0 |
| 2008 | | ((cke_rst & 0x3) << 28) |
| 2009 | | ((cksre & 0xf) << 24) |
| 2010 | | ((cksrx & 0xf) << 20) |
| 2011 | | ((par_lat & 0xf) << 16) |
| 2012 | | ((cs_to_cmd & 0xf) << 4) |
| 2013 | ); |
| 2014 | debug("FSLDDR: timing_cfg_7 = 0x%08x\n", ddr->timing_cfg_7); |
| 2015 | } |
| 2016 | |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 2017 | static void set_timing_cfg_8(const unsigned int ctrl_num, |
| 2018 | fsl_ddr_cfg_regs_t *ddr, |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 2019 | const memctl_options_t *popts, |
| 2020 | const common_timing_params_t *common_dimm, |
| 2021 | unsigned int cas_latency) |
| 2022 | { |
| 2023 | unsigned int rwt_bg, wrt_bg, rrt_bg, wwt_bg; |
| 2024 | unsigned int acttoact_bg, wrtord_bg, pre_all_rec; |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 2025 | unsigned int tccdl = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps); |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 2026 | unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) + |
| 2027 | ((ddr->timing_cfg_2 & 0x00040000) >> 14); |
| 2028 | |
| 2029 | rwt_bg = cas_latency + 2 + 4 - wr_lat; |
| 2030 | if (rwt_bg < tccdl) |
| 2031 | rwt_bg = tccdl - rwt_bg; |
| 2032 | else |
| 2033 | rwt_bg = 0; |
| 2034 | |
| 2035 | wrt_bg = wr_lat + 4 + 1 - cas_latency; |
| 2036 | if (wrt_bg < tccdl) |
| 2037 | wrt_bg = tccdl - wrt_bg; |
| 2038 | else |
| 2039 | wrt_bg = 0; |
| 2040 | |
| 2041 | if (popts->burst_length == DDR_BL8) { |
| 2042 | rrt_bg = tccdl - 4; |
| 2043 | wwt_bg = tccdl - 4; |
| 2044 | } else { |
| 2045 | rrt_bg = tccdl - 2; |
York Sun | 5e52647 | 2015-01-06 13:18:52 -0800 | [diff] [blame] | 2046 | wwt_bg = tccdl - 2; |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 2047 | } |
| 2048 | |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 2049 | acttoact_bg = picos_to_mclk(ctrl_num, common_dimm->trrdl_ps); |
| 2050 | wrtord_bg = max(4U, picos_to_mclk(ctrl_num, 7500)); |
York Sun | f0e4f6d | 2014-06-26 11:14:44 -0700 | [diff] [blame] | 2051 | if (popts->otf_burst_chop_en) |
| 2052 | wrtord_bg += 2; |
| 2053 | |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 2054 | pre_all_rec = 0; |
| 2055 | |
| 2056 | ddr->timing_cfg_8 = (0 |
| 2057 | | ((rwt_bg & 0xf) << 28) |
| 2058 | | ((wrt_bg & 0xf) << 24) |
| 2059 | | ((rrt_bg & 0xf) << 20) |
| 2060 | | ((wwt_bg & 0xf) << 16) |
| 2061 | | ((acttoact_bg & 0xf) << 12) |
| 2062 | | ((wrtord_bg & 0xf) << 8) |
| 2063 | | ((pre_all_rec & 0x1f) << 0) |
| 2064 | ); |
| 2065 | |
| 2066 | debug("FSLDDR: timing_cfg_8 = 0x%08x\n", ddr->timing_cfg_8); |
| 2067 | } |
| 2068 | |
| 2069 | static void set_timing_cfg_9(fsl_ddr_cfg_regs_t *ddr) |
| 2070 | { |
| 2071 | ddr->timing_cfg_9 = 0; |
| 2072 | debug("FSLDDR: timing_cfg_9 = 0x%08x\n", ddr->timing_cfg_9); |
| 2073 | } |
| 2074 | |
York Sun | a8b3d52 | 2014-09-11 13:32:06 -0700 | [diff] [blame] | 2075 | /* This function needs to be called after set_ddr_sdram_cfg() is called */ |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 2076 | static void set_ddr_dq_mapping(fsl_ddr_cfg_regs_t *ddr, |
| 2077 | const dimm_params_t *dimm_params) |
| 2078 | { |
York Sun | a8b3d52 | 2014-09-11 13:32:06 -0700 | [diff] [blame] | 2079 | unsigned int acc_ecc_en = (ddr->ddr_sdram_cfg >> 2) & 0x1; |
York Sun | fc63b28 | 2015-03-19 09:30:27 -0700 | [diff] [blame] | 2080 | int i; |
York Sun | a8b3d52 | 2014-09-11 13:32:06 -0700 | [diff] [blame] | 2081 | |
York Sun | fc63b28 | 2015-03-19 09:30:27 -0700 | [diff] [blame] | 2082 | for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { |
| 2083 | if (dimm_params[i].n_ranks) |
| 2084 | break; |
| 2085 | } |
| 2086 | if (i >= CONFIG_DIMM_SLOTS_PER_CTLR) { |
| 2087 | puts("DDR error: no DIMM found!\n"); |
| 2088 | return; |
| 2089 | } |
| 2090 | |
| 2091 | ddr->dq_map_0 = ((dimm_params[i].dq_mapping[0] & 0x3F) << 26) | |
| 2092 | ((dimm_params[i].dq_mapping[1] & 0x3F) << 20) | |
| 2093 | ((dimm_params[i].dq_mapping[2] & 0x3F) << 14) | |
| 2094 | ((dimm_params[i].dq_mapping[3] & 0x3F) << 8) | |
| 2095 | ((dimm_params[i].dq_mapping[4] & 0x3F) << 2); |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 2096 | |
York Sun | fc63b28 | 2015-03-19 09:30:27 -0700 | [diff] [blame] | 2097 | ddr->dq_map_1 = ((dimm_params[i].dq_mapping[5] & 0x3F) << 26) | |
| 2098 | ((dimm_params[i].dq_mapping[6] & 0x3F) << 20) | |
| 2099 | ((dimm_params[i].dq_mapping[7] & 0x3F) << 14) | |
| 2100 | ((dimm_params[i].dq_mapping[10] & 0x3F) << 8) | |
| 2101 | ((dimm_params[i].dq_mapping[11] & 0x3F) << 2); |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 2102 | |
York Sun | fc63b28 | 2015-03-19 09:30:27 -0700 | [diff] [blame] | 2103 | ddr->dq_map_2 = ((dimm_params[i].dq_mapping[12] & 0x3F) << 26) | |
| 2104 | ((dimm_params[i].dq_mapping[13] & 0x3F) << 20) | |
| 2105 | ((dimm_params[i].dq_mapping[14] & 0x3F) << 14) | |
| 2106 | ((dimm_params[i].dq_mapping[15] & 0x3F) << 8) | |
| 2107 | ((dimm_params[i].dq_mapping[16] & 0x3F) << 2); |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 2108 | |
York Sun | a8b3d52 | 2014-09-11 13:32:06 -0700 | [diff] [blame] | 2109 | /* dq_map for ECC[4:7] is set to 0 if accumulated ECC is enabled */ |
York Sun | fc63b28 | 2015-03-19 09:30:27 -0700 | [diff] [blame] | 2110 | ddr->dq_map_3 = ((dimm_params[i].dq_mapping[17] & 0x3F) << 26) | |
| 2111 | ((dimm_params[i].dq_mapping[8] & 0x3F) << 20) | |
York Sun | a8b3d52 | 2014-09-11 13:32:06 -0700 | [diff] [blame] | 2112 | (acc_ecc_en ? 0 : |
York Sun | fc63b28 | 2015-03-19 09:30:27 -0700 | [diff] [blame] | 2113 | (dimm_params[i].dq_mapping[9] & 0x3F) << 14) | |
| 2114 | dimm_params[i].dq_mapping_ors; |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 2115 | |
| 2116 | debug("FSLDDR: dq_map_0 = 0x%08x\n", ddr->dq_map_0); |
| 2117 | debug("FSLDDR: dq_map_1 = 0x%08x\n", ddr->dq_map_1); |
| 2118 | debug("FSLDDR: dq_map_2 = 0x%08x\n", ddr->dq_map_2); |
| 2119 | debug("FSLDDR: dq_map_3 = 0x%08x\n", ddr->dq_map_3); |
| 2120 | } |
| 2121 | static void set_ddr_sdram_cfg_3(fsl_ddr_cfg_regs_t *ddr, |
| 2122 | const memctl_options_t *popts) |
| 2123 | { |
| 2124 | int rd_pre; |
| 2125 | |
| 2126 | rd_pre = popts->quad_rank_present ? 1 : 0; |
| 2127 | |
| 2128 | ddr->ddr_sdram_cfg_3 = (rd_pre & 0x1) << 16; |
| 2129 | |
| 2130 | debug("FSLDDR: ddr_sdram_cfg_3 = 0x%08x\n", ddr->ddr_sdram_cfg_3); |
| 2131 | } |
| 2132 | #endif /* CONFIG_SYS_FSL_DDR4 */ |
| 2133 | |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 2134 | /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */ |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 2135 | static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 2136 | { |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 2137 | unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */ |
| 2138 | /* Normal Operation Full Calibration Time (tZQoper) */ |
| 2139 | unsigned int zqoper = 0; |
| 2140 | /* Normal Operation Short Calibration Time (tZQCS) */ |
| 2141 | unsigned int zqcs = 0; |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 2142 | #ifdef CONFIG_SYS_FSL_DDR4 |
| 2143 | unsigned int zqcs_init; |
| 2144 | #endif |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 2145 | |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 2146 | if (zq_en) { |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 2147 | #ifdef CONFIG_SYS_FSL_DDR4 |
| 2148 | zqinit = 10; /* 1024 clocks */ |
| 2149 | zqoper = 9; /* 512 clocks */ |
| 2150 | zqcs = 7; /* 128 clocks */ |
| 2151 | zqcs_init = 5; /* 1024 refresh sequences */ |
| 2152 | #else |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 2153 | zqinit = 9; /* 512 clocks */ |
| 2154 | zqoper = 8; /* 256 clocks */ |
| 2155 | zqcs = 6; /* 64 clocks */ |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 2156 | #endif |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 2157 | } |
| 2158 | |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 2159 | ddr->ddr_zq_cntl = (0 |
| 2160 | | ((zq_en & 0x1) << 31) |
| 2161 | | ((zqinit & 0xF) << 24) |
| 2162 | | ((zqoper & 0xF) << 16) |
| 2163 | | ((zqcs & 0xF) << 8) |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 2164 | #ifdef CONFIG_SYS_FSL_DDR4 |
| 2165 | | ((zqcs_init & 0xF) << 0) |
| 2166 | #endif |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 2167 | ); |
York Sun | ba0c2eb | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 2168 | debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl); |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 2169 | } |
| 2170 | |
| 2171 | /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */ |
Dave Liu | 64ee7df | 2009-12-16 10:24:37 -0600 | [diff] [blame] | 2172 | static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en, |
| 2173 | const memctl_options_t *popts) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 2174 | { |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 2175 | /* |
| 2176 | * First DQS pulse rising edge after margining mode |
| 2177 | * is programmed (tWL_MRD) |
| 2178 | */ |
| 2179 | unsigned int wrlvl_mrd = 0; |
| 2180 | /* ODT delay after margining mode is programmed (tWL_ODTEN) */ |
| 2181 | unsigned int wrlvl_odten = 0; |
| 2182 | /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */ |
| 2183 | unsigned int wrlvl_dqsen = 0; |
| 2184 | /* WRLVL_SMPL: Write leveling sample time */ |
| 2185 | unsigned int wrlvl_smpl = 0; |
| 2186 | /* WRLVL_WLR: Write leveling repeition time */ |
| 2187 | unsigned int wrlvl_wlr = 0; |
| 2188 | /* WRLVL_START: Write leveling start time */ |
| 2189 | unsigned int wrlvl_start = 0; |
| 2190 | |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 2191 | /* suggest enable write leveling for DDR3 due to fly-by topology */ |
| 2192 | if (wrlvl_en) { |
| 2193 | /* tWL_MRD min = 40 nCK, we set it 64 */ |
| 2194 | wrlvl_mrd = 0x6; |
| 2195 | /* tWL_ODTEN 128 */ |
| 2196 | wrlvl_odten = 0x7; |
| 2197 | /* tWL_DQSEN min = 25 nCK, we set it 32 */ |
| 2198 | wrlvl_dqsen = 0x5; |
| 2199 | /* |
Dave Liu | 64ee7df | 2009-12-16 10:24:37 -0600 | [diff] [blame] | 2200 | * Write leveling sample time at least need 6 clocks |
| 2201 | * higher than tWLO to allow enough time for progagation |
| 2202 | * delay and sampling the prime data bits. |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 2203 | */ |
| 2204 | wrlvl_smpl = 0xf; |
| 2205 | /* |
| 2206 | * Write leveling repetition time |
| 2207 | * at least tWLO + 6 clocks clocks |
york | 1714e49 | 2010-07-02 22:25:56 +0000 | [diff] [blame] | 2208 | * we set it 64 |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 2209 | */ |
york | 1714e49 | 2010-07-02 22:25:56 +0000 | [diff] [blame] | 2210 | wrlvl_wlr = 0x6; |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 2211 | /* |
| 2212 | * Write leveling start time |
| 2213 | * The value use for the DQS_ADJUST for the first sample |
York Sun | ba0c2eb | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 2214 | * when write leveling is enabled. It probably needs to be |
| 2215 | * overriden per platform. |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 2216 | */ |
| 2217 | wrlvl_start = 0x8; |
Dave Liu | 64ee7df | 2009-12-16 10:24:37 -0600 | [diff] [blame] | 2218 | /* |
| 2219 | * Override the write leveling sample and start time |
| 2220 | * according to specific board |
| 2221 | */ |
| 2222 | if (popts->wrlvl_override) { |
| 2223 | wrlvl_smpl = popts->wrlvl_sample; |
| 2224 | wrlvl_start = popts->wrlvl_start; |
| 2225 | } |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 2226 | } |
| 2227 | |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 2228 | ddr->ddr_wrlvl_cntl = (0 |
| 2229 | | ((wrlvl_en & 0x1) << 31) |
| 2230 | | ((wrlvl_mrd & 0x7) << 24) |
| 2231 | | ((wrlvl_odten & 0x7) << 20) |
| 2232 | | ((wrlvl_dqsen & 0x7) << 16) |
| 2233 | | ((wrlvl_smpl & 0xf) << 12) |
| 2234 | | ((wrlvl_wlr & 0x7) << 8) |
Dave Liu | 4758d53 | 2008-11-21 16:31:29 +0800 | [diff] [blame] | 2235 | | ((wrlvl_start & 0x1F) << 0) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 2236 | ); |
York Sun | ba0c2eb | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 2237 | debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl); |
York Sun | 7d69ea3 | 2012-10-08 07:44:22 +0000 | [diff] [blame] | 2238 | ddr->ddr_wrlvl_cntl_2 = popts->wrlvl_ctl_2; |
| 2239 | debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2); |
| 2240 | ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3; |
| 2241 | debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3); |
| 2242 | |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 2243 | } |
| 2244 | |
| 2245 | /* DDR Self Refresh Counter (DDR_SR_CNTR) */ |
Dave Liu | 2aad0ae | 2008-11-21 16:31:35 +0800 | [diff] [blame] | 2246 | static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 2247 | { |
Dave Liu | 2aad0ae | 2008-11-21 16:31:35 +0800 | [diff] [blame] | 2248 | /* Self Refresh Idle Threshold */ |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 2249 | ddr->ddr_sr_cntr = (sr_it & 0xF) << 16; |
| 2250 | } |
| 2251 | |
york | 4260372 | 2010-07-02 22:25:54 +0000 | [diff] [blame] | 2252 | static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) |
| 2253 | { |
| 2254 | if (popts->addr_hash) { |
| 2255 | ddr->ddr_eor = 0x40000000; /* address hash enable */ |
Kumar Gala | 4513d76 | 2011-03-18 11:53:06 -0500 | [diff] [blame] | 2256 | puts("Address hashing enabled.\n"); |
york | 4260372 | 2010-07-02 22:25:54 +0000 | [diff] [blame] | 2257 | } |
| 2258 | } |
| 2259 | |
York Sun | ba0c2eb | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 2260 | static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) |
| 2261 | { |
| 2262 | ddr->ddr_cdr1 = popts->ddr_cdr1; |
| 2263 | debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1); |
| 2264 | } |
| 2265 | |
York Sun | 7d69ea3 | 2012-10-08 07:44:22 +0000 | [diff] [blame] | 2266 | static void set_ddr_cdr2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) |
| 2267 | { |
| 2268 | ddr->ddr_cdr2 = popts->ddr_cdr2; |
| 2269 | debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2); |
| 2270 | } |
| 2271 | |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 2272 | unsigned int |
| 2273 | check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr) |
| 2274 | { |
| 2275 | unsigned int res = 0; |
| 2276 | |
| 2277 | /* |
| 2278 | * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are |
| 2279 | * not set at the same time. |
| 2280 | */ |
| 2281 | if (ddr->ddr_sdram_cfg & 0x10000000 |
| 2282 | && ddr->ddr_sdram_cfg & 0x00008000) { |
| 2283 | printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] " |
| 2284 | " should not be set at the same time.\n"); |
| 2285 | res++; |
| 2286 | } |
| 2287 | |
| 2288 | return res; |
| 2289 | } |
| 2290 | |
| 2291 | unsigned int |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 2292 | compute_fsl_memctl_config_regs(const unsigned int ctrl_num, |
| 2293 | const memctl_options_t *popts, |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 2294 | fsl_ddr_cfg_regs_t *ddr, |
| 2295 | const common_timing_params_t *common_dimm, |
| 2296 | const dimm_params_t *dimm_params, |
Haiying Wang | 80ad401 | 2010-12-01 10:35:31 -0500 | [diff] [blame] | 2297 | unsigned int dbw_cap_adj, |
| 2298 | unsigned int size_only) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 2299 | { |
| 2300 | unsigned int i; |
| 2301 | unsigned int cas_latency; |
| 2302 | unsigned int additive_latency; |
Dave Liu | 2aad0ae | 2008-11-21 16:31:35 +0800 | [diff] [blame] | 2303 | unsigned int sr_it; |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 2304 | unsigned int zq_en; |
| 2305 | unsigned int wrlvl_en; |
York Sun | ba0c2eb | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 2306 | unsigned int ip_rev = 0; |
| 2307 | unsigned int unq_mrs_en = 0; |
York Sun | 2927c5e | 2010-10-18 13:46:50 -0700 | [diff] [blame] | 2308 | int cs_en = 1; |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 2309 | |
| 2310 | memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t)); |
| 2311 | |
| 2312 | if (common_dimm == NULL) { |
| 2313 | printf("Error: subset DIMM params struct null pointer\n"); |
| 2314 | return 1; |
| 2315 | } |
| 2316 | |
| 2317 | /* |
| 2318 | * Process overrides first. |
| 2319 | * |
| 2320 | * FIXME: somehow add dereated caslat to this |
| 2321 | */ |
| 2322 | cas_latency = (popts->cas_latency_override) |
| 2323 | ? popts->cas_latency_override_value |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 2324 | : common_dimm->lowest_common_spd_caslat; |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 2325 | |
| 2326 | additive_latency = (popts->additive_latency_override) |
| 2327 | ? popts->additive_latency_override_value |
| 2328 | : common_dimm->additive_latency; |
| 2329 | |
Dave Liu | 2aad0ae | 2008-11-21 16:31:35 +0800 | [diff] [blame] | 2330 | sr_it = (popts->auto_self_refresh_en) |
| 2331 | ? popts->sr_it |
| 2332 | : 0; |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 2333 | /* ZQ calibration */ |
| 2334 | zq_en = (popts->zq_en) ? 1 : 0; |
| 2335 | /* write leveling */ |
| 2336 | wrlvl_en = (popts->wrlvl_en) ? 1 : 0; |
Dave Liu | 2aad0ae | 2008-11-21 16:31:35 +0800 | [diff] [blame] | 2337 | |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 2338 | /* Chip Select Memory Bounds (CSn_BNDS) */ |
| 2339 | for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { |
York Sun | e8dc17b | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 2340 | unsigned long long ea, sa; |
york | 93799ca | 2010-07-02 22:25:52 +0000 | [diff] [blame] | 2341 | unsigned int cs_per_dimm |
| 2342 | = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR; |
| 2343 | unsigned int dimm_number |
| 2344 | = i / cs_per_dimm; |
| 2345 | unsigned long long rank_density |
York Sun | e8dc17b | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 2346 | = dimm_params[dimm_number].rank_density >> dbw_cap_adj; |
Haiying Wang | 272b596 | 2008-10-03 12:36:39 -0400 | [diff] [blame] | 2347 | |
york | 93799ca | 2010-07-02 22:25:52 +0000 | [diff] [blame] | 2348 | if (dimm_params[dimm_number].n_ranks == 0) { |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 2349 | debug("Skipping setup of CS%u " |
york | f4f93c6 | 2010-07-02 22:25:53 +0000 | [diff] [blame] | 2350 | "because n_ranks on DIMM %u is 0\n", i, dimm_number); |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 2351 | continue; |
| 2352 | } |
York Sun | e8dc17b | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 2353 | if (popts->memctl_interleaving) { |
york | 93799ca | 2010-07-02 22:25:52 +0000 | [diff] [blame] | 2354 | switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { |
York Sun | e8dc17b | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 2355 | case FSL_DDR_CS0_CS1_CS2_CS3: |
| 2356 | break; |
york | 93799ca | 2010-07-02 22:25:52 +0000 | [diff] [blame] | 2357 | case FSL_DDR_CS0_CS1: |
| 2358 | case FSL_DDR_CS0_CS1_AND_CS2_CS3: |
York Sun | 2927c5e | 2010-10-18 13:46:50 -0700 | [diff] [blame] | 2359 | if (i > 1) |
| 2360 | cs_en = 0; |
york | 93799ca | 2010-07-02 22:25:52 +0000 | [diff] [blame] | 2361 | break; |
| 2362 | case FSL_DDR_CS2_CS3: |
York Sun | e8dc17b | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 2363 | default: |
York Sun | 2927c5e | 2010-10-18 13:46:50 -0700 | [diff] [blame] | 2364 | if (i > 0) |
| 2365 | cs_en = 0; |
york | 93799ca | 2010-07-02 22:25:52 +0000 | [diff] [blame] | 2366 | break; |
york | 93799ca | 2010-07-02 22:25:52 +0000 | [diff] [blame] | 2367 | } |
York Sun | e8dc17b | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 2368 | sa = common_dimm->base_address; |
York Sun | 98df4d1 | 2012-10-08 07:44:23 +0000 | [diff] [blame] | 2369 | ea = sa + common_dimm->total_mem - 1; |
York Sun | e8dc17b | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 2370 | } else if (!popts->memctl_interleaving) { |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 2371 | /* |
| 2372 | * If memory interleaving between controllers is NOT |
| 2373 | * enabled, the starting address for each memory |
| 2374 | * controller is distinct. However, because rank |
| 2375 | * interleaving is enabled, the starting and ending |
| 2376 | * addresses of the total memory on that memory |
| 2377 | * controller needs to be programmed into its |
| 2378 | * respective CS0_BNDS. |
| 2379 | */ |
Haiying Wang | 272b596 | 2008-10-03 12:36:39 -0400 | [diff] [blame] | 2380 | switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { |
| 2381 | case FSL_DDR_CS0_CS1_CS2_CS3: |
Haiying Wang | 272b596 | 2008-10-03 12:36:39 -0400 | [diff] [blame] | 2382 | sa = common_dimm->base_address; |
York Sun | 98df4d1 | 2012-10-08 07:44:23 +0000 | [diff] [blame] | 2383 | ea = sa + common_dimm->total_mem - 1; |
Haiying Wang | 272b596 | 2008-10-03 12:36:39 -0400 | [diff] [blame] | 2384 | break; |
| 2385 | case FSL_DDR_CS0_CS1_AND_CS2_CS3: |
York Sun | e8dc17b | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 2386 | if ((i >= 2) && (dimm_number == 0)) { |
york | 93799ca | 2010-07-02 22:25:52 +0000 | [diff] [blame] | 2387 | sa = dimm_params[dimm_number].base_address + |
York Sun | e8dc17b | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 2388 | 2 * rank_density; |
| 2389 | ea = sa + 2 * rank_density - 1; |
york | 93799ca | 2010-07-02 22:25:52 +0000 | [diff] [blame] | 2390 | } else { |
| 2391 | sa = dimm_params[dimm_number].base_address; |
York Sun | e8dc17b | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 2392 | ea = sa + 2 * rank_density - 1; |
Haiying Wang | 272b596 | 2008-10-03 12:36:39 -0400 | [diff] [blame] | 2393 | } |
| 2394 | break; |
| 2395 | case FSL_DDR_CS0_CS1: |
york | 93799ca | 2010-07-02 22:25:52 +0000 | [diff] [blame] | 2396 | if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) { |
| 2397 | sa = dimm_params[dimm_number].base_address; |
York Sun | e8dc17b | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 2398 | ea = sa + rank_density - 1; |
| 2399 | if (i != 1) |
| 2400 | sa += (i % cs_per_dimm) * rank_density; |
| 2401 | ea += (i % cs_per_dimm) * rank_density; |
york | 93799ca | 2010-07-02 22:25:52 +0000 | [diff] [blame] | 2402 | } else { |
| 2403 | sa = 0; |
| 2404 | ea = 0; |
| 2405 | } |
| 2406 | if (i == 0) |
York Sun | e8dc17b | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 2407 | ea += rank_density; |
Haiying Wang | 272b596 | 2008-10-03 12:36:39 -0400 | [diff] [blame] | 2408 | break; |
| 2409 | case FSL_DDR_CS2_CS3: |
york | 93799ca | 2010-07-02 22:25:52 +0000 | [diff] [blame] | 2410 | if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) { |
| 2411 | sa = dimm_params[dimm_number].base_address; |
York Sun | e8dc17b | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 2412 | ea = sa + rank_density - 1; |
| 2413 | if (i != 3) |
| 2414 | sa += (i % cs_per_dimm) * rank_density; |
| 2415 | ea += (i % cs_per_dimm) * rank_density; |
york | 93799ca | 2010-07-02 22:25:52 +0000 | [diff] [blame] | 2416 | } else { |
| 2417 | sa = 0; |
| 2418 | ea = 0; |
Haiying Wang | 272b596 | 2008-10-03 12:36:39 -0400 | [diff] [blame] | 2419 | } |
york | 93799ca | 2010-07-02 22:25:52 +0000 | [diff] [blame] | 2420 | if (i == 2) |
| 2421 | ea += (rank_density >> dbw_cap_adj); |
Haiying Wang | 272b596 | 2008-10-03 12:36:39 -0400 | [diff] [blame] | 2422 | break; |
| 2423 | default: /* No bank(chip-select) interleaving */ |
York Sun | e8dc17b | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 2424 | sa = dimm_params[dimm_number].base_address; |
| 2425 | ea = sa + rank_density - 1; |
| 2426 | if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) { |
| 2427 | sa += (i % cs_per_dimm) * rank_density; |
| 2428 | ea += (i % cs_per_dimm) * rank_density; |
| 2429 | } else { |
| 2430 | sa = 0; |
| 2431 | ea = 0; |
| 2432 | } |
Haiying Wang | 272b596 | 2008-10-03 12:36:39 -0400 | [diff] [blame] | 2433 | break; |
| 2434 | } |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 2435 | } |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 2436 | |
| 2437 | sa >>= 24; |
| 2438 | ea >>= 24; |
| 2439 | |
York Sun | 98df4d1 | 2012-10-08 07:44:23 +0000 | [diff] [blame] | 2440 | if (cs_en) { |
| 2441 | ddr->cs[i].bnds = (0 |
York Sun | 63c91cd | 2013-06-03 12:39:06 -0700 | [diff] [blame] | 2442 | | ((sa & 0xffff) << 16) /* starting address */ |
| 2443 | | ((ea & 0xffff) << 0) /* ending address */ |
York Sun | 98df4d1 | 2012-10-08 07:44:23 +0000 | [diff] [blame] | 2444 | ); |
| 2445 | } else { |
York Sun | c21a739 | 2013-06-25 11:37:45 -0700 | [diff] [blame] | 2446 | /* setting bnds to 0xffffffff for inactive CS */ |
| 2447 | ddr->cs[i].bnds = 0xffffffff; |
York Sun | 98df4d1 | 2012-10-08 07:44:23 +0000 | [diff] [blame] | 2448 | } |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 2449 | |
Haiying Wang | d90e040 | 2008-10-03 12:37:26 -0400 | [diff] [blame] | 2450 | debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds); |
York Sun | 98df4d1 | 2012-10-08 07:44:23 +0000 | [diff] [blame] | 2451 | set_csn_config(dimm_number, i, ddr, popts, dimm_params); |
| 2452 | set_csn_config_2(i, ddr); |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 2453 | } |
| 2454 | |
Haiying Wang | 80ad401 | 2010-12-01 10:35:31 -0500 | [diff] [blame] | 2455 | /* |
| 2456 | * In the case we only need to compute the ddr sdram size, we only need |
| 2457 | * to set csn registers, so return from here. |
| 2458 | */ |
| 2459 | if (size_only) |
| 2460 | return 0; |
| 2461 | |
york | 4260372 | 2010-07-02 22:25:54 +0000 | [diff] [blame] | 2462 | set_ddr_eor(ddr, popts); |
| 2463 | |
York Sun | f062659 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 2464 | #if !defined(CONFIG_SYS_FSL_DDR1) |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 2465 | set_timing_cfg_0(ctrl_num, ddr, popts, dimm_params); |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 2466 | #endif |
| 2467 | |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 2468 | set_timing_cfg_3(ctrl_num, ddr, popts, common_dimm, cas_latency, |
York Sun | 63c91cd | 2013-06-03 12:39:06 -0700 | [diff] [blame] | 2469 | additive_latency); |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 2470 | set_timing_cfg_1(ctrl_num, ddr, popts, common_dimm, cas_latency); |
| 2471 | set_timing_cfg_2(ctrl_num, ddr, popts, common_dimm, |
| 2472 | cas_latency, additive_latency); |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 2473 | |
York Sun | ba0c2eb | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 2474 | set_ddr_cdr1(ddr, popts); |
York Sun | 7d69ea3 | 2012-10-08 07:44:22 +0000 | [diff] [blame] | 2475 | set_ddr_cdr2(ddr, popts); |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 2476 | set_ddr_sdram_cfg(ddr, popts, common_dimm); |
York Sun | 55eb5fa | 2015-03-19 09:30:26 -0700 | [diff] [blame] | 2477 | ip_rev = fsl_ddr_get_version(ctrl_num); |
York Sun | ba0c2eb | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 2478 | if (ip_rev > 0x40400) |
| 2479 | unq_mrs_en = 1; |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 2480 | |
York Sun | a8b3d52 | 2014-09-11 13:32:06 -0700 | [diff] [blame] | 2481 | if ((ip_rev > 0x40700) && (popts->cswl_override != 0)) |
York Sun | e0f6046 | 2014-09-05 13:52:43 +0800 | [diff] [blame] | 2482 | ddr->debug[18] = popts->cswl_override; |
| 2483 | |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 2484 | set_ddr_sdram_cfg_2(ctrl_num, ddr, popts, unq_mrs_en); |
| 2485 | set_ddr_sdram_mode(ctrl_num, ddr, popts, common_dimm, |
| 2486 | cas_latency, additive_latency, unq_mrs_en); |
| 2487 | set_ddr_sdram_mode_2(ctrl_num, ddr, popts, common_dimm, unq_mrs_en); |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 2488 | #ifdef CONFIG_SYS_FSL_DDR4 |
| 2489 | set_ddr_sdram_mode_9(ddr, popts, common_dimm, unq_mrs_en); |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 2490 | set_ddr_sdram_mode_10(ctrl_num, ddr, popts, common_dimm, unq_mrs_en); |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 2491 | #endif |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 2492 | set_ddr_sdram_interval(ctrl_num, ddr, popts, common_dimm); |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 2493 | set_ddr_data_init(ddr); |
| 2494 | set_ddr_sdram_clk_cntl(ddr, popts); |
| 2495 | set_ddr_init_addr(ddr); |
| 2496 | set_ddr_init_ext_addr(ddr); |
Dave Liu | 3525e1a | 2010-03-05 12:22:00 +0800 | [diff] [blame] | 2497 | set_timing_cfg_4(ddr, popts); |
York Sun | ba0c2eb | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 2498 | set_timing_cfg_5(ddr, cas_latency); |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 2499 | #ifdef CONFIG_SYS_FSL_DDR4 |
| 2500 | set_ddr_sdram_cfg_3(ddr, popts); |
| 2501 | set_timing_cfg_6(ddr); |
York Sun | 2c0b62d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 2502 | set_timing_cfg_7(ctrl_num, ddr, common_dimm); |
| 2503 | set_timing_cfg_8(ctrl_num, ddr, popts, common_dimm, cas_latency); |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 2504 | set_timing_cfg_9(ddr); |
| 2505 | set_ddr_dq_mapping(ddr, dimm_params); |
| 2506 | #endif |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 2507 | |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 2508 | set_ddr_zq_cntl(ddr, zq_en); |
Dave Liu | 64ee7df | 2009-12-16 10:24:37 -0600 | [diff] [blame] | 2509 | set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts); |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 2510 | |
Dave Liu | 2aad0ae | 2008-11-21 16:31:35 +0800 | [diff] [blame] | 2511 | set_ddr_sr_cntr(ddr, sr_it); |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 2512 | |
York Sun | ba0c2eb | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 2513 | set_ddr_sdram_rcw(ddr, popts, common_dimm); |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 2514 | |
York Sun | 972cc40 | 2013-06-25 11:37:41 -0700 | [diff] [blame] | 2515 | #ifdef CONFIG_SYS_FSL_DDR_EMU |
| 2516 | /* disble DDR training for emulator */ |
| 2517 | ddr->debug[2] = 0x00000400; |
York Sun | 63f5771 | 2015-01-06 13:18:45 -0800 | [diff] [blame] | 2518 | ddr->debug[4] = 0xff800800; |
| 2519 | ddr->debug[5] = 0x08000800; |
| 2520 | ddr->debug[6] = 0x08000800; |
| 2521 | ddr->debug[7] = 0x08000800; |
| 2522 | ddr->debug[8] = 0x08000800; |
York Sun | 972cc40 | 2013-06-25 11:37:41 -0700 | [diff] [blame] | 2523 | #endif |
York Sun | 9982579 | 2014-05-23 13:15:00 -0700 | [diff] [blame] | 2524 | #ifdef CONFIG_SYS_FSL_ERRATUM_A004508 |
| 2525 | if ((ip_rev >= 0x40000) && (ip_rev < 0x40400)) |
| 2526 | ddr->debug[2] |= 0x00000200; /* set bit 22 */ |
| 2527 | #endif |
| 2528 | |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 2529 | return check_fsl_memctl_config_regs(ddr); |
| 2530 | } |