| commit | d90e040f3681d51ea7c6fd7cb1aa3c63a15311af | [log] [tgz] |
|---|---|---|
| author | Haiying Wang <Haiying.Wang@freescale.com> | Fri Oct 03 12:37:26 2008 -0400 |
| committer | Wolfgang Denk <wd@denx.de> | Sat Oct 18 21:54:05 2008 +0200 |
| tree | 6915cd565889166c69253d825e384a354e8c052e | |
| parent | b834f922390c056b2b97e798c250b0dbc3f9eee0 [diff] |
Add debug information for DDR controller registers Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>