| commit | a8b3d52b7e17dc594036b3ba26650be29e7ad754 | [log] [tgz] |
|---|---|---|
| author | York Sun <yorksun@freescale.com> | Thu Sep 11 13:32:06 2014 -0700 |
| committer | York Sun <yorksun@freescale.com> | Thu Sep 25 08:36:20 2014 -0700 |
| tree | 0d8686b5543a221089465049b6366fc993b826a1 | |
| parent | c4da12e52f9c957fcd750f11e62157e64d43b397 [diff] |
driver/ddr/fsl: Fix DDR4 driver When accumulated ECC is enabled, the DQ_MAP for ECC[4:7] needs to be set to 0, i.e. 0->0, 1->1, etc., required by controller logic, even these pins are not actually connected. Also fix a bug when reading from DDR register to use proper accessor for correct endianess. Signed-off-by: York Sun <yorksun@freescale.com>