| commit | 82aa953c7d0626e84d7d8fa1d2a512ffaa47d9fd | [log] [tgz] |
|---|---|---|
| author | Dave Liu <daveliu@freescale.com> | Sat Mar 14 12:48:19 2009 +0800 |
| committer | Kumar Gala <galak@kernel.crashing.org> | Mon Mar 30 13:33:50 2009 -0500 |
| tree | da8979bf71471ade2083ad1a352a32f74a7234c4 | |
| parent | ac05b5ed60f20c878a860920b8595f0b34289de4 [diff] |
fsl-ddr: Fix two bugs in the ddr infrastructure 1. wr_lat UM said the total write latency for DDR2 is equal to WR_LAT + ADD_LAT, the write latency is CL + ADD_LAT - 1. so, the WR_LAT = CL - 1; 2. rd_to_pre we missed to add the ADD_LAT for DDR2 case. Reported-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Signed-off-by: Dave Liu <daveliu@freescale.com>