| commit | 3525e1aa3e0f37c52b88e660ec90c5538c94dec5 | [log] [tgz] |
|---|---|---|
| author | Dave Liu <daveliu@freescale.com> | Fri Mar 05 12:22:00 2010 +0800 |
| committer | Kumar Gala <galak@kernel.crashing.org> | Wed Apr 07 00:07:23 2010 -0500 |
| tree | 41e5ea01cfc6d023c4789bdf759f447c7cc43dad | |
| parent | e5853af74a2e4d7969bb0567ba6e201aeea1b1b9 [diff] |
fsl-ddr: Fix the turnaround timing for TIMING_CFG_4 Read-to-read/Write-to-write turnaround for same chip select of DDR3 memory, BL/2+2 cycles is enough for them at BC4 and OTF case, BL/2 cycles is enough for fixed BL8. Cutting down the turnaround from BL/2+4 to BL/2+2 or BL/2 will improve the memory performance. Signed-off-by: Dave Liu <daveliu@freescale.com>