Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1 | /* |
Kumar Gala | 14f2eb1 | 2009-09-10 14:54:55 -0500 | [diff] [blame^] | 2 | * Copyright 2008-2009 Freescale Semiconductor, Inc. |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 3 | * |
| 4 | * This program is free software; you can redistribute it and/or |
| 5 | * modify it under the terms of the GNU General Public License |
| 6 | * Version 2 as published by the Free Software Foundation. |
| 7 | */ |
| 8 | |
| 9 | /* |
| 10 | * Generic driver for Freescale DDR/DDR2/DDR3 memory controller. |
| 11 | * Based on code from spd_sdram.c |
| 12 | * Author: James Yang [at freescale.com] |
| 13 | */ |
| 14 | |
| 15 | #include <common.h> |
| 16 | #include <asm/fsl_ddr_sdram.h> |
| 17 | |
| 18 | #include "ddr.h" |
| 19 | |
| 20 | extern unsigned int picos_to_mclk(unsigned int picos); |
| 21 | /* |
| 22 | * Determine Rtt value. |
| 23 | * |
| 24 | * This should likely be either board or controller specific. |
| 25 | * |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 26 | * Rtt(nominal) - DDR2: |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 27 | * 0 = Rtt disabled |
| 28 | * 1 = 75 ohm |
| 29 | * 2 = 150 ohm |
| 30 | * 3 = 50 ohm |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 31 | * Rtt(nominal) - DDR3: |
| 32 | * 0 = Rtt disabled |
| 33 | * 1 = 60 ohm |
| 34 | * 2 = 120 ohm |
| 35 | * 3 = 40 ohm |
| 36 | * 4 = 20 ohm |
| 37 | * 5 = 30 ohm |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 38 | * |
| 39 | * FIXME: Apparently 8641 needs a value of 2 |
| 40 | * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572 |
| 41 | * |
| 42 | * FIXME: There was some effort down this line earlier: |
| 43 | * |
| 44 | * unsigned int i; |
| 45 | * for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) { |
| 46 | * if (popts->dimmslot[i].num_valid_cs |
| 47 | * && (popts->cs_local_opts[2*i].odt_rd_cfg |
| 48 | * || popts->cs_local_opts[2*i].odt_wr_cfg)) { |
| 49 | * rtt = 2; |
| 50 | * break; |
| 51 | * } |
| 52 | * } |
| 53 | */ |
| 54 | static inline int fsl_ddr_get_rtt(void) |
| 55 | { |
| 56 | int rtt; |
| 57 | |
| 58 | #if defined(CONFIG_FSL_DDR1) |
| 59 | rtt = 0; |
| 60 | #elif defined(CONFIG_FSL_DDR2) |
| 61 | rtt = 3; |
| 62 | #else |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 63 | rtt = 0; |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 64 | #endif |
| 65 | |
| 66 | return rtt; |
| 67 | } |
| 68 | |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 69 | /* |
| 70 | * compute the CAS write latency according to DDR3 spec |
| 71 | * CWL = 5 if tCK >= 2.5ns |
| 72 | * 6 if 2.5ns > tCK >= 1.875ns |
| 73 | * 7 if 1.875ns > tCK >= 1.5ns |
| 74 | * 8 if 1.5ns > tCK >= 1.25ns |
| 75 | */ |
| 76 | static inline unsigned int compute_cas_write_latency(void) |
| 77 | { |
| 78 | unsigned int cwl; |
| 79 | const unsigned int mclk_ps = get_memory_clk_period_ps(); |
| 80 | |
| 81 | if (mclk_ps >= 2500) |
| 82 | cwl = 5; |
| 83 | else if (mclk_ps >= 1875) |
| 84 | cwl = 6; |
| 85 | else if (mclk_ps >= 1500) |
| 86 | cwl = 7; |
| 87 | else if (mclk_ps >= 1250) |
| 88 | cwl = 8; |
| 89 | else |
| 90 | cwl = 8; |
| 91 | return cwl; |
| 92 | } |
| 93 | |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 94 | /* Chip Select Configuration (CSn_CONFIG) */ |
| 95 | static void set_csn_config(int i, fsl_ddr_cfg_regs_t *ddr, |
| 96 | const memctl_options_t *popts, |
| 97 | const dimm_params_t *dimm_params) |
| 98 | { |
| 99 | unsigned int cs_n_en = 0; /* Chip Select enable */ |
| 100 | unsigned int intlv_en = 0; /* Memory controller interleave enable */ |
| 101 | unsigned int intlv_ctl = 0; /* Interleaving control */ |
| 102 | unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */ |
| 103 | unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */ |
| 104 | unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */ |
| 105 | unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */ |
| 106 | unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */ |
| 107 | unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */ |
| 108 | |
| 109 | /* Compute CS_CONFIG only for existing ranks of each DIMM. */ |
| 110 | if ((((i&1) == 0) |
| 111 | && (dimm_params[i/2].n_ranks == 1)) |
| 112 | || (dimm_params[i/2].n_ranks == 2)) { |
| 113 | unsigned int n_banks_per_sdram_device; |
| 114 | cs_n_en = 1; |
| 115 | if (i == 0) { |
| 116 | /* These fields only available in CS0_CONFIG */ |
| 117 | intlv_en = popts->memctl_interleaving; |
| 118 | intlv_ctl = popts->memctl_interleaving_mode; |
| 119 | } |
| 120 | ap_n_en = popts->cs_local_opts[i].auto_precharge; |
| 121 | odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg; |
| 122 | odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg; |
| 123 | n_banks_per_sdram_device |
| 124 | = dimm_params[i/2].n_banks_per_sdram_device; |
| 125 | ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2; |
| 126 | row_bits_cs_n = dimm_params[i/2].n_row_addr - 12; |
| 127 | col_bits_cs_n = dimm_params[i/2].n_col_addr - 8; |
| 128 | } |
| 129 | |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 130 | ddr->cs[i].config = (0 |
| 131 | | ((cs_n_en & 0x1) << 31) |
| 132 | | ((intlv_en & 0x3) << 29) |
Haiying Wang | 272b596 | 2008-10-03 12:36:39 -0400 | [diff] [blame] | 133 | | ((intlv_ctl & 0xf) << 24) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 134 | | ((ap_n_en & 0x1) << 23) |
| 135 | |
| 136 | /* XXX: some implementation only have 1 bit starting at left */ |
| 137 | | ((odt_rd_cfg & 0x7) << 20) |
| 138 | |
| 139 | /* XXX: Some implementation only have 1 bit starting at left */ |
| 140 | | ((odt_wr_cfg & 0x7) << 16) |
| 141 | |
| 142 | | ((ba_bits_cs_n & 0x3) << 14) |
| 143 | | ((row_bits_cs_n & 0x7) << 8) |
| 144 | | ((col_bits_cs_n & 0x7) << 0) |
| 145 | ); |
Haiying Wang | d90e040 | 2008-10-03 12:37:26 -0400 | [diff] [blame] | 146 | debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config); |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 147 | } |
| 148 | |
| 149 | /* Chip Select Configuration 2 (CSn_CONFIG_2) */ |
| 150 | /* FIXME: 8572 */ |
| 151 | static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr) |
| 152 | { |
| 153 | unsigned int pasr_cfg = 0; /* Partial array self refresh config */ |
| 154 | |
| 155 | ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24); |
Haiying Wang | d90e040 | 2008-10-03 12:37:26 -0400 | [diff] [blame] | 156 | debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2); |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 157 | } |
| 158 | |
| 159 | /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */ |
| 160 | |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 161 | #if !defined(CONFIG_FSL_DDR1) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 162 | /* |
| 163 | * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0) |
| 164 | * |
| 165 | * Avoid writing for DDR I. The new PQ38 DDR controller |
| 166 | * dreams up non-zero default values to be backwards compatible. |
| 167 | */ |
| 168 | static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr) |
| 169 | { |
| 170 | unsigned char trwt_mclk = 0; /* Read-to-write turnaround */ |
| 171 | unsigned char twrt_mclk = 0; /* Write-to-read turnaround */ |
| 172 | /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */ |
| 173 | unsigned char trrt_mclk = 0; /* Read-to-read turnaround */ |
| 174 | unsigned char twwt_mclk = 0; /* Write-to-write turnaround */ |
| 175 | |
| 176 | /* Active powerdown exit timing (tXARD and tXARDS). */ |
| 177 | unsigned char act_pd_exit_mclk; |
| 178 | /* Precharge powerdown exit timing (tXP). */ |
| 179 | unsigned char pre_pd_exit_mclk; |
| 180 | /* Precharge powerdown exit timing (tAXPD). */ |
| 181 | unsigned char taxpd_mclk; |
| 182 | /* Mode register set cycle time (tMRD). */ |
| 183 | unsigned char tmrd_mclk; |
| 184 | |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 185 | #if defined(CONFIG_FSL_DDR3) |
| 186 | /* |
| 187 | * (tXARD and tXARDS). Empirical? |
| 188 | * The DDR3 spec has not tXARD, |
| 189 | * we use the tXP instead of it. |
| 190 | * tXP=max(3nCK, 7.5ns) for DDR3. |
| 191 | * we use the tXP=6 |
| 192 | * spec has not the tAXPD, we use |
| 193 | * tAXPD=8, need design to confirm. |
| 194 | */ |
| 195 | act_pd_exit_mclk = 6; |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 196 | pre_pd_exit_mclk = 6; |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 197 | taxpd_mclk = 8; |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 198 | tmrd_mclk = 4; |
| 199 | #else /* CONFIG_FSL_DDR2 */ |
| 200 | /* |
| 201 | * (tXARD and tXARDS). Empirical? |
| 202 | * tXARD = 2 for DDR2 |
| 203 | * tXP=2 |
| 204 | * tAXPD=8 |
| 205 | */ |
| 206 | act_pd_exit_mclk = 2; |
| 207 | pre_pd_exit_mclk = 2; |
| 208 | taxpd_mclk = 8; |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 209 | tmrd_mclk = 2; |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 210 | #endif |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 211 | |
| 212 | ddr->timing_cfg_0 = (0 |
| 213 | | ((trwt_mclk & 0x3) << 30) /* RWT */ |
| 214 | | ((twrt_mclk & 0x3) << 28) /* WRT */ |
| 215 | | ((trrt_mclk & 0x3) << 26) /* RRT */ |
| 216 | | ((twwt_mclk & 0x3) << 24) /* WWT */ |
| 217 | | ((act_pd_exit_mclk & 0x7) << 20) /* ACT_PD_EXIT */ |
Dave Liu | 4758d53 | 2008-11-21 16:31:29 +0800 | [diff] [blame] | 218 | | ((pre_pd_exit_mclk & 0xF) << 16) /* PRE_PD_EXIT */ |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 219 | | ((taxpd_mclk & 0xf) << 8) /* ODT_PD_EXIT */ |
| 220 | | ((tmrd_mclk & 0xf) << 0) /* MRS_CYC */ |
| 221 | ); |
| 222 | debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0); |
| 223 | } |
| 224 | #endif /* defined(CONFIG_FSL_DDR2) */ |
| 225 | |
| 226 | /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */ |
| 227 | static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr, |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 228 | const common_timing_params_t *common_dimm, |
| 229 | unsigned int cas_latency) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 230 | { |
| 231 | /* Extended Activate to precharge interval (tRAS) */ |
| 232 | unsigned int ext_acttopre = 0; |
| 233 | unsigned int ext_refrec; /* Extended refresh recovery time (tRFC) */ |
| 234 | unsigned int ext_caslat = 0; /* Extended MCAS latency from READ cmd */ |
| 235 | unsigned int cntl_adj = 0; /* Control Adjust */ |
| 236 | |
Dave Liu | 5c1bb51 | 2008-11-21 16:31:22 +0800 | [diff] [blame] | 237 | /* If the tRAS > 19 MCLK, we use the ext mode */ |
| 238 | if (picos_to_mclk(common_dimm->tRAS_ps) > 0x13) |
| 239 | ext_acttopre = 1; |
| 240 | |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 241 | ext_refrec = (picos_to_mclk(common_dimm->tRFC_ps) - 8) >> 4; |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 242 | |
| 243 | /* If the CAS latency more than 8, use the ext mode */ |
| 244 | if (cas_latency > 8) |
| 245 | ext_caslat = 1; |
| 246 | |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 247 | ddr->timing_cfg_3 = (0 |
| 248 | | ((ext_acttopre & 0x1) << 24) |
Dave Liu | 5c1bb51 | 2008-11-21 16:31:22 +0800 | [diff] [blame] | 249 | | ((ext_refrec & 0xF) << 16) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 250 | | ((ext_caslat & 0x1) << 12) |
| 251 | | ((cntl_adj & 0x7) << 0) |
| 252 | ); |
Haiying Wang | d90e040 | 2008-10-03 12:37:26 -0400 | [diff] [blame] | 253 | debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3); |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 254 | } |
| 255 | |
| 256 | /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */ |
| 257 | static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr, |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 258 | const memctl_options_t *popts, |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 259 | const common_timing_params_t *common_dimm, |
| 260 | unsigned int cas_latency) |
| 261 | { |
| 262 | /* Precharge-to-activate interval (tRP) */ |
| 263 | unsigned char pretoact_mclk; |
| 264 | /* Activate to precharge interval (tRAS) */ |
| 265 | unsigned char acttopre_mclk; |
| 266 | /* Activate to read/write interval (tRCD) */ |
| 267 | unsigned char acttorw_mclk; |
| 268 | /* CASLAT */ |
| 269 | unsigned char caslat_ctrl; |
| 270 | /* Refresh recovery time (tRFC) ; trfc_low */ |
| 271 | unsigned char refrec_ctrl; |
| 272 | /* Last data to precharge minimum interval (tWR) */ |
| 273 | unsigned char wrrec_mclk; |
| 274 | /* Activate-to-activate interval (tRRD) */ |
| 275 | unsigned char acttoact_mclk; |
| 276 | /* Last write data pair to read command issue interval (tWTR) */ |
| 277 | unsigned char wrtord_mclk; |
| 278 | |
| 279 | pretoact_mclk = picos_to_mclk(common_dimm->tRP_ps); |
| 280 | acttopre_mclk = picos_to_mclk(common_dimm->tRAS_ps); |
| 281 | acttorw_mclk = picos_to_mclk(common_dimm->tRCD_ps); |
| 282 | |
| 283 | /* |
| 284 | * Translate CAS Latency to a DDR controller field value: |
| 285 | * |
| 286 | * CAS Lat DDR I DDR II Ctrl |
| 287 | * Clocks SPD Bit SPD Bit Value |
| 288 | * ------- ------- ------- ----- |
| 289 | * 1.0 0 0001 |
| 290 | * 1.5 1 0010 |
| 291 | * 2.0 2 2 0011 |
| 292 | * 2.5 3 0100 |
| 293 | * 3.0 4 3 0101 |
| 294 | * 3.5 5 0110 |
| 295 | * 4.0 4 0111 |
| 296 | * 4.5 1000 |
| 297 | * 5.0 5 1001 |
| 298 | */ |
| 299 | #if defined(CONFIG_FSL_DDR1) |
| 300 | caslat_ctrl = (cas_latency + 1) & 0x07; |
| 301 | #elif defined(CONFIG_FSL_DDR2) |
| 302 | caslat_ctrl = 2 * cas_latency - 1; |
| 303 | #else |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 304 | /* |
| 305 | * if the CAS latency more than 8 cycle, |
| 306 | * we need set extend bit for it at |
| 307 | * TIMING_CFG_3[EXT_CASLAT] |
| 308 | */ |
| 309 | if (cas_latency > 8) |
| 310 | cas_latency -= 8; |
| 311 | caslat_ctrl = 2 * cas_latency - 1; |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 312 | #endif |
| 313 | |
| 314 | refrec_ctrl = picos_to_mclk(common_dimm->tRFC_ps) - 8; |
| 315 | wrrec_mclk = picos_to_mclk(common_dimm->tWR_ps); |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 316 | if (popts->OTF_burst_chop_en) |
| 317 | wrrec_mclk += 2; |
| 318 | |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 319 | acttoact_mclk = picos_to_mclk(common_dimm->tRRD_ps); |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 320 | /* |
| 321 | * JEDEC has min requirement for tRRD |
| 322 | */ |
| 323 | #if defined(CONFIG_FSL_DDR3) |
| 324 | if (acttoact_mclk < 4) |
| 325 | acttoact_mclk = 4; |
| 326 | #endif |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 327 | wrtord_mclk = picos_to_mclk(common_dimm->tWTR_ps); |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 328 | /* |
| 329 | * JEDEC has some min requirements for tWTR |
| 330 | */ |
| 331 | #if defined(CONFIG_FSL_DDR2) |
| 332 | if (wrtord_mclk < 2) |
| 333 | wrtord_mclk = 2; |
| 334 | #elif defined(CONFIG_FSL_DDR3) |
| 335 | if (wrtord_mclk < 4) |
| 336 | wrtord_mclk = 4; |
| 337 | #endif |
| 338 | if (popts->OTF_burst_chop_en) |
| 339 | wrtord_mclk += 2; |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 340 | |
| 341 | ddr->timing_cfg_1 = (0 |
Dave Liu | 5c1bb51 | 2008-11-21 16:31:22 +0800 | [diff] [blame] | 342 | | ((pretoact_mclk & 0x0F) << 28) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 343 | | ((acttopre_mclk & 0x0F) << 24) |
Dave Liu | 5c1bb51 | 2008-11-21 16:31:22 +0800 | [diff] [blame] | 344 | | ((acttorw_mclk & 0xF) << 20) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 345 | | ((caslat_ctrl & 0xF) << 16) |
| 346 | | ((refrec_ctrl & 0xF) << 12) |
Dave Liu | 5c1bb51 | 2008-11-21 16:31:22 +0800 | [diff] [blame] | 347 | | ((wrrec_mclk & 0x0F) << 8) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 348 | | ((acttoact_mclk & 0x07) << 4) |
| 349 | | ((wrtord_mclk & 0x07) << 0) |
| 350 | ); |
Haiying Wang | d90e040 | 2008-10-03 12:37:26 -0400 | [diff] [blame] | 351 | debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1); |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 352 | } |
| 353 | |
| 354 | /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */ |
| 355 | static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr, |
| 356 | const memctl_options_t *popts, |
| 357 | const common_timing_params_t *common_dimm, |
| 358 | unsigned int cas_latency, |
| 359 | unsigned int additive_latency) |
| 360 | { |
| 361 | /* Additive latency */ |
| 362 | unsigned char add_lat_mclk; |
| 363 | /* CAS-to-preamble override */ |
| 364 | unsigned short cpo; |
| 365 | /* Write latency */ |
| 366 | unsigned char wr_lat; |
| 367 | /* Read to precharge (tRTP) */ |
| 368 | unsigned char rd_to_pre; |
| 369 | /* Write command to write data strobe timing adjustment */ |
| 370 | unsigned char wr_data_delay; |
| 371 | /* Minimum CKE pulse width (tCKE) */ |
| 372 | unsigned char cke_pls; |
| 373 | /* Window for four activates (tFAW) */ |
| 374 | unsigned short four_act; |
| 375 | |
| 376 | /* FIXME add check that this must be less than acttorw_mclk */ |
| 377 | add_lat_mclk = additive_latency; |
| 378 | cpo = popts->cpo_override; |
| 379 | |
| 380 | #if defined(CONFIG_FSL_DDR1) |
| 381 | /* |
| 382 | * This is a lie. It should really be 1, but if it is |
| 383 | * set to 1, bits overlap into the old controller's |
| 384 | * otherwise unused ACSM field. If we leave it 0, then |
| 385 | * the HW will magically treat it as 1 for DDR 1. Oh Yea. |
| 386 | */ |
| 387 | wr_lat = 0; |
| 388 | #elif defined(CONFIG_FSL_DDR2) |
Dave Liu | 82aa953 | 2009-03-14 12:48:19 +0800 | [diff] [blame] | 389 | wr_lat = cas_latency - 1; |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 390 | #else |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 391 | wr_lat = compute_cas_write_latency(); |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 392 | #endif |
| 393 | |
| 394 | rd_to_pre = picos_to_mclk(common_dimm->tRTP_ps); |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 395 | /* |
| 396 | * JEDEC has some min requirements for tRTP |
| 397 | */ |
Dave Liu | 82aa953 | 2009-03-14 12:48:19 +0800 | [diff] [blame] | 398 | #if defined(CONFIG_FSL_DDR2) |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 399 | if (rd_to_pre < 2) |
| 400 | rd_to_pre = 2; |
| 401 | #elif defined(CONFIG_FSL_DDR3) |
| 402 | if (rd_to_pre < 4) |
| 403 | rd_to_pre = 4; |
Dave Liu | 82aa953 | 2009-03-14 12:48:19 +0800 | [diff] [blame] | 404 | #endif |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 405 | if (additive_latency) |
| 406 | rd_to_pre += additive_latency; |
| 407 | if (popts->OTF_burst_chop_en) |
| 408 | rd_to_pre += 2; /* according to UM */ |
| 409 | |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 410 | wr_data_delay = popts->write_data_delay; |
| 411 | cke_pls = picos_to_mclk(popts->tCKE_clock_pulse_width_ps); |
| 412 | four_act = picos_to_mclk(popts->tFAW_window_four_activates_ps); |
| 413 | |
| 414 | ddr->timing_cfg_2 = (0 |
Dave Liu | 4758d53 | 2008-11-21 16:31:29 +0800 | [diff] [blame] | 415 | | ((add_lat_mclk & 0xf) << 28) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 416 | | ((cpo & 0x1f) << 23) |
Dave Liu | 4758d53 | 2008-11-21 16:31:29 +0800 | [diff] [blame] | 417 | | ((wr_lat & 0xf) << 19) |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 418 | | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT) |
| 419 | | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 420 | | ((cke_pls & 0x7) << 6) |
Dave Liu | 4758d53 | 2008-11-21 16:31:29 +0800 | [diff] [blame] | 421 | | ((four_act & 0x3f) << 0) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 422 | ); |
Haiying Wang | d90e040 | 2008-10-03 12:37:26 -0400 | [diff] [blame] | 423 | debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2); |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 424 | } |
| 425 | |
| 426 | /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */ |
| 427 | static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, |
| 428 | const memctl_options_t *popts, |
| 429 | const common_timing_params_t *common_dimm) |
| 430 | { |
| 431 | unsigned int mem_en; /* DDR SDRAM interface logic enable */ |
| 432 | unsigned int sren; /* Self refresh enable (during sleep) */ |
| 433 | unsigned int ecc_en; /* ECC enable. */ |
| 434 | unsigned int rd_en; /* Registered DIMM enable */ |
| 435 | unsigned int sdram_type; /* Type of SDRAM */ |
| 436 | unsigned int dyn_pwr; /* Dynamic power management mode */ |
| 437 | unsigned int dbw; /* DRAM dta bus width */ |
Dave Liu | 4758d53 | 2008-11-21 16:31:29 +0800 | [diff] [blame] | 438 | unsigned int eight_be = 0; /* 8-beat burst enable, DDR2 is zero */ |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 439 | unsigned int ncap = 0; /* Non-concurrent auto-precharge */ |
| 440 | unsigned int threeT_en; /* Enable 3T timing */ |
| 441 | unsigned int twoT_en; /* Enable 2T timing */ |
| 442 | unsigned int ba_intlv_ctl; /* Bank (CS) interleaving control */ |
| 443 | unsigned int x32_en = 0; /* x32 enable */ |
| 444 | unsigned int pchb8 = 0; /* precharge bit 8 enable */ |
| 445 | unsigned int hse; /* Global half strength override */ |
| 446 | unsigned int mem_halt = 0; /* memory controller halt */ |
| 447 | unsigned int bi = 0; /* Bypass initialization */ |
| 448 | |
| 449 | mem_en = 1; |
| 450 | sren = popts->self_refresh_in_sleep; |
| 451 | if (common_dimm->all_DIMMs_ECC_capable) { |
| 452 | /* Allow setting of ECC only if all DIMMs are ECC. */ |
| 453 | ecc_en = popts->ECC_mode; |
| 454 | } else { |
| 455 | ecc_en = 0; |
| 456 | } |
| 457 | |
| 458 | rd_en = (common_dimm->all_DIMMs_registered |
| 459 | && !common_dimm->all_DIMMs_unbuffered); |
| 460 | |
| 461 | sdram_type = CONFIG_FSL_SDRAM_TYPE; |
| 462 | |
| 463 | dyn_pwr = popts->dynamic_power; |
| 464 | dbw = popts->data_bus_width; |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 465 | /* 8-beat burst enable DDR-III case |
| 466 | * we must clear it when use the on-the-fly mode, |
| 467 | * must set it when use the 32-bits bus mode. |
| 468 | */ |
| 469 | if (sdram_type == SDRAM_TYPE_DDR3) { |
| 470 | if (popts->burst_length == DDR_BL8) |
| 471 | eight_be = 1; |
| 472 | if (popts->burst_length == DDR_OTF) |
| 473 | eight_be = 0; |
| 474 | if (dbw == 0x1) |
| 475 | eight_be = 1; |
| 476 | } |
| 477 | |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 478 | threeT_en = popts->threeT_en; |
| 479 | twoT_en = popts->twoT_en; |
| 480 | ba_intlv_ctl = popts->ba_intlv_ctl; |
| 481 | hse = popts->half_strength_driver_enable; |
| 482 | |
| 483 | ddr->ddr_sdram_cfg = (0 |
| 484 | | ((mem_en & 0x1) << 31) |
| 485 | | ((sren & 0x1) << 30) |
| 486 | | ((ecc_en & 0x1) << 29) |
| 487 | | ((rd_en & 0x1) << 28) |
| 488 | | ((sdram_type & 0x7) << 24) |
| 489 | | ((dyn_pwr & 0x1) << 21) |
| 490 | | ((dbw & 0x3) << 19) |
| 491 | | ((eight_be & 0x1) << 18) |
| 492 | | ((ncap & 0x1) << 17) |
| 493 | | ((threeT_en & 0x1) << 16) |
| 494 | | ((twoT_en & 0x1) << 15) |
| 495 | | ((ba_intlv_ctl & 0x7F) << 8) |
| 496 | | ((x32_en & 0x1) << 5) |
| 497 | | ((pchb8 & 0x1) << 4) |
| 498 | | ((hse & 0x1) << 3) |
| 499 | | ((mem_halt & 0x1) << 1) |
| 500 | | ((bi & 0x1) << 0) |
| 501 | ); |
Haiying Wang | d90e040 | 2008-10-03 12:37:26 -0400 | [diff] [blame] | 502 | debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg); |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 503 | } |
| 504 | |
| 505 | /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */ |
| 506 | static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, |
| 507 | const memctl_options_t *popts) |
| 508 | { |
| 509 | unsigned int frc_sr = 0; /* Force self refresh */ |
| 510 | unsigned int sr_ie = 0; /* Self-refresh interrupt enable */ |
| 511 | unsigned int dll_rst_dis; /* DLL reset disable */ |
| 512 | unsigned int dqs_cfg; /* DQS configuration */ |
| 513 | unsigned int odt_cfg; /* ODT configuration */ |
| 514 | unsigned int num_pr; /* Number of posted refreshes */ |
| 515 | unsigned int obc_cfg; /* On-The-Fly Burst Chop Cfg */ |
| 516 | unsigned int ap_en; /* Address Parity Enable */ |
| 517 | unsigned int d_init; /* DRAM data initialization */ |
| 518 | unsigned int rcw_en = 0; /* Register Control Word Enable */ |
| 519 | unsigned int md_en = 0; /* Mirrored DIMM Enable */ |
| 520 | |
| 521 | dll_rst_dis = 1; /* Make this configurable */ |
| 522 | dqs_cfg = popts->DQS_config; |
| 523 | if (popts->cs_local_opts[0].odt_rd_cfg |
| 524 | || popts->cs_local_opts[0].odt_wr_cfg) { |
| 525 | /* FIXME */ |
| 526 | odt_cfg = 2; |
| 527 | } else { |
| 528 | odt_cfg = 0; |
| 529 | } |
| 530 | |
| 531 | num_pr = 1; /* Make this configurable */ |
| 532 | |
| 533 | /* |
| 534 | * 8572 manual says |
| 535 | * {TIMING_CFG_1[PRETOACT] |
| 536 | * + [DDR_SDRAM_CFG_2[NUM_PR] |
| 537 | * * ({EXT_REFREC || REFREC} + 8 + 2)]} |
| 538 | * << DDR_SDRAM_INTERVAL[REFINT] |
| 539 | */ |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 540 | #if defined(CONFIG_FSL_DDR3) |
| 541 | obc_cfg = popts->OTF_burst_chop_en; |
| 542 | #else |
| 543 | obc_cfg = 0; |
| 544 | #endif |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 545 | |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 546 | ap_en = 0; /* Make this configurable? */ |
| 547 | |
| 548 | #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) |
| 549 | /* Use the DDR controller to auto initialize memory. */ |
| 550 | d_init = 1; |
| 551 | ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE; |
| 552 | debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init); |
| 553 | #else |
| 554 | /* Memory will be initialized via DMA, or not at all. */ |
| 555 | d_init = 0; |
| 556 | #endif |
| 557 | |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 558 | #if defined(CONFIG_FSL_DDR3) |
| 559 | md_en = popts->mirrored_dimm; |
| 560 | #endif |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 561 | ddr->ddr_sdram_cfg_2 = (0 |
| 562 | | ((frc_sr & 0x1) << 31) |
| 563 | | ((sr_ie & 0x1) << 30) |
| 564 | | ((dll_rst_dis & 0x1) << 29) |
| 565 | | ((dqs_cfg & 0x3) << 26) |
| 566 | | ((odt_cfg & 0x3) << 21) |
| 567 | | ((num_pr & 0xf) << 12) |
| 568 | | ((obc_cfg & 0x1) << 6) |
| 569 | | ((ap_en & 0x1) << 5) |
| 570 | | ((d_init & 0x1) << 4) |
| 571 | | ((rcw_en & 0x1) << 2) |
| 572 | | ((md_en & 0x1) << 0) |
| 573 | ); |
Haiying Wang | d90e040 | 2008-10-03 12:37:26 -0400 | [diff] [blame] | 574 | debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2); |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 575 | } |
| 576 | |
| 577 | /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */ |
| 578 | static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr) |
| 579 | { |
| 580 | unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */ |
| 581 | unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */ |
| 582 | |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 583 | #if defined(CONFIG_FSL_DDR3) |
| 584 | unsigned int rtt_wr = 2; /* 120 ohm Rtt_WR */ |
| 585 | unsigned int srt = 0; /* self-refresh temerature, normal range */ |
| 586 | unsigned int asr = 0; /* auto self-refresh disable */ |
| 587 | unsigned int cwl = compute_cas_write_latency() - 5; |
| 588 | unsigned int pasr = 0; /* partial array self refresh disable */ |
| 589 | |
| 590 | esdmode2 = (0 |
| 591 | | ((rtt_wr & 0x3) << 9) |
| 592 | | ((srt & 0x1) << 7) |
| 593 | | ((asr & 0x1) << 6) |
| 594 | | ((cwl & 0x7) << 3) |
| 595 | | ((pasr & 0x7) << 0)); |
| 596 | #endif |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 597 | ddr->ddr_sdram_mode_2 = (0 |
| 598 | | ((esdmode2 & 0xFFFF) << 16) |
| 599 | | ((esdmode3 & 0xFFFF) << 0) |
| 600 | ); |
Haiying Wang | d90e040 | 2008-10-03 12:37:26 -0400 | [diff] [blame] | 601 | debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2); |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 602 | } |
| 603 | |
| 604 | /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */ |
| 605 | static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr, |
| 606 | const memctl_options_t *popts, |
| 607 | const common_timing_params_t *common_dimm) |
| 608 | { |
| 609 | unsigned int refint; /* Refresh interval */ |
| 610 | unsigned int bstopre; /* Precharge interval */ |
| 611 | |
| 612 | refint = picos_to_mclk(common_dimm->refresh_rate_ps); |
| 613 | |
| 614 | bstopre = popts->bstopre; |
| 615 | |
| 616 | /* refint field used 0x3FFF in earlier controllers */ |
| 617 | ddr->ddr_sdram_interval = (0 |
| 618 | | ((refint & 0xFFFF) << 16) |
| 619 | | ((bstopre & 0x3FFF) << 0) |
| 620 | ); |
Haiying Wang | d90e040 | 2008-10-03 12:37:26 -0400 | [diff] [blame] | 621 | debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval); |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 622 | } |
| 623 | |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 624 | #if defined(CONFIG_FSL_DDR3) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 625 | /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */ |
| 626 | static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, |
| 627 | const memctl_options_t *popts, |
| 628 | const common_timing_params_t *common_dimm, |
| 629 | unsigned int cas_latency, |
| 630 | unsigned int additive_latency) |
| 631 | { |
| 632 | unsigned short esdmode; /* Extended SDRAM mode */ |
| 633 | unsigned short sdmode; /* SDRAM mode */ |
| 634 | |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 635 | /* Mode Register - MR1 */ |
| 636 | unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */ |
| 637 | unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */ |
| 638 | unsigned int rtt; |
| 639 | unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */ |
| 640 | unsigned int al = 0; /* Posted CAS# additive latency (AL) */ |
| 641 | unsigned int dic = 1; /* Output driver impedance, 34ohm */ |
| 642 | unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal), |
| 643 | 1=Disable (Test/Debug) */ |
| 644 | |
| 645 | /* Mode Register - MR0 */ |
| 646 | unsigned int dll_on; /* DLL control for precharge PD, 0=off, 1=on */ |
| 647 | unsigned int wr; /* Write Recovery */ |
| 648 | unsigned int dll_rst; /* DLL Reset */ |
| 649 | unsigned int mode; /* Normal=0 or Test=1 */ |
| 650 | unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */ |
| 651 | /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */ |
| 652 | unsigned int bt; |
| 653 | unsigned int bl; /* BL: Burst Length */ |
| 654 | |
| 655 | unsigned int wr_mclk; |
| 656 | |
| 657 | const unsigned int mclk_ps = get_memory_clk_period_ps(); |
| 658 | |
| 659 | rtt = fsl_ddr_get_rtt(); |
| 660 | if (popts->rtt_override) |
| 661 | rtt = popts->rtt_override_value; |
| 662 | |
| 663 | if (additive_latency == (cas_latency - 1)) |
| 664 | al = 1; |
| 665 | if (additive_latency == (cas_latency - 2)) |
| 666 | al = 2; |
| 667 | |
| 668 | /* |
| 669 | * The esdmode value will also be used for writing |
| 670 | * MR1 during write leveling for DDR3, although the |
| 671 | * bits specifically related to the write leveling |
| 672 | * scheme will be handled automatically by the DDR |
| 673 | * controller. so we set the wrlvl_en = 0 here. |
| 674 | */ |
| 675 | esdmode = (0 |
| 676 | | ((qoff & 0x1) << 12) |
| 677 | | ((tdqs_en & 0x1) << 11) |
Kumar Gala | 14f2eb1 | 2009-09-10 14:54:55 -0500 | [diff] [blame^] | 678 | | ((rtt & 0x4) << 7) /* rtt field is split */ |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 679 | | ((wrlvl_en & 0x1) << 7) |
Kumar Gala | 14f2eb1 | 2009-09-10 14:54:55 -0500 | [diff] [blame^] | 680 | | ((rtt & 0x2) << 5) /* rtt field is split */ |
| 681 | | ((dic & 0x2) << 4) /* DIC field is split */ |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 682 | | ((al & 0x3) << 3) |
Kumar Gala | 14f2eb1 | 2009-09-10 14:54:55 -0500 | [diff] [blame^] | 683 | | ((rtt & 0x1) << 2) /* rtt field is split */ |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 684 | | ((dic & 0x1) << 1) /* DIC field is split */ |
| 685 | | ((dll_en & 0x1) << 0) |
| 686 | ); |
| 687 | |
| 688 | /* |
| 689 | * DLL control for precharge PD |
| 690 | * 0=slow exit DLL off (tXPDLL) |
| 691 | * 1=fast exit DLL on (tXP) |
| 692 | */ |
| 693 | dll_on = 1; |
| 694 | wr_mclk = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps; |
| 695 | if (wr_mclk >= 12) |
| 696 | wr = 6; |
| 697 | else if (wr_mclk >= 9) |
| 698 | wr = 5; |
| 699 | else |
| 700 | wr = wr_mclk - 4; |
| 701 | dll_rst = 0; /* dll no reset */ |
| 702 | mode = 0; /* normal mode */ |
| 703 | |
| 704 | /* look up table to get the cas latency bits */ |
| 705 | if (cas_latency >= 5 && cas_latency <= 11) { |
| 706 | unsigned char cas_latency_table[7] = { |
| 707 | 0x2, /* 5 clocks */ |
| 708 | 0x4, /* 6 clocks */ |
| 709 | 0x6, /* 7 clocks */ |
| 710 | 0x8, /* 8 clocks */ |
| 711 | 0xa, /* 9 clocks */ |
| 712 | 0xc, /* 10 clocks */ |
| 713 | 0xe /* 11 clocks */ |
| 714 | }; |
| 715 | caslat = cas_latency_table[cas_latency - 5]; |
| 716 | } |
| 717 | bt = 0; /* Nibble sequential */ |
| 718 | |
| 719 | switch (popts->burst_length) { |
| 720 | case DDR_BL8: |
| 721 | bl = 0; |
| 722 | break; |
| 723 | case DDR_OTF: |
| 724 | bl = 1; |
| 725 | break; |
| 726 | case DDR_BC4: |
| 727 | bl = 2; |
| 728 | break; |
| 729 | default: |
| 730 | printf("Error: invalid burst length of %u specified. " |
| 731 | " Defaulting to on-the-fly BC4 or BL8 beats.\n", |
| 732 | popts->burst_length); |
| 733 | bl = 1; |
| 734 | break; |
| 735 | } |
| 736 | |
| 737 | sdmode = (0 |
| 738 | | ((dll_on & 0x1) << 12) |
| 739 | | ((wr & 0x7) << 9) |
| 740 | | ((dll_rst & 0x1) << 8) |
| 741 | | ((mode & 0x1) << 7) |
| 742 | | (((caslat >> 1) & 0x7) << 4) |
| 743 | | ((bt & 0x1) << 3) |
| 744 | | ((bl & 0x3) << 0) |
| 745 | ); |
| 746 | |
| 747 | ddr->ddr_sdram_mode = (0 |
| 748 | | ((esdmode & 0xFFFF) << 16) |
| 749 | | ((sdmode & 0xFFFF) << 0) |
| 750 | ); |
| 751 | |
| 752 | debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode); |
| 753 | } |
| 754 | |
| 755 | #else /* !CONFIG_FSL_DDR3 */ |
| 756 | |
| 757 | /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */ |
| 758 | static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, |
| 759 | const memctl_options_t *popts, |
| 760 | const common_timing_params_t *common_dimm, |
| 761 | unsigned int cas_latency, |
| 762 | unsigned int additive_latency) |
| 763 | { |
| 764 | unsigned short esdmode; /* Extended SDRAM mode */ |
| 765 | unsigned short sdmode; /* SDRAM mode */ |
| 766 | |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 767 | /* |
| 768 | * FIXME: This ought to be pre-calculated in a |
| 769 | * technology-specific routine, |
| 770 | * e.g. compute_DDR2_mode_register(), and then the |
| 771 | * sdmode and esdmode passed in as part of common_dimm. |
| 772 | */ |
| 773 | |
| 774 | /* Extended Mode Register */ |
| 775 | unsigned int mrs = 0; /* Mode Register Set */ |
| 776 | unsigned int outputs = 0; /* 0=Enabled, 1=Disabled */ |
| 777 | unsigned int rdqs_en = 0; /* RDQS Enable: 0=no, 1=yes */ |
| 778 | unsigned int dqs_en = 0; /* DQS# Enable: 0=enable, 1=disable */ |
| 779 | unsigned int ocd = 0; /* 0x0=OCD not supported, |
| 780 | 0x7=OCD default state */ |
| 781 | unsigned int rtt; |
| 782 | unsigned int al; /* Posted CAS# additive latency (AL) */ |
| 783 | unsigned int ods = 0; /* Output Drive Strength: |
| 784 | 0 = Full strength (18ohm) |
| 785 | 1 = Reduced strength (4ohm) */ |
| 786 | unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal), |
| 787 | 1=Disable (Test/Debug) */ |
| 788 | |
| 789 | /* Mode Register (MR) */ |
| 790 | unsigned int mr; /* Mode Register Definition */ |
| 791 | unsigned int pd; /* Power-Down Mode */ |
| 792 | unsigned int wr; /* Write Recovery */ |
| 793 | unsigned int dll_res; /* DLL Reset */ |
| 794 | unsigned int mode; /* Normal=0 or Test=1 */ |
Kumar Gala | 35ad58d | 2008-09-05 14:40:29 -0500 | [diff] [blame] | 795 | unsigned int caslat = 0;/* CAS# latency */ |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 796 | /* BT: Burst Type (0=Sequential, 1=Interleaved) */ |
| 797 | unsigned int bt; |
| 798 | unsigned int bl; /* BL: Burst Length */ |
| 799 | |
| 800 | #if defined(CONFIG_FSL_DDR2) |
| 801 | const unsigned int mclk_ps = get_memory_clk_period_ps(); |
| 802 | #endif |
| 803 | |
| 804 | rtt = fsl_ddr_get_rtt(); |
| 805 | |
| 806 | al = additive_latency; |
| 807 | |
| 808 | esdmode = (0 |
| 809 | | ((mrs & 0x3) << 14) |
| 810 | | ((outputs & 0x1) << 12) |
| 811 | | ((rdqs_en & 0x1) << 11) |
| 812 | | ((dqs_en & 0x1) << 10) |
| 813 | | ((ocd & 0x7) << 7) |
| 814 | | ((rtt & 0x2) << 5) /* rtt field is split */ |
| 815 | | ((al & 0x7) << 3) |
| 816 | | ((rtt & 0x1) << 2) /* rtt field is split */ |
| 817 | | ((ods & 0x1) << 1) |
| 818 | | ((dll_en & 0x1) << 0) |
| 819 | ); |
| 820 | |
| 821 | mr = 0; /* FIXME: CHECKME */ |
| 822 | |
| 823 | /* |
| 824 | * 0 = Fast Exit (Normal) |
| 825 | * 1 = Slow Exit (Low Power) |
| 826 | */ |
| 827 | pd = 0; |
| 828 | |
| 829 | #if defined(CONFIG_FSL_DDR1) |
| 830 | wr = 0; /* Historical */ |
| 831 | #elif defined(CONFIG_FSL_DDR2) |
| 832 | wr = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps - 1; |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 833 | #endif |
| 834 | dll_res = 0; |
| 835 | mode = 0; |
| 836 | |
| 837 | #if defined(CONFIG_FSL_DDR1) |
| 838 | if (1 <= cas_latency && cas_latency <= 4) { |
| 839 | unsigned char mode_caslat_table[4] = { |
| 840 | 0x5, /* 1.5 clocks */ |
| 841 | 0x2, /* 2.0 clocks */ |
| 842 | 0x6, /* 2.5 clocks */ |
| 843 | 0x3 /* 3.0 clocks */ |
| 844 | }; |
Kumar Gala | 35ad58d | 2008-09-05 14:40:29 -0500 | [diff] [blame] | 845 | caslat = mode_caslat_table[cas_latency - 1]; |
| 846 | } else { |
| 847 | printf("Warning: unknown cas_latency %d\n", cas_latency); |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 848 | } |
| 849 | #elif defined(CONFIG_FSL_DDR2) |
| 850 | caslat = cas_latency; |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 851 | #endif |
| 852 | bt = 0; |
| 853 | |
| 854 | switch (popts->burst_length) { |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 855 | case DDR_BL4: |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 856 | bl = 2; |
| 857 | break; |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 858 | case DDR_BL8: |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 859 | bl = 3; |
| 860 | break; |
| 861 | default: |
| 862 | printf("Error: invalid burst length of %u specified. " |
| 863 | " Defaulting to 4 beats.\n", |
| 864 | popts->burst_length); |
| 865 | bl = 2; |
| 866 | break; |
| 867 | } |
| 868 | |
| 869 | sdmode = (0 |
| 870 | | ((mr & 0x3) << 14) |
| 871 | | ((pd & 0x1) << 12) |
| 872 | | ((wr & 0x7) << 9) |
| 873 | | ((dll_res & 0x1) << 8) |
| 874 | | ((mode & 0x1) << 7) |
| 875 | | ((caslat & 0x7) << 4) |
| 876 | | ((bt & 0x1) << 3) |
| 877 | | ((bl & 0x7) << 0) |
| 878 | ); |
| 879 | |
| 880 | ddr->ddr_sdram_mode = (0 |
| 881 | | ((esdmode & 0xFFFF) << 16) |
| 882 | | ((sdmode & 0xFFFF) << 0) |
| 883 | ); |
Haiying Wang | d90e040 | 2008-10-03 12:37:26 -0400 | [diff] [blame] | 884 | debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode); |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 885 | } |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 886 | #endif |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 887 | |
| 888 | /* DDR SDRAM Data Initialization (DDR_DATA_INIT) */ |
| 889 | static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr) |
| 890 | { |
| 891 | unsigned int init_value; /* Initialization value */ |
| 892 | |
| 893 | init_value = 0xDEADBEEF; |
| 894 | ddr->ddr_data_init = init_value; |
| 895 | } |
| 896 | |
| 897 | /* |
| 898 | * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL) |
| 899 | * The old controller on the 8540/60 doesn't have this register. |
| 900 | * Hope it's OK to set it (to 0) anyway. |
| 901 | */ |
| 902 | static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr, |
| 903 | const memctl_options_t *popts) |
| 904 | { |
| 905 | unsigned int clk_adjust; /* Clock adjust */ |
| 906 | |
| 907 | clk_adjust = popts->clk_adjust; |
| 908 | ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23; |
| 909 | } |
| 910 | |
| 911 | /* DDR Initialization Address (DDR_INIT_ADDR) */ |
| 912 | static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr) |
| 913 | { |
| 914 | unsigned int init_addr = 0; /* Initialization address */ |
| 915 | |
| 916 | ddr->ddr_init_addr = init_addr; |
| 917 | } |
| 918 | |
| 919 | /* DDR Initialization Address (DDR_INIT_EXT_ADDR) */ |
| 920 | static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr) |
| 921 | { |
| 922 | unsigned int uia = 0; /* Use initialization address */ |
| 923 | unsigned int init_ext_addr = 0; /* Initialization address */ |
| 924 | |
| 925 | ddr->ddr_init_ext_addr = (0 |
| 926 | | ((uia & 0x1) << 31) |
| 927 | | (init_ext_addr & 0xF) |
| 928 | ); |
| 929 | } |
| 930 | |
| 931 | /* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */ |
| 932 | static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr) |
| 933 | { |
| 934 | unsigned int rwt = 0; /* Read-to-write turnaround for same CS */ |
| 935 | unsigned int wrt = 0; /* Write-to-read turnaround for same CS */ |
| 936 | unsigned int rrt = 0; /* Read-to-read turnaround for same CS */ |
| 937 | unsigned int wwt = 0; /* Write-to-write turnaround for same CS */ |
| 938 | unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */ |
| 939 | |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 940 | #if defined(CONFIG_FSL_DDR3) |
| 941 | /* We need set BL/2 + 4 for BC4 or OTF */ |
| 942 | rrt = 4; /* BL/2 + 4 clocks */ |
| 943 | wwt = 4; /* BL/2 + 4 clocks */ |
| 944 | dll_lock = 1; /* tDLLK = 512 clocks from spec */ |
| 945 | #endif |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 946 | ddr->timing_cfg_4 = (0 |
| 947 | | ((rwt & 0xf) << 28) |
| 948 | | ((wrt & 0xf) << 24) |
| 949 | | ((rrt & 0xf) << 20) |
| 950 | | ((wwt & 0xf) << 16) |
| 951 | | (dll_lock & 0x3) |
| 952 | ); |
Haiying Wang | d90e040 | 2008-10-03 12:37:26 -0400 | [diff] [blame] | 953 | debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4); |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 954 | } |
| 955 | |
| 956 | /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */ |
| 957 | static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr) |
| 958 | { |
| 959 | unsigned int rodt_on = 0; /* Read to ODT on */ |
| 960 | unsigned int rodt_off = 0; /* Read to ODT off */ |
| 961 | unsigned int wodt_on = 0; /* Write to ODT on */ |
| 962 | unsigned int wodt_off = 0; /* Write to ODT off */ |
| 963 | |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 964 | #if defined(CONFIG_FSL_DDR3) |
| 965 | rodt_on = 3; /* 2 clocks */ |
| 966 | rodt_off = 4; /* 4 clocks */ |
| 967 | wodt_on = 2; /* 1 clocks */ |
| 968 | wodt_off = 4; /* 4 clocks */ |
| 969 | #endif |
| 970 | |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 971 | ddr->timing_cfg_5 = (0 |
Dave Liu | 4758d53 | 2008-11-21 16:31:29 +0800 | [diff] [blame] | 972 | | ((rodt_on & 0x1f) << 24) |
| 973 | | ((rodt_off & 0x7) << 20) |
| 974 | | ((wodt_on & 0x1f) << 12) |
| 975 | | ((wodt_off & 0x7) << 8) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 976 | ); |
Haiying Wang | d90e040 | 2008-10-03 12:37:26 -0400 | [diff] [blame] | 977 | debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5); |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 978 | } |
| 979 | |
| 980 | /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */ |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 981 | static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 982 | { |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 983 | unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */ |
| 984 | /* Normal Operation Full Calibration Time (tZQoper) */ |
| 985 | unsigned int zqoper = 0; |
| 986 | /* Normal Operation Short Calibration Time (tZQCS) */ |
| 987 | unsigned int zqcs = 0; |
| 988 | |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 989 | if (zq_en) { |
| 990 | zqinit = 9; /* 512 clocks */ |
| 991 | zqoper = 8; /* 256 clocks */ |
| 992 | zqcs = 6; /* 64 clocks */ |
| 993 | } |
| 994 | |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 995 | ddr->ddr_zq_cntl = (0 |
| 996 | | ((zq_en & 0x1) << 31) |
| 997 | | ((zqinit & 0xF) << 24) |
| 998 | | ((zqoper & 0xF) << 16) |
| 999 | | ((zqcs & 0xF) << 8) |
| 1000 | ); |
| 1001 | } |
| 1002 | |
| 1003 | /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */ |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1004 | static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, |
| 1005 | unsigned int wrlvl_en) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1006 | { |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1007 | /* |
| 1008 | * First DQS pulse rising edge after margining mode |
| 1009 | * is programmed (tWL_MRD) |
| 1010 | */ |
| 1011 | unsigned int wrlvl_mrd = 0; |
| 1012 | /* ODT delay after margining mode is programmed (tWL_ODTEN) */ |
| 1013 | unsigned int wrlvl_odten = 0; |
| 1014 | /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */ |
| 1015 | unsigned int wrlvl_dqsen = 0; |
| 1016 | /* WRLVL_SMPL: Write leveling sample time */ |
| 1017 | unsigned int wrlvl_smpl = 0; |
| 1018 | /* WRLVL_WLR: Write leveling repeition time */ |
| 1019 | unsigned int wrlvl_wlr = 0; |
| 1020 | /* WRLVL_START: Write leveling start time */ |
| 1021 | unsigned int wrlvl_start = 0; |
| 1022 | |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1023 | /* suggest enable write leveling for DDR3 due to fly-by topology */ |
| 1024 | if (wrlvl_en) { |
| 1025 | /* tWL_MRD min = 40 nCK, we set it 64 */ |
| 1026 | wrlvl_mrd = 0x6; |
| 1027 | /* tWL_ODTEN 128 */ |
| 1028 | wrlvl_odten = 0x7; |
| 1029 | /* tWL_DQSEN min = 25 nCK, we set it 32 */ |
| 1030 | wrlvl_dqsen = 0x5; |
| 1031 | /* |
| 1032 | * Write leveling sample time at least need 14 clocks |
| 1033 | * due to tWLO = 9, we set it 15 clocks |
| 1034 | */ |
| 1035 | wrlvl_smpl = 0xf; |
| 1036 | /* |
| 1037 | * Write leveling repetition time |
| 1038 | * at least tWLO + 6 clocks clocks |
| 1039 | * we set it 32 |
| 1040 | */ |
| 1041 | wrlvl_wlr = 0x5; |
| 1042 | /* |
| 1043 | * Write leveling start time |
| 1044 | * The value use for the DQS_ADJUST for the first sample |
| 1045 | * when write leveling is enabled. |
| 1046 | * we set it 1 clock delay |
| 1047 | */ |
| 1048 | wrlvl_start = 0x8; |
| 1049 | } |
| 1050 | |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1051 | ddr->ddr_wrlvl_cntl = (0 |
| 1052 | | ((wrlvl_en & 0x1) << 31) |
| 1053 | | ((wrlvl_mrd & 0x7) << 24) |
| 1054 | | ((wrlvl_odten & 0x7) << 20) |
| 1055 | | ((wrlvl_dqsen & 0x7) << 16) |
| 1056 | | ((wrlvl_smpl & 0xf) << 12) |
| 1057 | | ((wrlvl_wlr & 0x7) << 8) |
Dave Liu | 4758d53 | 2008-11-21 16:31:29 +0800 | [diff] [blame] | 1058 | | ((wrlvl_start & 0x1F) << 0) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1059 | ); |
| 1060 | } |
| 1061 | |
| 1062 | /* DDR Self Refresh Counter (DDR_SR_CNTR) */ |
Dave Liu | 2aad0ae | 2008-11-21 16:31:35 +0800 | [diff] [blame] | 1063 | static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1064 | { |
Dave Liu | 2aad0ae | 2008-11-21 16:31:35 +0800 | [diff] [blame] | 1065 | /* Self Refresh Idle Threshold */ |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1066 | ddr->ddr_sr_cntr = (sr_it & 0xF) << 16; |
| 1067 | } |
| 1068 | |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1069 | /* DDR SDRAM Register Control Word 1 (DDR_SDRAM_RCW_1) */ |
| 1070 | static void set_ddr_sdram_rcw_1(fsl_ddr_cfg_regs_t *ddr) |
| 1071 | { |
| 1072 | unsigned int rcw0 = 0; /* RCW0: Register Control Word 0 */ |
| 1073 | unsigned int rcw1 = 0; /* RCW1: Register Control Word 1 */ |
| 1074 | unsigned int rcw2 = 0; /* RCW2: Register Control Word 2 */ |
| 1075 | unsigned int rcw3 = 0; /* RCW3: Register Control Word 3 */ |
| 1076 | unsigned int rcw4 = 0; /* RCW4: Register Control Word 4 */ |
| 1077 | unsigned int rcw5 = 0; /* RCW5: Register Control Word 5 */ |
| 1078 | unsigned int rcw6 = 0; /* RCW6: Register Control Word 6 */ |
| 1079 | unsigned int rcw7 = 0; /* RCW7: Register Control Word 7 */ |
| 1080 | |
| 1081 | ddr->ddr_sdram_rcw_1 = (0 |
| 1082 | | ((rcw0 & 0xF) << 28) |
| 1083 | | ((rcw1 & 0xF) << 24) |
| 1084 | | ((rcw2 & 0xF) << 20) |
| 1085 | | ((rcw3 & 0xF) << 16) |
| 1086 | | ((rcw4 & 0xF) << 12) |
| 1087 | | ((rcw5 & 0xF) << 8) |
| 1088 | | ((rcw6 & 0xF) << 4) |
| 1089 | | ((rcw7 & 0xF) << 0) |
| 1090 | ); |
| 1091 | } |
| 1092 | |
| 1093 | /* DDR SDRAM Register Control Word 2 (DDR_SDRAM_RCW_2) */ |
| 1094 | static void set_ddr_sdram_rcw_2(fsl_ddr_cfg_regs_t *ddr) |
| 1095 | { |
| 1096 | unsigned int rcw8 = 0; /* RCW0: Register Control Word 8 */ |
| 1097 | unsigned int rcw9 = 0; /* RCW1: Register Control Word 9 */ |
| 1098 | unsigned int rcw10 = 0; /* RCW2: Register Control Word 10 */ |
| 1099 | unsigned int rcw11 = 0; /* RCW3: Register Control Word 11 */ |
| 1100 | unsigned int rcw12 = 0; /* RCW4: Register Control Word 12 */ |
| 1101 | unsigned int rcw13 = 0; /* RCW5: Register Control Word 13 */ |
| 1102 | unsigned int rcw14 = 0; /* RCW6: Register Control Word 14 */ |
| 1103 | unsigned int rcw15 = 0; /* RCW7: Register Control Word 15 */ |
| 1104 | |
| 1105 | ddr->ddr_sdram_rcw_2 = (0 |
| 1106 | | ((rcw8 & 0xF) << 28) |
| 1107 | | ((rcw9 & 0xF) << 24) |
| 1108 | | ((rcw10 & 0xF) << 20) |
| 1109 | | ((rcw11 & 0xF) << 16) |
| 1110 | | ((rcw12 & 0xF) << 12) |
| 1111 | | ((rcw13 & 0xF) << 8) |
| 1112 | | ((rcw14 & 0xF) << 4) |
| 1113 | | ((rcw15 & 0xF) << 0) |
| 1114 | ); |
| 1115 | } |
| 1116 | |
| 1117 | unsigned int |
| 1118 | check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr) |
| 1119 | { |
| 1120 | unsigned int res = 0; |
| 1121 | |
| 1122 | /* |
| 1123 | * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are |
| 1124 | * not set at the same time. |
| 1125 | */ |
| 1126 | if (ddr->ddr_sdram_cfg & 0x10000000 |
| 1127 | && ddr->ddr_sdram_cfg & 0x00008000) { |
| 1128 | printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] " |
| 1129 | " should not be set at the same time.\n"); |
| 1130 | res++; |
| 1131 | } |
| 1132 | |
| 1133 | return res; |
| 1134 | } |
| 1135 | |
| 1136 | unsigned int |
| 1137 | compute_fsl_memctl_config_regs(const memctl_options_t *popts, |
| 1138 | fsl_ddr_cfg_regs_t *ddr, |
| 1139 | const common_timing_params_t *common_dimm, |
| 1140 | const dimm_params_t *dimm_params, |
| 1141 | unsigned int dbw_cap_adj) |
| 1142 | { |
| 1143 | unsigned int i; |
| 1144 | unsigned int cas_latency; |
| 1145 | unsigned int additive_latency; |
Dave Liu | 2aad0ae | 2008-11-21 16:31:35 +0800 | [diff] [blame] | 1146 | unsigned int sr_it; |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1147 | unsigned int zq_en; |
| 1148 | unsigned int wrlvl_en; |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1149 | |
| 1150 | memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t)); |
| 1151 | |
| 1152 | if (common_dimm == NULL) { |
| 1153 | printf("Error: subset DIMM params struct null pointer\n"); |
| 1154 | return 1; |
| 1155 | } |
| 1156 | |
| 1157 | /* |
| 1158 | * Process overrides first. |
| 1159 | * |
| 1160 | * FIXME: somehow add dereated caslat to this |
| 1161 | */ |
| 1162 | cas_latency = (popts->cas_latency_override) |
| 1163 | ? popts->cas_latency_override_value |
| 1164 | : common_dimm->lowest_common_SPD_caslat; |
| 1165 | |
| 1166 | additive_latency = (popts->additive_latency_override) |
| 1167 | ? popts->additive_latency_override_value |
| 1168 | : common_dimm->additive_latency; |
| 1169 | |
Dave Liu | 2aad0ae | 2008-11-21 16:31:35 +0800 | [diff] [blame] | 1170 | sr_it = (popts->auto_self_refresh_en) |
| 1171 | ? popts->sr_it |
| 1172 | : 0; |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1173 | /* ZQ calibration */ |
| 1174 | zq_en = (popts->zq_en) ? 1 : 0; |
| 1175 | /* write leveling */ |
| 1176 | wrlvl_en = (popts->wrlvl_en) ? 1 : 0; |
Dave Liu | 2aad0ae | 2008-11-21 16:31:35 +0800 | [diff] [blame] | 1177 | |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1178 | /* Chip Select Memory Bounds (CSn_BNDS) */ |
| 1179 | for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { |
Kumar Gala | 68ef4bd | 2009-06-11 23:42:35 -0500 | [diff] [blame] | 1180 | unsigned long long ea = 0, sa = 0; |
Haiying Wang | 272b596 | 2008-10-03 12:36:39 -0400 | [diff] [blame] | 1181 | |
| 1182 | if (popts->ba_intlv_ctl && (i > 0) && |
| 1183 | ((popts->ba_intlv_ctl & 0x60) != FSL_DDR_CS2_CS3 )) { |
| 1184 | /* Don't set up boundaries for other CS |
| 1185 | * other than CS0, if bank interleaving |
| 1186 | * is enabled and not CS2+CS3 interleaved. |
| 1187 | */ |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1188 | break; |
| 1189 | } |
| 1190 | |
| 1191 | if (dimm_params[i/2].n_ranks == 0) { |
| 1192 | debug("Skipping setup of CS%u " |
| 1193 | "because n_ranks on DIMM %u is 0\n", i, i/2); |
| 1194 | continue; |
| 1195 | } |
| 1196 | if (popts->memctl_interleaving && popts->ba_intlv_ctl) { |
| 1197 | /* |
| 1198 | * This works superbank 2CS |
| 1199 | * There are 2 memory controllers configured |
| 1200 | * identically, memory is interleaved between them, |
| 1201 | * and each controller uses rank interleaving within |
| 1202 | * itself. Therefore the starting and ending address |
| 1203 | * on each controller is twice the amount present on |
| 1204 | * each controller. |
| 1205 | */ |
Haiying Wang | 272b596 | 2008-10-03 12:36:39 -0400 | [diff] [blame] | 1206 | unsigned long long rank_density |
| 1207 | = dimm_params[0].capacity; |
| 1208 | ea = (2 * (rank_density >> dbw_cap_adj)) - 1; |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1209 | } |
| 1210 | else if (!popts->memctl_interleaving && popts->ba_intlv_ctl) { |
| 1211 | /* |
| 1212 | * If memory interleaving between controllers is NOT |
| 1213 | * enabled, the starting address for each memory |
| 1214 | * controller is distinct. However, because rank |
| 1215 | * interleaving is enabled, the starting and ending |
| 1216 | * addresses of the total memory on that memory |
| 1217 | * controller needs to be programmed into its |
| 1218 | * respective CS0_BNDS. |
| 1219 | */ |
Haiying Wang | 272b596 | 2008-10-03 12:36:39 -0400 | [diff] [blame] | 1220 | unsigned long long rank_density |
| 1221 | = dimm_params[i/2].rank_density; |
| 1222 | switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { |
| 1223 | case FSL_DDR_CS0_CS1_CS2_CS3: |
| 1224 | /* CS0+CS1+CS2+CS3 interleaving, only CS0_CNDS |
| 1225 | * needs to be set. |
| 1226 | */ |
| 1227 | sa = common_dimm->base_address; |
| 1228 | ea = sa + (4 * (rank_density >> dbw_cap_adj))-1; |
| 1229 | break; |
| 1230 | case FSL_DDR_CS0_CS1_AND_CS2_CS3: |
| 1231 | /* CS0+CS1 and CS2+CS3 interleaving, CS0_CNDS |
| 1232 | * and CS2_CNDS need to be set. |
| 1233 | */ |
| 1234 | if (!(i&1)) { |
| 1235 | sa = dimm_params[i/2].base_address; |
| 1236 | ea = sa + (i * (rank_density >> |
| 1237 | dbw_cap_adj)) - 1; |
| 1238 | } |
| 1239 | break; |
| 1240 | case FSL_DDR_CS0_CS1: |
| 1241 | /* CS0+CS1 interleaving, CS0_CNDS needs |
| 1242 | * to be set |
| 1243 | */ |
| 1244 | sa = common_dimm->base_address; |
| 1245 | ea = sa + (2 * (rank_density >> dbw_cap_adj))-1; |
| 1246 | break; |
| 1247 | case FSL_DDR_CS2_CS3: |
| 1248 | /* CS2+CS3 interleaving*/ |
| 1249 | if (i == 2) { |
| 1250 | sa = dimm_params[i/2].base_address; |
| 1251 | ea = sa + (2 * (rank_density >> |
| 1252 | dbw_cap_adj)) - 1; |
| 1253 | } |
| 1254 | break; |
| 1255 | default: /* No bank(chip-select) interleaving */ |
| 1256 | break; |
| 1257 | } |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1258 | } |
| 1259 | else if (popts->memctl_interleaving && !popts->ba_intlv_ctl) { |
| 1260 | /* |
| 1261 | * Only the rank on CS0 of each memory controller may |
| 1262 | * be used if memory controller interleaving is used |
| 1263 | * without rank interleaving within each memory |
| 1264 | * controller. However, the ending address programmed |
| 1265 | * into each CS0 must be the sum of the amount of |
| 1266 | * memory in the two CS0 ranks. |
| 1267 | */ |
| 1268 | if (i == 0) { |
| 1269 | unsigned long long rank_density |
| 1270 | = dimm_params[0].rank_density; |
| 1271 | ea = (2 * (rank_density >> dbw_cap_adj)) - 1; |
| 1272 | } |
| 1273 | |
| 1274 | } |
| 1275 | else if (!popts->memctl_interleaving && !popts->ba_intlv_ctl) { |
| 1276 | /* |
| 1277 | * No rank interleaving and no memory controller |
| 1278 | * interleaving. |
| 1279 | */ |
| 1280 | unsigned long long rank_density |
| 1281 | = dimm_params[i/2].rank_density; |
| 1282 | sa = dimm_params[i/2].base_address; |
| 1283 | ea = sa + (rank_density >> dbw_cap_adj) - 1; |
| 1284 | if (i&1) { |
| 1285 | if ((dimm_params[i/2].n_ranks == 1)) { |
| 1286 | /* Odd chip select, single-rank dimm */ |
| 1287 | sa = 0; |
| 1288 | ea = 0; |
| 1289 | } else { |
| 1290 | /* Odd chip select, dual-rank DIMM */ |
| 1291 | sa += rank_density >> dbw_cap_adj; |
| 1292 | ea += rank_density >> dbw_cap_adj; |
| 1293 | } |
| 1294 | } |
| 1295 | } |
| 1296 | |
| 1297 | sa >>= 24; |
| 1298 | ea >>= 24; |
| 1299 | |
| 1300 | ddr->cs[i].bnds = (0 |
| 1301 | | ((sa & 0xFFF) << 16) /* starting address MSB */ |
| 1302 | | ((ea & 0xFFF) << 0) /* ending address MSB */ |
| 1303 | ); |
| 1304 | |
Haiying Wang | d90e040 | 2008-10-03 12:37:26 -0400 | [diff] [blame] | 1305 | debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds); |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1306 | set_csn_config(i, ddr, popts, dimm_params); |
| 1307 | set_csn_config_2(i, ddr); |
| 1308 | } |
| 1309 | |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1310 | #if !defined(CONFIG_FSL_DDR1) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1311 | set_timing_cfg_0(ddr); |
| 1312 | #endif |
| 1313 | |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1314 | set_timing_cfg_3(ddr, common_dimm, cas_latency); |
| 1315 | set_timing_cfg_1(ddr, popts, common_dimm, cas_latency); |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1316 | set_timing_cfg_2(ddr, popts, common_dimm, |
| 1317 | cas_latency, additive_latency); |
| 1318 | |
| 1319 | set_ddr_sdram_cfg(ddr, popts, common_dimm); |
| 1320 | |
| 1321 | set_ddr_sdram_cfg_2(ddr, popts); |
| 1322 | set_ddr_sdram_mode(ddr, popts, common_dimm, |
| 1323 | cas_latency, additive_latency); |
| 1324 | set_ddr_sdram_mode_2(ddr); |
| 1325 | set_ddr_sdram_interval(ddr, popts, common_dimm); |
| 1326 | set_ddr_data_init(ddr); |
| 1327 | set_ddr_sdram_clk_cntl(ddr, popts); |
| 1328 | set_ddr_init_addr(ddr); |
| 1329 | set_ddr_init_ext_addr(ddr); |
| 1330 | set_timing_cfg_4(ddr); |
| 1331 | set_timing_cfg_5(ddr); |
| 1332 | |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 1333 | set_ddr_zq_cntl(ddr, zq_en); |
| 1334 | set_ddr_wrlvl_cntl(ddr, wrlvl_en); |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1335 | |
Dave Liu | 2aad0ae | 2008-11-21 16:31:35 +0800 | [diff] [blame] | 1336 | set_ddr_sr_cntr(ddr, sr_it); |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1337 | |
| 1338 | set_ddr_sdram_rcw_1(ddr); |
| 1339 | set_ddr_sdram_rcw_2(ddr); |
| 1340 | |
| 1341 | return check_fsl_memctl_config_regs(ddr); |
| 1342 | } |