| commit | 27f83be91d6b86415451c87228cc753e97a35424 | [log] [tgz] |
|---|---|---|
| author | York Sun <yorksun@freescale.com> | Thu Feb 10 10:13:10 2011 -0800 |
| committer | Kumar Gala <galak@kernel.crashing.org> | Thu Feb 10 23:40:02 2011 -0600 |
| tree | dedbbaa272786a4f7c87971b5f88864452754892 | |
| parent | 1feac1ef51bac26fa4c10e17f4f3aa8f4e6912ec [diff] |
powerpc/8xxx: Add additional cycle to write-to-read turnaound for DDR3 When DDR data rate is higher than 1200MT/s or controller interleaving is enabled, additional cycle for write-to-read turnaround is needed to satisfy dynamic ODT timing. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>