blob: c0ffeb3333fc96bd3c8361ab27964e38b09f0eb4 [file] [log] [blame]
Ian Campbelld8e69e02014-10-24 21:20:44 +01001if ARCH_SUNXI
2
Siva Durga Prasad Paladugu809438d2016-07-29 15:31:47 +05303config IDENT_STRING
4 default " Allwinner Technology"
5
Simon Glasse304a5e2016-10-17 20:12:36 -06006config PRE_CONSOLE_BUFFER
7 default y
8
Simon Glass0bdfc3e2016-09-12 23:18:39 -06009config SPL_GPIO_SUPPORT
10 default y
11
Simon Glassf2a89462016-09-12 23:18:41 -060012config SPL_LIBCOMMON_SUPPORT
13 default y
14
Simon Glassf6de2572016-09-12 23:18:42 -060015config SPL_LIBDISK_SUPPORT
16 default y
17
Simon Glassb16c92c2016-09-12 23:18:43 -060018config SPL_LIBGENERIC_SUPPORT
19 default y
20
Simon Glassbd58f1d2016-09-12 23:18:44 -060021config SPL_MMC_SUPPORT
22 default y
23
Simon Glass0d7c7e02016-09-12 23:18:54 -060024config SPL_POWER_SUPPORT
25 default y
26
Simon Glasse076d6f2016-09-12 23:18:56 -060027config SPL_SERIAL_SUPPORT
28 default y
29
Hans de Goedef07872b2015-04-06 20:33:34 +020030# Note only one of these may be selected at a time! But hidden choices are
31# not supported by Kconfig
32config SUNXI_GEN_SUN4I
33 bool
34 ---help---
35 Select this for sunxi SoCs which have resets and clocks set up
36 as the original A10 (mach-sun4i).
37
38config SUNXI_GEN_SUN6I
39 bool
40 ---help---
41 Select this for sunxi SoCs which have sun6i like periphery, like
42 separate ahb reset control registers, custom pmic bus, new style
43 watchdog, etc.
44
45
Ian Campbelld8e69e02014-10-24 21:20:44 +010046choice
47 prompt "Sunxi SoC Variant"
Hans de Goedeb05a6482016-06-12 11:57:07 +020048 optional
Ian Campbelld8e69e02014-10-24 21:20:44 +010049
Ian Campbell4a24a1c2014-10-24 21:20:45 +010050config MACH_SUN4I
Ian Campbelld8e69e02014-10-24 21:20:44 +010051 bool "sun4i (Allwinner A10)"
52 select CPU_V7
Hans de Goedef07872b2015-04-06 20:33:34 +020053 select SUNXI_GEN_SUN4I
Ian Campbelld8e69e02014-10-24 21:20:44 +010054 select SUPPORT_SPL
55
Ian Campbell4a24a1c2014-10-24 21:20:45 +010056config MACH_SUN5I
Ian Campbelld8e69e02014-10-24 21:20:44 +010057 bool "sun5i (Allwinner A13)"
58 select CPU_V7
Hans de Goedef07872b2015-04-06 20:33:34 +020059 select SUNXI_GEN_SUN4I
Ian Campbelld8e69e02014-10-24 21:20:44 +010060 select SUPPORT_SPL
61
Ian Campbell4a24a1c2014-10-24 21:20:45 +010062config MACH_SUN6I
Ian Campbelld8e69e02014-10-24 21:20:44 +010063 bool "sun6i (Allwinner A31)"
64 select CPU_V7
Chen-Yu Tsaif31017c2015-05-28 21:25:32 +080065 select CPU_V7_HAS_NONSEC
66 select CPU_V7_HAS_VIRT
Masahiro Yamadad5415b22016-08-30 16:22:22 +090067 select ARCH_SUPPORT_PSCI
Hans de Goedef07872b2015-04-06 20:33:34 +020068 select SUNXI_GEN_SUN6I
Hans de Goedea5403b92014-10-25 20:18:10 +020069 select SUPPORT_SPL
Chen-Yu Tsaif31017c2015-05-28 21:25:32 +080070 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbelld8e69e02014-10-24 21:20:44 +010071
Ian Campbell4a24a1c2014-10-24 21:20:45 +010072config MACH_SUN7I
Ian Campbelld8e69e02014-10-24 21:20:44 +010073 bool "sun7i (Allwinner A20)"
74 select CPU_V7
Hans de Goede85437352014-11-14 09:34:30 +010075 select CPU_V7_HAS_NONSEC
76 select CPU_V7_HAS_VIRT
Masahiro Yamadad5415b22016-08-30 16:22:22 +090077 select ARCH_SUPPORT_PSCI
Hans de Goedef07872b2015-04-06 20:33:34 +020078 select SUNXI_GEN_SUN4I
Ian Campbelld8e69e02014-10-24 21:20:44 +010079 select SUPPORT_SPL
Hans de Goedea5636382014-10-24 20:12:04 +020080 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbelld8e69e02014-10-24 21:20:44 +010081
Hans de Goedef055ed62015-04-06 20:55:39 +020082config MACH_SUN8I_A23
Ian Campbelld8e69e02014-10-24 21:20:44 +010083 bool "sun8i (Allwinner A23)"
84 select CPU_V7
Chen-Yu Tsai5acec7c2015-05-28 21:25:34 +080085 select CPU_V7_HAS_NONSEC
86 select CPU_V7_HAS_VIRT
Masahiro Yamadad5415b22016-08-30 16:22:22 +090087 select ARCH_SUPPORT_PSCI
Hans de Goedef07872b2015-04-06 20:33:34 +020088 select SUNXI_GEN_SUN6I
Hans de Goede966d2392014-12-07 14:34:27 +010089 select SUPPORT_SPL
Chen-Yu Tsai5acec7c2015-05-28 21:25:34 +080090 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbelld8e69e02014-10-24 21:20:44 +010091
Vishnu Patekar3702f142015-03-01 23:47:48 +053092config MACH_SUN8I_A33
93 bool "sun8i (Allwinner A33)"
94 select CPU_V7
Chen-Yu Tsai5acec7c2015-05-28 21:25:34 +080095 select CPU_V7_HAS_NONSEC
96 select CPU_V7_HAS_VIRT
Masahiro Yamadad5415b22016-08-30 16:22:22 +090097 select ARCH_SUPPORT_PSCI
Vishnu Patekar3702f142015-03-01 23:47:48 +053098 select SUNXI_GEN_SUN6I
99 select SUPPORT_SPL
Chen-Yu Tsai5acec7c2015-05-28 21:25:34 +0800100 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Vishnu Patekar3702f142015-03-01 23:47:48 +0530101
Chen-Yu Tsai1fcaea02016-05-02 10:28:07 +0800102config MACH_SUN8I_A83T
103 bool "sun8i (Allwinner A83T)"
104 select CPU_V7
105 select SUNXI_GEN_SUN6I
106 select SUPPORT_SPL
107
Jens Kuskef9770722015-11-17 15:12:58 +0100108config MACH_SUN8I_H3
109 bool "sun8i (Allwinner H3)"
110 select CPU_V7
Chen-Yu Tsaiaa9ab0e2016-01-06 15:13:09 +0800111 select CPU_V7_HAS_NONSEC
112 select CPU_V7_HAS_VIRT
Masahiro Yamadad5415b22016-08-30 16:22:22 +0900113 select ARCH_SUPPORT_PSCI
Jens Kuskef9770722015-11-17 15:12:58 +0100114 select SUNXI_GEN_SUN6I
Jens Kuske53f018e2015-11-17 15:12:59 +0100115 select SUPPORT_SPL
Chen-Yu Tsaiaa9ab0e2016-01-06 15:13:09 +0800116 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Jens Kuskef9770722015-11-17 15:12:58 +0100117
Hans de Goede7bfe2bb2015-01-13 19:25:06 +0100118config MACH_SUN9I
119 bool "sun9i (Allwinner A80)"
120 select CPU_V7
121 select SUNXI_GEN_SUN6I
122
Chen-Yu Tsai1fcaea02016-05-02 10:28:07 +0800123config MACH_SUN50I
124 bool "sun50i (Allwinner A64)"
125 select ARM64
126 select SUNXI_GEN_SUN6I
127
Ian Campbelld8e69e02014-10-24 21:20:44 +0100128endchoice
Maxime Ripard2c519412014-10-03 20:16:29 +0800129
Hans de Goedef055ed62015-04-06 20:55:39 +0200130# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
131config MACH_SUN8I
132 bool
vishnupatekarcdf1e482015-11-29 01:07:19 +0800133 default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3 || MACH_SUN8I_A83T
Hans de Goedef055ed62015-04-06 20:55:39 +0200134
Vishnu Patekarc49936f2016-01-12 01:20:58 +0800135config DRAM_TYPE
136 int "sunxi dram type"
137 depends on MACH_SUN8I_A83T
138 default 3
139 ---help---
140 Set the dram type, 3: DDR3, 7: LPDDR3
Hans de Goedef055ed62015-04-06 20:55:39 +0200141
Hans de Goede3aeaa282014-11-15 19:46:39 +0100142config DRAM_CLK
Hans de Goede59d9fc72015-01-17 14:24:55 +0100143 int "sunxi dram clock speed"
144 default 312 if MACH_SUN6I || MACH_SUN8I
145 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
Hans de Goede3aeaa282014-11-15 19:46:39 +0100146 ---help---
147 Set the dram clock speed, valid range 240 - 480, must be a multiple
Hans de Goede06ddc452015-01-25 11:29:27 +0100148 of 24.
Hans de Goede3aeaa282014-11-15 19:46:39 +0100149
Siarhei Siamashka47359bb2015-02-01 00:27:06 +0200150if MACH_SUN5I || MACH_SUN7I
151config DRAM_MBUS_CLK
152 int "sunxi mbus clock speed"
153 default 300
154 ---help---
155 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
156
157endif
158
Hans de Goede3aeaa282014-11-15 19:46:39 +0100159config DRAM_ZQ
Hans de Goede59d9fc72015-01-17 14:24:55 +0100160 int "sunxi dram zq value"
161 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
162 default 127 if MACH_SUN7I
Hans de Goede3aeaa282014-11-15 19:46:39 +0100163 ---help---
Hans de Goede06ddc452015-01-25 11:29:27 +0100164 Set the dram zq value.
Hans de Goede3aeaa282014-11-15 19:46:39 +0100165
Hans de Goedeffdc05c2015-05-13 15:00:46 +0200166config DRAM_ODT_EN
167 bool "sunxi dram odt enable"
168 default n if !MACH_SUN8I_A23
169 default y if MACH_SUN8I_A23
170 ---help---
171 Select this to enable dram odt (on die termination).
172
Hans de Goede59d9fc72015-01-17 14:24:55 +0100173if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
174config DRAM_EMR1
175 int "sunxi dram emr1 value"
176 default 0 if MACH_SUN4I
177 default 4 if MACH_SUN5I || MACH_SUN7I
178 ---help---
Hans de Goede06ddc452015-01-25 11:29:27 +0100179 Set the dram controller emr1 value.
Siarhei Siamashka9900db12015-02-01 00:27:05 +0200180
Siarhei Siamashka47359bb2015-02-01 00:27:06 +0200181config DRAM_TPR3
182 hex "sunxi dram tpr3 value"
183 default 0
184 ---help---
185 Set the dram controller tpr3 parameter. This parameter configures
186 the delay on the command lane and also phase shifts, which are
187 applied for sampling incoming read data. The default value 0
188 means that no phase/delay adjustments are necessary. Properly
189 configuring this parameter increases reliability at high DRAM
190 clock speeds.
191
192config DRAM_DQS_GATING_DELAY
193 hex "sunxi dram dqs_gating_delay value"
194 default 0
195 ---help---
196 Set the dram controller dqs_gating_delay parmeter. Each byte
197 encodes the DQS gating delay for each byte lane. The delay
198 granularity is 1/4 cycle. For example, the value 0x05060606
199 means that the delay is 5 quarter-cycles for one lane (1.25
200 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
201 The default value 0 means autodetection. The results of hardware
202 autodetection are not very reliable and depend on the chip
203 temperature (sometimes producing different results on cold start
204 and warm reboot). But the accuracy of hardware autodetection
205 is usually good enough, unless running at really high DRAM
206 clocks speeds (up to 600MHz). If unsure, keep as 0.
207
Siarhei Siamashka9900db12015-02-01 00:27:05 +0200208choice
209 prompt "sunxi dram timings"
210 default DRAM_TIMINGS_VENDOR_MAGIC
211 ---help---
212 Select the timings of the DDR3 chips.
213
214config DRAM_TIMINGS_VENDOR_MAGIC
215 bool "Magic vendor timings from Android"
216 ---help---
217 The same DRAM timings as in the Allwinner boot0 bootloader.
218
219config DRAM_TIMINGS_DDR3_1066F_1333H
220 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
221 ---help---
222 Use the timings of the standard JEDEC DDR3-1066F speed bin for
223 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
224 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
225 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
226 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
227 that down binning to DDR3-1066F is supported (because DDR3-1066F
228 uses a bit faster timings than DDR3-1333H).
229
230config DRAM_TIMINGS_DDR3_800E_1066G_1333J
231 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
232 ---help---
233 Use the timings of the slowest possible JEDEC speed bin for the
234 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
235 DDR3-800E, DDR3-1066G or DDR3-1333J.
236
237endchoice
238
Hans de Goede3aeaa282014-11-15 19:46:39 +0100239endif
240
Hans de Goedeffdc05c2015-05-13 15:00:46 +0200241if MACH_SUN8I_A23
242config DRAM_ODT_CORRECTION
243 int "sunxi dram odt correction value"
244 default 0
245 ---help---
246 Set the dram odt correction value (range -255 - 255). In allwinner
247 fex files, this option is found in bits 8-15 of the u32 odt_en variable
248 in the [dram] section. When bit 31 of the odt_en variable is set
249 then the correction is negative. Usually the value for this is 0.
250endif
251
Iain Paton630df142015-03-28 10:26:38 +0000252config SYS_CLK_FREQ
Siarhei Siamashka26c50fb2016-03-29 17:29:10 +0200253 default 816000000 if MACH_SUN50I
Iain Paton630df142015-03-28 10:26:38 +0000254 default 912000000 if MACH_SUN7I
255 default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
256
Maxime Ripard2c519412014-10-03 20:16:29 +0800257config SYS_CONFIG_NAME
Ian Campbell4a24a1c2014-10-24 21:20:45 +0100258 default "sun4i" if MACH_SUN4I
259 default "sun5i" if MACH_SUN5I
260 default "sun6i" if MACH_SUN6I
261 default "sun7i" if MACH_SUN7I
262 default "sun8i" if MACH_SUN8I
Hans de Goede7bfe2bb2015-01-13 19:25:06 +0100263 default "sun9i" if MACH_SUN9I
Siarhei Siamashka26c50fb2016-03-29 17:29:10 +0200264 default "sun50i" if MACH_SUN50I
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900265
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900266config SYS_BOARD
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900267 default "sunxi"
268
269config SYS_SOC
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900270 default "sunxi"
271
Siarhei Siamashka121161f2014-12-25 02:34:47 +0200272config UART0_PORT_F
273 bool "UART0 on MicroSD breakout board"
Siarhei Siamashka121161f2014-12-25 02:34:47 +0200274 default n
275 ---help---
276 Repurpose the SD card slot for getting access to the UART0 serial
277 console. Primarily useful only for low level u-boot debugging on
278 tablets, where normal UART0 is difficult to access and requires
279 device disassembly and/or soldering. As the SD card can't be used
280 at the same time, the system can be only booted in the FEL mode.
281 Only enable this if you really know what you are doing.
282
Hans de Goede05e5bcb2014-10-22 14:56:36 +0200283config OLD_SUNXI_KERNEL_COMPAT
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900284 bool "Enable workarounds for booting old kernels"
Hans de Goede05e5bcb2014-10-22 14:56:36 +0200285 default n
286 ---help---
287 Set this to enable various workarounds for old kernels, this results in
288 sub-optimal settings for newer kernels, only enable if needed.
289
Maxime Riparde0c7aa42015-10-15 22:04:07 +0200290config MMC
291 depends on !UART0_PORT_F
292 default y if ARCH_SUNXI
293
Hans de Goede7412ef82014-10-02 20:29:26 +0200294config MMC0_CD_PIN
295 string "Card detect pin for mmc0"
Chen-Yu Tsai36741482016-05-02 10:28:08 +0800296 default "PF6" if MACH_SUN8I_A83T || MACH_SUN8I_H3 || MACH_SUN50I
Hans de Goede7412ef82014-10-02 20:29:26 +0200297 default ""
298 ---help---
299 Set the card detect pin for mmc0, leave empty to not use cd. This
300 takes a string in the format understood by sunxi_name_to_gpio, e.g.
301 PH1 for pin 1 of port H.
302
303config MMC1_CD_PIN
304 string "Card detect pin for mmc1"
305 default ""
306 ---help---
307 See MMC0_CD_PIN help text.
308
309config MMC2_CD_PIN
310 string "Card detect pin for mmc2"
311 default ""
312 ---help---
313 See MMC0_CD_PIN help text.
314
315config MMC3_CD_PIN
316 string "Card detect pin for mmc3"
317 default ""
318 ---help---
319 See MMC0_CD_PIN help text.
320
Paul Kocialkowskid390d8c2015-03-22 18:12:23 +0100321config MMC1_PINS
322 string "Pins for mmc1"
323 default ""
324 ---help---
325 Set the pins used for mmc1, when applicable. This takes a string in the
326 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
327
328config MMC2_PINS
329 string "Pins for mmc2"
330 default ""
331 ---help---
332 See MMC1_PINS help text.
333
334config MMC3_PINS
335 string "Pins for mmc3"
336 default ""
337 ---help---
338 See MMC1_PINS help text.
339
Hans de Goedeaf593e42014-10-02 20:43:50 +0200340config MMC_SUNXI_SLOT_EXTRA
341 int "mmc extra slot number"
342 default -1
343 ---help---
344 sunxi builds always enable mmc0, some boards also have a second sdcard
345 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
346 support for this.
347
Hans de Goede99c9fb02016-04-01 22:39:26 +0200348config INITIAL_USB_SCAN_DELAY
349 int "delay initial usb scan by x ms to allow builtin devices to init"
350 default 0
351 ---help---
352 Some boards have on board usb devices which need longer than the
353 USB spec's 1 second to connect from board powerup. Set this config
354 option to a non 0 value to add an extra delay before the first usb
355 bus scan.
356
Hans de Goedee7b852a2015-01-07 15:26:06 +0100357config USB0_VBUS_PIN
358 string "Vbus enable pin for usb0 (otg)"
359 default ""
360 ---help---
361 Set the Vbus enable pin for usb0 (otg). This takes a string in the
362 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
363
Hans de Goedeeaa0d702015-02-16 22:13:43 +0100364config USB0_VBUS_DET
365 string "Vbus detect pin for usb0 (otg)"
Hans de Goedeeaa0d702015-02-16 22:13:43 +0100366 default ""
367 ---help---
368 Set the Vbus detect pin for usb0 (otg). This takes a string in the
369 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
370
Hans de Goedeaadd97f2015-06-14 17:29:53 +0200371config USB0_ID_DET
372 string "ID detect pin for usb0 (otg)"
373 default ""
374 ---help---
375 Set the ID detect pin for usb0 (otg). This takes a string in the
376 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
377
Hans de Goedeaf4273b2014-11-07 16:09:00 +0100378config USB1_VBUS_PIN
379 string "Vbus enable pin for usb1 (ehci0)"
380 default "PH6" if MACH_SUN4I || MACH_SUN7I
Hans de Goedeb5ab8ce2014-11-07 14:51:12 +0100381 default "PH27" if MACH_SUN6I
Hans de Goedeaf4273b2014-11-07 16:09:00 +0100382 ---help---
383 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
384 a string in the format understood by sunxi_name_to_gpio, e.g.
385 PH1 for pin 1 of port H.
386
387config USB2_VBUS_PIN
388 string "Vbus enable pin for usb2 (ehci1)"
389 default "PH3" if MACH_SUN4I || MACH_SUN7I
Hans de Goedeb5ab8ce2014-11-07 14:51:12 +0100390 default "PH24" if MACH_SUN6I
Hans de Goedeaf4273b2014-11-07 16:09:00 +0100391 ---help---
392 See USB1_VBUS_PIN help text.
393
Hans de Goedea60c3fc2016-03-18 08:42:01 +0100394config USB3_VBUS_PIN
395 string "Vbus enable pin for usb3 (ehci2)"
396 default ""
397 ---help---
398 See USB1_VBUS_PIN help text.
399
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200400config I2C0_ENABLE
401 bool "Enable I2C/TWI controller 0"
402 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
403 default n if MACH_SUN6I || MACH_SUN8I
Hans de Goede2c526402016-05-15 13:51:58 +0200404 select CMD_I2C
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200405 ---help---
406 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
407 its clock and setting up the bus. This is especially useful on devices
408 with slaves connected to the bus or with pins exposed through e.g. an
409 expansion port/header.
410
411config I2C1_ENABLE
412 bool "Enable I2C/TWI controller 1"
413 default n
Hans de Goede2c526402016-05-15 13:51:58 +0200414 select CMD_I2C
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200415 ---help---
416 See I2C0_ENABLE help text.
417
418config I2C2_ENABLE
419 bool "Enable I2C/TWI controller 2"
420 default n
Hans de Goede2c526402016-05-15 13:51:58 +0200421 select CMD_I2C
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200422 ---help---
423 See I2C0_ENABLE help text.
424
425if MACH_SUN6I || MACH_SUN7I
426config I2C3_ENABLE
427 bool "Enable I2C/TWI controller 3"
428 default n
Hans de Goede2c526402016-05-15 13:51:58 +0200429 select CMD_I2C
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200430 ---help---
431 See I2C0_ENABLE help text.
432endif
433
Jelle van der Waa3f3a3092016-02-23 18:47:19 +0100434if SUNXI_GEN_SUN6I
Jelle van der Waa8d3d7c12016-01-14 14:06:26 +0100435config R_I2C_ENABLE
436 bool "Enable the PRCM I2C/TWI controller"
Jelle van der Waa3f3a3092016-02-23 18:47:19 +0100437 # This is used for the pmic on H3
438 default y if SY8106A_POWER
Hans de Goede2c526402016-05-15 13:51:58 +0200439 select CMD_I2C
Jelle van der Waa8d3d7c12016-01-14 14:06:26 +0100440 ---help---
441 Set this to y to enable the I2C controller which is part of the PRCM.
Jelle van der Waa3f3a3092016-02-23 18:47:19 +0100442endif
Jelle van der Waa8d3d7c12016-01-14 14:06:26 +0100443
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200444if MACH_SUN7I
445config I2C4_ENABLE
446 bool "Enable I2C/TWI controller 4"
447 default n
Hans de Goede2c526402016-05-15 13:51:58 +0200448 select CMD_I2C
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200449 ---help---
450 See I2C0_ENABLE help text.
451endif
452
Hans de Goede3ae1d132015-04-25 17:25:14 +0200453config AXP_GPIO
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900454 bool "Enable support for gpio-s on axp PMICs"
Hans de Goede3ae1d132015-04-25 17:25:14 +0200455 default n
456 ---help---
457 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
458
Luc Verhaegenb01df1e2014-08-13 07:55:06 +0200459config VIDEO
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900460 bool "Enable graphical uboot console on HDMI, LCD or VGA"
Andre Przywara8f977272016-09-05 01:32:40 +0100461 depends on !MACH_SUN8I_A83T && !MACH_SUN8I_H3 && !MACH_SUN9I && !MACH_SUN50I
Luc Verhaegenb01df1e2014-08-13 07:55:06 +0200462 default y
463 ---help---
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100464 Say Y here to add support for using a cfb console on the HDMI, LCD
465 or VGA output found on most sunxi devices. See doc/README.video for
466 info on how to select the video output and mode.
467
Hans de Goedee9544592014-12-23 23:04:35 +0100468config VIDEO_HDMI
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900469 bool "HDMI output support"
Hans de Goedee9544592014-12-23 23:04:35 +0100470 depends on VIDEO && !MACH_SUN8I
471 default y
472 ---help---
473 Say Y here to add support for outputting video over HDMI.
474
Hans de Goede260f5202014-12-25 13:58:06 +0100475config VIDEO_VGA
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900476 bool "VGA output support"
Hans de Goede260f5202014-12-25 13:58:06 +0100477 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
478 default n
479 ---help---
480 Say Y here to add support for outputting video over VGA.
481
Hans de Goedeac1633c2014-12-24 12:17:07 +0100482config VIDEO_VGA_VIA_LCD
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900483 bool "VGA via LCD controller support"
Chen-Yu Tsai39ca4c12015-01-12 18:02:10 +0800484 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
Hans de Goedeac1633c2014-12-24 12:17:07 +0100485 default n
486 ---help---
487 Say Y here to add support for external DACs connected to the parallel
488 LCD interface driving a VGA connector, such as found on the
489 Olimex A13 boards.
490
Hans de Goede18366f72015-01-25 15:33:07 +0100491config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900492 bool "Force sync active high for VGA via LCD controller support"
Hans de Goede18366f72015-01-25 15:33:07 +0100493 depends on VIDEO_VGA_VIA_LCD
494 default n
495 ---help---
496 Say Y here if you've a board which uses opendrain drivers for the vga
497 hsync and vsync signals. Opendrain drivers cannot generate steep enough
498 positive edges for a stable video output, so on boards with opendrain
499 drivers the sync signals must always be active high.
500
Chen-Yu Tsai9ed19522015-01-12 18:02:11 +0800501config VIDEO_VGA_EXTERNAL_DAC_EN
502 string "LCD panel power enable pin"
503 depends on VIDEO_VGA_VIA_LCD
504 default ""
505 ---help---
506 Set the enable pin for the external VGA DAC. This takes a string in the
507 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
508
Hans de Goedec06e00e2015-08-03 19:20:26 +0200509config VIDEO_COMPOSITE
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900510 bool "Composite video output support"
Hans de Goedec06e00e2015-08-03 19:20:26 +0200511 depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
512 default n
513 ---help---
514 Say Y here to add support for outputting composite video.
515
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100516config VIDEO_LCD_MODE
517 string "LCD panel timing details"
518 depends on VIDEO
519 default ""
520 ---help---
521 LCD panel timing details string, leave empty if there is no LCD panel.
522 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
523 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
Hans de Goede924c8932015-08-16 11:23:42 +0200524 Also see: http://linux-sunxi.org/LCD
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100525
Hans de Goede481b6642015-01-13 13:21:46 +0100526config VIDEO_LCD_DCLK_PHASE
527 int "LCD panel display clock phase"
528 depends on VIDEO
529 default 1
530 ---help---
531 Select LCD panel display clock phase shift, range 0-3.
532
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100533config VIDEO_LCD_POWER
534 string "LCD panel power enable pin"
535 depends on VIDEO
536 default ""
537 ---help---
538 Set the power enable pin for the LCD panel. This takes a string in the
539 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
540
Hans de Goedece9e3322015-02-16 17:26:41 +0100541config VIDEO_LCD_RESET
542 string "LCD panel reset pin"
543 depends on VIDEO
544 default ""
545 ---help---
546 Set the reset pin for the LCD panel. This takes a string in the format
547 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
548
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100549config VIDEO_LCD_BL_EN
550 string "LCD panel backlight enable pin"
551 depends on VIDEO
552 default ""
553 ---help---
554 Set the backlight enable pin for the LCD panel. This takes a string in the
555 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
556 port H.
557
558config VIDEO_LCD_BL_PWM
559 string "LCD panel backlight pwm pin"
560 depends on VIDEO
561 default ""
562 ---help---
563 Set the backlight pwm pin for the LCD panel. This takes a string in the
564 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
Luc Verhaegenb01df1e2014-08-13 07:55:06 +0200565
Hans de Goede2d5d3022015-01-22 21:02:42 +0100566config VIDEO_LCD_BL_PWM_ACTIVE_LOW
567 bool "LCD panel backlight pwm is inverted"
568 depends on VIDEO
569 default y
570 ---help---
571 Set this if the backlight pwm output is active low.
572
Hans de Goedea5b4cfe2015-02-16 17:23:25 +0100573config VIDEO_LCD_PANEL_I2C
574 bool "LCD panel needs to be configured via i2c"
575 depends on VIDEO
Hans de Goede6de9f762015-03-07 12:00:02 +0100576 default n
Hans de Goede2c526402016-05-15 13:51:58 +0200577 select CMD_I2C
Hans de Goedea5b4cfe2015-02-16 17:23:25 +0100578 ---help---
579 Say y here if the LCD panel needs to be configured via i2c. This
580 will add a bitbang i2c controller using gpios to talk to the LCD.
581
582config VIDEO_LCD_PANEL_I2C_SDA
583 string "LCD panel i2c interface SDA pin"
584 depends on VIDEO_LCD_PANEL_I2C
585 default "PG12"
586 ---help---
587 Set the SDA pin for the LCD i2c interface. This takes a string in the
588 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
589
590config VIDEO_LCD_PANEL_I2C_SCL
591 string "LCD panel i2c interface SCL pin"
592 depends on VIDEO_LCD_PANEL_I2C
593 default "PG10"
594 ---help---
595 Set the SCL pin for the LCD i2c interface. This takes a string in the
596 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
597
Hans de Goede797a0f52015-01-01 22:04:34 +0100598
599# Note only one of these may be selected at a time! But hidden choices are
600# not supported by Kconfig
601config VIDEO_LCD_IF_PARALLEL
602 bool
603
604config VIDEO_LCD_IF_LVDS
605 bool
606
607
608choice
609 prompt "LCD panel support"
610 depends on VIDEO
611 ---help---
612 Select which type of LCD panel to support.
613
614config VIDEO_LCD_PANEL_PARALLEL
615 bool "Generic parallel interface LCD panel"
616 select VIDEO_LCD_IF_PARALLEL
617
618config VIDEO_LCD_PANEL_LVDS
619 bool "Generic lvds interface LCD panel"
620 select VIDEO_LCD_IF_LVDS
621
Siarhei Siamashkac02f0522015-01-19 05:23:33 +0200622config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
623 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
624 select VIDEO_LCD_SSD2828
625 select VIDEO_LCD_IF_PARALLEL
626 ---help---
Hans de Goede91f1b822015-08-08 16:13:53 +0200627 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
628
629config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
630 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
631 select VIDEO_LCD_ANX9804
632 select VIDEO_LCD_IF_PARALLEL
633 select VIDEO_LCD_PANEL_I2C
634 ---help---
635 Select this for eDP LCD panels with 4 lanes running at 1.62G,
636 connected via an ANX9804 bridge chip.
Siarhei Siamashkac02f0522015-01-19 05:23:33 +0200637
Hans de Goede743fb9552015-01-20 09:23:36 +0100638config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
639 bool "Hitachi tx18d42vm LCD panel"
640 select VIDEO_LCD_HITACHI_TX18D42VM
641 select VIDEO_LCD_IF_LVDS
642 ---help---
643 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
644
Hans de Goede613dade2015-02-16 17:49:47 +0100645config VIDEO_LCD_TL059WV5C0
646 bool "tl059wv5c0 LCD panel"
647 select VIDEO_LCD_PANEL_I2C
648 select VIDEO_LCD_IF_PARALLEL
649 ---help---
650 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
651 Aigo M60/M608/M606 tablets.
652
Hans de Goede797a0f52015-01-01 22:04:34 +0100653endchoice
654
655
Hans de Goedebf880fe2015-01-25 12:10:48 +0100656config GMAC_TX_DELAY
657 int "GMAC Transmit Clock Delay Chain"
658 default 0
659 ---help---
660 Set the GMAC Transmit Clock Delay Chain value.
661
Hans de Goede66ab79d2015-09-13 13:02:48 +0200662config SPL_STACK_R_ADDR
Siarhei Siamashka26c50fb2016-03-29 17:29:10 +0200663 default 0x4fe00000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I || MACH_SUN50I
Hans de Goede66ab79d2015-09-13 13:02:48 +0200664 default 0x2fe00000 if MACH_SUN9I
665
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900666endif