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Simon Glass4cc43bf2021-08-18 21:40:25 -06001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Devicetree file for running sandbox tests
4 *
5 * This includes lots of extra devices used by various tests.
6 *
7 * Note that SPL use the main sandbox.dts file
8 */
9
Simon Glassb2c1cac2014-02-26 15:59:21 -070010/dts-v1/;
11
Eddie James1a55a7a2023-10-24 10:43:51 -050012#include <config.h>
Patrick Delaunay23aee612020-01-13 11:35:13 +010013#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/gpio/sandbox-gpio.h>
Marek Szyprowskiad398592021-02-18 11:33:18 +010015#include <dt-bindings/input/input.h>
Sean Anderson3438e3b2020-09-14 11:01:57 -040016#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +053017#include <dt-bindings/mux/mux.h>
Patrick Delaunay23aee612020-01-13 11:35:13 +010018
Simon Glassb2c1cac2014-02-26 15:59:21 -070019/ {
20 model = "sandbox";
21 compatible = "sandbox";
22 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -060023 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070024
Simon Glassfef72b72014-07-23 06:55:03 -060025 aliases {
26 console = &uart0;
Michael Walle7efcdfd2021-02-25 16:51:11 +010027 ethernet0 = "/eth@10002000";
28 ethernet2 = &swp_0;
29 ethernet3 = &eth_3;
30 ethernet4 = &dsa_eth0;
31 ethernet5 = &eth_5;
Sean Anderson67d93a42022-05-05 13:11:30 -040032 ethernet6 = "/eth@10004000";
33 ethernet7 = &swp_1;
34 ethernet8 = &phy_eth0;
Simon Glass5620cf82018-10-01 12:22:40 -060035 gpio1 = &gpio_a;
36 gpio2 = &gpio_b;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +010037 gpio3 = &gpio_c;
Simon Glass0ccb0972015-01-25 08:27:05 -070038 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -060039 mmc0 = "/mmc0";
40 mmc1 = "/mmc1";
Simon Glassf1eba352022-10-20 18:23:20 -060041 mmc2 = "/mmc2";
42 mmc3 = "/mmc3";
Simon Glassfff928c2023-08-24 13:55:41 -060043 mmc4 = "/mmc4";
44 mmc5 = "/mmc5";
Alexander Gendin038cb022023-10-09 01:24:36 +000045 mmc6 = "/mmc6";
Mattijs Korpershoekd77f8152024-07-10 10:40:06 +020046 mmc7 = "/mmc7";
Bin Meng408e5902018-08-03 01:14:41 -070047 pci0 = &pci0;
48 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -070049 pci2 = &pci2;
Michael Walle7c41a222020-06-02 01:47:09 +020050 remoteproc0 = &rproc_1;
51 remoteproc1 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -060052 rtc0 = &rtc_0;
53 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -060054 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +020055 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -070056 testbus3 = "/some-bus";
57 testfdt0 = "/some-bus/c-test@0";
Simon Glass7d5e4112020-12-16 21:20:26 -070058 testfdt12 = "/some-bus/c-test@1";
Simon Glass0ccb0972015-01-25 08:27:05 -070059 testfdt3 = "/b-test";
60 testfdt5 = "/some-bus/c-test@5";
61 testfdt8 = "/a-test";
Simon Glass791a17f2020-12-16 21:20:27 -070062 testfdtm1 = &testfdtm1;
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +020063 fdt-dummy0 = "/translation-test@8000/dev@0,0";
64 fdt-dummy1 = "/translation-test@8000/dev@1,100";
65 fdt-dummy2 = "/translation-test@8000/dev@2,200";
66 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glass31680482015-03-25 12:23:05 -060067 usb0 = &usb_0;
68 usb1 = &usb_1;
69 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +020070 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +020071 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -060072 };
73
Eddie James1a55a7a2023-10-24 10:43:51 -050074 reserved-memory {
75 #address-cells = <1>;
76 #size-cells = <1>;
77 ranges;
78
79 event_log: tcg_event_log {
80 no-map;
81 reg = <(CFG_SYS_SDRAM_SIZE - 0x2000) 0x2000>;
82 };
83 };
84
Simon Glass5e135d32022-10-20 18:23:15 -060085 binman: binman {
Philippe Reynes462d1632022-03-28 22:56:53 +020086 };
87
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020088 config {
Simon Glass0034d962021-08-07 07:24:01 -060089 testing-bool;
90 testing-int = <123>;
91 testing-str = "testing";
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020092 environment {
93 from_fdt = "yes";
94 fdt_env_path = "";
95 };
96 };
97
Michal Simek43c42bd2023-08-31 08:59:05 +020098 options {
99 u-boot {
100 compatible = "u-boot,config";
101 bootscr-ram-offset = /bits/ 64 <0x12345678>;
Michal Simek6a7c1ce2023-08-31 09:04:27 +0200102 bootscr-flash-offset = /bits/ 64 <0>;
103 bootscr-flash-size = /bits/ 64 <0x2000>;
Michal Simek43c42bd2023-08-31 08:59:05 +0200104 };
105 };
106
Simon Glassb255efc2022-04-24 23:31:24 -0600107 bootstd {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700108 bootph-verify;
Simon Glassb255efc2022-04-24 23:31:24 -0600109 compatible = "u-boot,boot-std";
110
111 filename-prefixes = "/", "/boot/";
112 bootdev-order = "mmc2", "mmc1";
113
Simon Glassb71d7f72023-05-10 16:34:46 -0600114 extlinux {
115 compatible = "u-boot,extlinux";
Simon Glassb255efc2022-04-24 23:31:24 -0600116 };
117
118 efi {
119 compatible = "u-boot,distro-efi";
120 };
Simon Glassa9289612022-10-20 18:23:14 -0600121
Simon Glassd2bc33ed2023-01-06 08:52:41 -0600122 theme {
123 font-size = <30>;
Simon Glass86f1ac52023-06-01 10:23:00 -0600124 menu-inset = <3>;
125 menuitem-gap-y = <1>;
Simon Glassd2bc33ed2023-01-06 08:52:41 -0600126 };
127
Simon Glass82adc292023-08-14 16:40:30 -0600128 cedit-theme {
129 font-size = <30>;
130 menu-inset = <3>;
131 menuitem-gap-y = <1>;
132 };
133
Simon Glassf1eba352022-10-20 18:23:20 -0600134 /*
135 * This is used for the VBE OS-request tests. A FAT filesystem
136 * created in a partition with the VBE information appearing
Michal Simek33224372023-09-07 14:55:48 +0200137 * before the partition starts
Simon Glassf1eba352022-10-20 18:23:20 -0600138 */
Simon Glassa9289612022-10-20 18:23:14 -0600139 firmware0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700140 bootph-verify;
Simon Glassa9289612022-10-20 18:23:14 -0600141 compatible = "fwupd,vbe-simple";
142 storage = "mmc1";
143 skip-offset = <0x200>;
144 area-start = <0x400>;
145 area-size = <0x1000>;
146 state-offset = <0x400>;
147 state-size = <0x40>;
148 version-offset = <0x800>;
149 version-size = <0x100>;
150 };
Simon Glassf1eba352022-10-20 18:23:20 -0600151
152 /*
153 * This is used for the VBE VPL tests. The MMC device holds the
154 * binman image.bin file. The test progresses through each phase
155 * of U-Boot, loading each in turn from MMC.
156 *
157 * Note that the test enables this node (and mmc3) before
158 * running U-Boot
159 */
160 firmware1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700161 bootph-verify;
Simon Glassf1eba352022-10-20 18:23:20 -0600162 status = "disabled";
163 compatible = "fwupd,vbe-simple";
164 storage = "mmc3";
Simon Glass9bb73e32023-04-02 14:01:24 +1200165 skip-offset = <0x800000>;
Simon Glassf1eba352022-10-20 18:23:20 -0600166 area-start = <0>;
167 area-size = <0xe00000>;
168 state-offset = <0xdffc00>;
169 state-size = <0x40>;
170 version-offset = <0xdffe00>;
171 version-size = <0x100>;
172 };
Simon Glassb255efc2022-04-24 23:31:24 -0600173 };
174
Simon Glass61300722023-06-01 10:23:01 -0600175 cedit: cedit {
176 };
177
Andrew Scull451b8b12022-05-30 10:00:12 +0000178 fuzzing-engine {
179 compatible = "sandbox,fuzzing-engine";
180 };
181
Nandor Han6521e5d2021-06-10 16:56:44 +0300182 reboot-mode0 {
183 compatible = "reboot-mode-gpio";
184 gpios = <&gpio_c 0 GPIO_ACTIVE_HIGH>, <&gpio_c 1 GPIO_ACTIVE_HIGH>;
185 u-boot,env-variable = "bootstatus";
186 mode-test = <0x01>;
187 mode-download = <0x03>;
188 };
189
Nandor Han7e4067a2021-06-10 16:56:45 +0300190 reboot_mode1: reboot-mode@14 {
191 compatible = "reboot-mode-rtc";
192 rtc = <&rtc_0>;
193 reg = <0x30 4>;
194 u-boot,env-variable = "bootstatus";
195 big-endian;
196 mode-test = <0x21969147>;
197 mode-download = <0x51939147>;
198 };
199
Simon Glassed96cde2018-12-10 10:37:33 -0700200 audio: audio-codec {
201 compatible = "sandbox,audio-codec";
202 #sound-dai-cells = <1>;
203 };
204
Philippe Reynes1ee26482020-07-24 18:19:51 +0200205 buttons {
206 compatible = "gpio-keys";
207
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200208 btn1 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200209 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200210 label = "button1";
Dzmitry Sankouski157f2c52023-01-22 18:21:24 +0300211 linux,code = <BTN_1>;
Philippe Reynes1ee26482020-07-24 18:19:51 +0200212 };
213
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200214 btn2 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200215 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200216 label = "button2";
Dzmitry Sankouski157f2c52023-01-22 18:21:24 +0300217 linux,code = <BTN_2>;
Philippe Reynes1ee26482020-07-24 18:19:51 +0200218 };
219 };
220
Marek Szyprowskiad398592021-02-18 11:33:18 +0100221 buttons2 {
222 compatible = "adc-keys";
223 io-channels = <&adc 3>;
224 keyup-threshold-microvolt = <3000000>;
225
226 button-up {
227 label = "button3";
228 linux,code = <KEY_F3>;
229 press-threshold-microvolt = <1500000>;
230 };
231
232 button-down {
233 label = "button4";
234 linux,code = <KEY_F4>;
235 press-threshold-microvolt = <1000000>;
236 };
237
238 button-enter {
239 label = "button5";
240 linux,code = <KEY_F5>;
241 press-threshold-microvolt = <500000>;
242 };
243 };
244
Simon Glassc953aaf2018-12-10 10:37:34 -0700245 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -0600246 reg = <0 0>;
247 compatible = "google,cros-ec-sandbox";
248
249 /*
250 * This describes the flash memory within the EC. Note
251 * that the STM32L flash erases to 0, not 0xff.
252 */
253 flash {
254 image-pos = <0x08000000>;
255 size = <0x20000>;
256 erase-value = <0>;
257
258 /* Information for sandbox */
259 ro {
260 image-pos = <0>;
261 size = <0xf000>;
262 };
263 wp-ro {
264 image-pos = <0xf000>;
265 size = <0x1000>;
Simon Glassbf0a6922021-01-21 13:57:14 -0700266 used = <0x884>;
267 compress = "lz4";
268 uncomp-size = <0xcf8>;
269 hash {
270 algo = "sha256";
271 value = [00 01 02 03 04 05 06 07
272 08 09 0a 0b 0c 0d 0e 0f
273 10 11 12 13 14 15 16 17
274 18 19 1a 1b 1c 1d 1e 1f];
275 };
Simon Glass699c9ca2018-10-01 12:22:08 -0600276 };
277 rw {
278 image-pos = <0x10000>;
279 size = <0x10000>;
280 };
281 };
Alper Nebi Yasak8a8cd4f2021-05-19 19:33:31 +0300282
283 cros_ec_pwm: cros-ec-pwm {
284 compatible = "google,cros-ec-pwm";
285 #pwm-cells = <1>;
286 };
287
Simon Glass699c9ca2018-10-01 12:22:08 -0600288 };
289
Yannick Fertré9712c822019-10-07 15:29:05 +0200290 dsi_host: dsi_host {
291 compatible = "sandbox,dsi-host";
292 };
293
Simon Glassb2c1cac2014-02-26 15:59:21 -0700294 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600295 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700296 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600297 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700298 ping-add = <0>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700299 bootph-all;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100300 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
301 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass16e10402015-01-05 20:05:29 -0700302 <0>, <&gpio_a 12>;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100303 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
304 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
305 <&gpio_b 7 GPIO_IN 3 2 1>,
306 <&gpio_b 8 GPIO_OUT 3 2 1>,
307 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100308 test3-gpios =
309 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
310 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
311 <&gpio_c 2 GPIO_OUT>,
312 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
313 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong643778b2020-05-05 10:43:18 +0200314 <&gpio_c 5 GPIO_IN>,
315 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
316 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530317 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
318 test5-gpios = <&gpio_a 19>;
319
Simon Glass73025392021-10-23 17:26:04 -0600320 bool-value;
Stefan Herbrechtsmeier1b090e62022-06-14 15:21:30 +0200321 int8-value = /bits/ 8 <0x12>;
322 int16-value = /bits/ 16 <0x1234>;
Simon Glass6df01f92018-12-10 10:37:37 -0700323 int-value = <1234>;
324 uint-value = <(-1234)>;
Dario Binacchi421e81e2020-03-29 18:04:40 +0200325 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi81d80b52020-03-29 18:04:41 +0200326 int-array = <5678 9123 4567>;
Michal Simek08a194e2023-08-25 11:37:46 +0200327 int64-array = /bits/ 64 <0x1111222233334444 0x4444333322221111>;
Simon Glassdd0ed902020-07-07 13:11:58 -0600328 str-value = "test string";
Simon Glass515dcff2020-02-06 09:55:00 -0700329 interrupts-extended = <&irq 3 0>;
Simon Glass09642392020-07-07 13:12:11 -0600330 acpi,name = "GHIJ";
Patrick Delaunay8cd28012020-09-25 09:41:16 +0200331 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530332
333 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
334 <&muxcontroller0 2>, <&muxcontroller0 3>,
335 <&muxcontroller1>;
336 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
337 mux-syscon = <&syscon3>;
Dario Binacchi836cc9d2020-12-30 00:16:26 +0100338 display-timings {
339 timing0: 240x320 {
340 clock-frequency = <6500000>;
341 hactive = <240>;
342 vactive = <320>;
343 hfront-porch = <6>;
344 hback-porch = <7>;
345 hsync-len = <1>;
346 vback-porch = <5>;
347 vfront-porch = <8>;
348 vsync-len = <2>;
349 hsync-active = <1>;
350 vsync-active = <0>;
351 de-active = <1>;
352 pixelclk-active = <1>;
353 interlaced;
354 doublescan;
355 doubleclk;
356 };
357 timing1: 480x800 {
358 clock-frequency = <9000000>;
359 hactive = <480>;
360 vactive = <800>;
361 hfront-porch = <10>;
362 hback-porch = <59>;
363 hsync-len = <12>;
364 vback-porch = <15>;
365 vfront-porch = <17>;
366 vsync-len = <16>;
367 hsync-active = <0>;
368 vsync-active = <1>;
369 de-active = <0>;
370 pixelclk-active = <0>;
371 };
372 timing2: 800x480 {
373 clock-frequency = <33500000>;
374 hactive = <800>;
375 vactive = <480>;
376 hback-porch = <89>;
377 hfront-porch = <164>;
378 vback-porch = <23>;
379 vfront-porch = <10>;
380 hsync-len = <11>;
381 vsync-len = <13>;
382 };
383 };
Raphael Gallais-Poua853b922023-05-11 16:36:52 +0200384 panel-timing {
Nikhil M Jainbb9d1312023-01-31 15:35:15 +0530385 clock-frequency = <6500000>;
386 hactive = <240>;
387 vactive = <320>;
388 hfront-porch = <6>;
389 hback-porch = <7>;
390 hsync-len = <1>;
391 vback-porch = <5>;
392 vfront-porch = <8>;
393 vsync-len = <2>;
394 hsync-active = <1>;
395 vsync-active = <0>;
396 de-active = <1>;
397 pixelclk-active = <1>;
398 interlaced;
399 doublescan;
400 doubleclk;
401 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700402 };
403
404 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600405 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700406 compatible = "not,compatible";
407 };
408
409 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600410 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700411 };
412
Simon Glass5620cf82018-10-01 12:22:40 -0600413 backlight: backlight {
414 compatible = "pwm-backlight";
415 enable-gpios = <&gpio_a 1>;
416 power-supply = <&ldo_1>;
417 pwms = <&pwm 0 1000>;
418 default-brightness-level = <5>;
419 brightness-levels = <0 16 32 64 128 170 202 234 255>;
420 };
421
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200422 bind-test {
Patrice Chotard7b7f9392020-07-28 09:13:33 +0200423 compatible = "simple-bus";
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200424 bind-test-child1 {
425 compatible = "sandbox,phy";
426 #phy-cells = <1>;
427 };
428
429 bind-test-child2 {
430 compatible = "simple-bus";
431 };
432 };
433
Simon Glassb2c1cac2014-02-26 15:59:21 -0700434 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600435 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700436 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600437 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700438 ping-add = <3>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530439
440 mux-controls = <&muxcontroller0 0>;
441 mux-control-names = "mux0";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700442 };
443
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200444 phy_provider0: gen_phy@0 {
445 compatible = "sandbox,phy";
446 #phy-cells = <1>;
447 };
448
449 phy_provider1: gen_phy@1 {
450 compatible = "sandbox,phy";
451 #phy-cells = <0>;
452 broken;
453 };
454
developer71092972020-05-02 11:35:12 +0200455 phy_provider2: gen_phy@2 {
456 compatible = "sandbox,phy";
457 #phy-cells = <0>;
458 };
459
Jonas Karlman9f89e682023-08-31 22:16:35 +0000460 phy_provider3: gen_phy@3 {
461 compatible = "sandbox,phy";
462 #phy-cells = <2>;
463 };
464
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200465 gen_phy_user: gen_phy_user {
466 compatible = "simple-bus";
467 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
468 phy-names = "phy1", "phy2", "phy3";
469 };
470
developer71092972020-05-02 11:35:12 +0200471 gen_phy_user1: gen_phy_user1 {
472 compatible = "simple-bus";
473 phys = <&phy_provider0 0>, <&phy_provider2>;
474 phy-names = "phy1", "phy2";
475 };
476
Jonas Karlman9f89e682023-08-31 22:16:35 +0000477 gen_phy_user2: gen_phy_user2 {
478 compatible = "simple-bus";
479 phys = <&phy_provider3 0 0>;
480 phy-names = "phy1";
481 };
482
Simon Glassb2c1cac2014-02-26 15:59:21 -0700483 some-bus {
484 #address-cells = <1>;
485 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600486 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600487 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600488 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700489 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600490 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700491 compatible = "denx,u-boot-fdt-test";
492 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600493 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700494 ping-add = <5>;
495 };
Simon Glass40717422014-07-23 06:55:18 -0600496 c-test@0 {
497 compatible = "denx,u-boot-fdt-test";
498 reg = <0>;
499 ping-expect = <6>;
500 ping-add = <6>;
501 };
502 c-test@1 {
503 compatible = "denx,u-boot-fdt-test";
504 reg = <1>;
505 ping-expect = <7>;
506 ping-add = <7>;
507 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700508 };
509
510 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600511 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600512 ping-expect = <6>;
513 ping-add = <6>;
514 compatible = "google,another-fdt-test";
515 };
516
517 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600518 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600519 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700520 ping-add = <6>;
521 compatible = "google,another-fdt-test";
522 };
523
Simon Glass0ccb0972015-01-25 08:27:05 -0700524 f-test {
525 compatible = "denx,u-boot-fdt-test";
526 };
527
528 g-test {
529 compatible = "denx,u-boot-fdt-test";
530 };
531
Bin Mengd9d24782018-10-10 22:07:01 -0700532 h-test {
533 compatible = "denx,u-boot-fdt-test1";
534 };
535
developercf8bc132020-05-02 11:35:10 +0200536 i-test {
537 compatible = "mediatek,u-boot-fdt-test";
538 #address-cells = <1>;
539 #size-cells = <0>;
540
541 subnode@0 {
542 reg = <0>;
543 };
544
545 subnode@1 {
546 reg = <1>;
547 };
548
549 subnode@2 {
550 reg = <2>;
551 };
552 };
553
Simon Glass204675c2019-12-29 21:19:25 -0700554 devres-test {
555 compatible = "denx,u-boot-devres-test";
556 };
557
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530558 another-test {
559 reg = <0 2>;
560 compatible = "denx,u-boot-fdt-test";
561 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
562 test5-gpios = <&gpio_a 19>;
563 };
564
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100565 mmio-bus@0 {
566 #address-cells = <1>;
567 #size-cells = <1>;
568 compatible = "denx,u-boot-test-bus";
569 dma-ranges = <0x10000000 0x00000000 0x00040000>;
570
571 subnode@0 {
572 compatible = "denx,u-boot-fdt-test";
573 };
574 };
575
576 mmio-bus@1 {
577 #address-cells = <1>;
578 #size-cells = <1>;
579 compatible = "denx,u-boot-test-bus";
Nicolas Saenz Julienne892e9b42021-01-12 13:55:25 +0100580
581 subnode@0 {
582 compatible = "denx,u-boot-fdt-test";
583 };
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100584 };
585
Simon Glass3c601b12020-07-07 13:12:06 -0600586 acpi_test1: acpi-test {
Simon Glass2d67fdf2020-04-08 16:57:34 -0600587 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600588 acpi-ssdt-test-data = "ab";
Simon Glass990cd5b2020-07-07 13:12:08 -0600589 acpi-dsdt-test-data = "hi";
Simon Glassebb2e832020-07-07 13:11:39 -0600590 child {
591 compatible = "denx,u-boot-acpi-test";
592 };
Simon Glass2d67fdf2020-04-08 16:57:34 -0600593 };
594
Simon Glass3c601b12020-07-07 13:12:06 -0600595 acpi_test2: acpi-test2 {
Simon Glass17968c32020-04-26 09:19:46 -0600596 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600597 acpi-ssdt-test-data = "cd";
Simon Glass990cd5b2020-07-07 13:12:08 -0600598 acpi-dsdt-test-data = "jk";
Simon Glass17968c32020-04-26 09:19:46 -0600599 };
600
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200601 clocks {
602 clk_fixed: clk-fixed {
603 compatible = "fixed-clock";
604 #clock-cells = <0>;
605 clock-frequency = <1234>;
606 };
Anup Patel8d28c3c2019-02-25 08:14:55 +0000607
608 clk_fixed_factor: clk-fixed-factor {
609 compatible = "fixed-factor-clock";
610 #clock-cells = <0>;
611 clock-div = <3>;
612 clock-mult = <2>;
613 clocks = <&clk_fixed>;
614 };
Lukasz Majewskiccafcdd2019-06-24 15:50:47 +0200615
616 osc {
617 compatible = "fixed-clock";
618 #clock-cells = <0>;
619 clock-frequency = <20000000>;
620 };
Stephen Warrena9622432016-06-17 09:44:00 -0600621 };
622
623 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600624 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600625 #clock-cells = <1>;
Jean-Jacques Hiblotc1e9c942019-10-22 14:00:07 +0200626 assigned-clocks = <&clk_sandbox 3>;
627 assigned-clock-rates = <321>;
Stephen Warrena9622432016-06-17 09:44:00 -0600628 };
629
630 clk-test {
631 compatible = "sandbox,clk-test";
632 clocks = <&clk_fixed>,
633 <&clk_sandbox 1>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200634 <&clk_sandbox 0>,
Yang Xiwene89289c2023-12-16 02:28:52 +0800635 <&ccf 11>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200636 <&clk_sandbox 3>,
637 <&clk_sandbox 2>;
Yang Xiwene89289c2023-12-16 02:28:52 +0800638 clock-names = "fixed", "i2c", "spi", "i2c_root", "uart2", "uart1";
Simon Glass8cc4d822015-07-06 12:54:24 -0600639 };
640
Ashok Reddy Soma8f03cef2023-08-30 10:31:42 +0200641 clk-test2 {
642 compatible = "sandbox,clk-test";
643 assigned-clock-rates = <321>;
644 };
645
646 clk-test3 {
647 compatible = "sandbox,clk-test";
648 assigned-clocks = <&clk_sandbox 1>;
649 };
650
651 clk-test4 {
652 compatible = "sandbox,clk-test";
653 assigned-clock-rates = <654>, <321>;
654 assigned-clocks = <&clk_sandbox 1>;
655 };
656
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200657 ccf: clk-ccf {
658 compatible = "sandbox,clk-ccf";
Yang Xiwene89289c2023-12-16 02:28:52 +0800659 #clock-cells = <1>;
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200660 };
661
Simon Glass507ab962021-12-04 08:56:31 -0700662 efi-media {
663 compatible = "sandbox,efi-media";
664 };
665
Simon Glass5b968632015-05-22 15:42:15 -0600666 eth@10002000 {
667 compatible = "sandbox,eth";
668 reg = <0x10002000 0x1000>;
Simon Glass5b968632015-05-22 15:42:15 -0600669 };
670
671 eth_5: eth@10003000 {
672 compatible = "sandbox,eth";
673 reg = <0x10003000 0x1000>;
Sean Anderson13652b82022-05-05 13:11:44 -0400674 nvmem-cells = <&eth5_addr>;
675 nvmem-cell-names = "mac-address";
Simon Glass5b968632015-05-22 15:42:15 -0600676 };
677
Bin Meng04a11cb2015-08-27 22:25:53 -0700678 eth_3: sbe5 {
679 compatible = "sandbox,eth";
680 reg = <0x10005000 0x1000>;
Sean Andersone2dc0e62022-05-05 13:11:42 -0400681 nvmem-cells = <&eth3_addr>;
682 nvmem-cell-names = "mac-address";
Bin Meng04a11cb2015-08-27 22:25:53 -0700683 };
684
Simon Glass5b968632015-05-22 15:42:15 -0600685 eth@10004000 {
686 compatible = "sandbox,eth";
687 reg = <0x10004000 0x1000>;
Simon Glass5b968632015-05-22 15:42:15 -0600688 };
689
Marek Behúnf4f1ddc2022-04-07 00:32:57 +0200690 phy_eth0: phy-test-eth {
691 compatible = "sandbox,eth";
692 reg = <0x10007000 0x1000>;
Sean Anderson24b1b8d2022-05-05 13:11:35 -0400693 mac-address = [ 02 00 11 22 33 49 ];
Marek Behúnf4f1ddc2022-04-07 00:32:57 +0200694 phy-handle = <&ethphy1>;
Marek Behúnbc194772022-04-07 00:33:01 +0200695 phy-mode = "2500base-x";
Marek Behúnf4f1ddc2022-04-07 00:32:57 +0200696 };
697
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800698 dsa_eth0: dsa-test-eth {
699 compatible = "sandbox,eth";
700 reg = <0x10006000 0x1000>;
Sean Anderson5768e8b2022-05-05 13:11:43 -0400701 nvmem-cells = <&eth4_addr>;
702 nvmem-cell-names = "mac-address";
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800703 };
704
705 dsa-test {
706 compatible = "sandbox,dsa";
707
708 ports {
709 #address-cells = <1>;
710 #size-cells = <0>;
711 swp_0: port@0 {
712 reg = <0>;
713 label = "lan0";
714 phy-mode = "rgmii-rxid";
715
716 fixed-link {
717 speed = <100>;
718 full-duplex;
719 };
720 };
721
722 swp_1: port@1 {
723 reg = <1>;
724 label = "lan1";
725 phy-mode = "rgmii-txid";
Bin Meng381ed972021-03-14 20:14:58 +0800726 fixed-link = <0 1 100 0 0>;
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800727 };
728
729 port@2 {
730 reg = <2>;
731 ethernet = <&dsa_eth0>;
732
733 fixed-link {
734 speed = <1000>;
735 full-duplex;
736 };
737 };
738 };
739 };
740
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700741 firmware {
742 sandbox_firmware: sandbox-firmware {
743 compatible = "sandbox,firmware";
744 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200745
Etienne Carriere09665cb2022-02-21 09:22:39 +0100746 scmi {
Etienne Carriere02fd1262020-09-09 18:44:00 +0200747 compatible = "sandbox,scmi-agent";
748 #address-cells = <1>;
749 #size-cells = <0>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200750
AKASHI Takahiro535a7bd2023-10-16 14:39:45 +0900751 pwrdom_scmi: protocol@11 {
752 reg = <0x11>;
753 #power-domain-cells = <1>;
754 };
755
Etienne Carriere09665cb2022-02-21 09:22:39 +0100756 clk_scmi: protocol@14 {
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200757 reg = <0x14>;
758 #clock-cells = <1>;
AKASHI Takahirocc4ecda2023-10-11 19:06:59 +0900759 linaro,sandbox-channel-id = <0x14>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200760 };
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200761
Etienne Carriere09665cb2022-02-21 09:22:39 +0100762 reset_scmi: protocol@16 {
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200763 reg = <0x16>;
764 #reset-cells = <1>;
765 };
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100766
767 protocol@17 {
768 reg = <0x17>;
769
770 regulators {
771 #address-cells = <1>;
772 #size-cells = <0>;
773
Etienne Carriere09665cb2022-02-21 09:22:39 +0100774 regul0_scmi: reg@0 {
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100775 reg = <0>;
776 regulator-name = "sandbox-voltd0";
777 regulator-min-microvolt = <1100000>;
778 regulator-max-microvolt = <3300000>;
779 };
Etienne Carriere09665cb2022-02-21 09:22:39 +0100780 regul1_scmi: reg@1 {
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100781 reg = <0x1>;
782 regulator-name = "sandbox-voltd1";
783 regulator-min-microvolt = <1800000>;
784 };
785 };
786 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200787 };
Alexey Romanov9dc617d2023-09-21 11:13:36 +0300788
789 sm: secure-monitor {
790 compatible = "sandbox,sm";
791 };
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700792 };
793
Alexander Dahl6ac319d2022-09-30 14:04:30 +0200794 fpga {
795 compatible = "sandbox,fpga";
796 };
797
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100798 pinctrl-gpio {
799 compatible = "sandbox,pinctrl-gpio";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700800
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100801 gpio_a: base-gpios {
802 compatible = "sandbox,gpio";
803 gpio-controller;
804 #gpio-cells = <1>;
805 gpio-bank-name = "a";
806 sandbox,gpio-count = <20>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200807 hog_input_active_low {
808 gpio-hog;
809 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200810 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200811 };
812 hog_input_active_high {
813 gpio-hog;
814 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200815 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200816 };
817 hog_output_low {
818 gpio-hog;
819 output-low;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200820 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200821 };
822 hog_output_high {
823 gpio-hog;
824 output-high;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200825 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200826 };
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100827 };
828
829 gpio_b: extra-gpios {
830 compatible = "sandbox,gpio";
831 gpio-controller;
832 #gpio-cells = <5>;
833 gpio-bank-name = "b";
834 sandbox,gpio-count = <10>;
835 };
Simon Glass25348a42014-10-13 23:42:11 -0600836
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100837 gpio_c: pinmux-gpios {
838 compatible = "sandbox,gpio";
839 gpio-controller;
840 #gpio-cells = <2>;
841 gpio-bank-name = "c";
842 sandbox,gpio-count = <10>;
843 };
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100844 };
845
Simon Glass7df766e2014-12-10 08:55:55 -0700846 i2c@0 {
847 #address-cells = <1>;
848 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600849 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700850 compatible = "sandbox,i2c";
851 clock-frequency = <100000>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200852 pinctrl-names = "default";
853 pinctrl-0 = <&pinmux_i2c0_pins>;
854
Simon Glass7df766e2014-12-10 08:55:55 -0700855 eeprom@2c {
Sean Andersone2dc0e62022-05-05 13:11:42 -0400856 #address-cells = <1>;
857 #size-cells = <1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700858 reg = <0x2c>;
859 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700860 sandbox,emul = <&emul_eeprom>;
Michal Simek4f18f922020-05-28 11:48:55 +0200861 partitions {
862 compatible = "fixed-partitions";
863 #address-cells = <1>;
864 #size-cells = <1>;
865 bootcount_i2c: bootcount@10 {
866 reg = <10 2>;
867 };
868 };
Sean Andersone2dc0e62022-05-05 13:11:42 -0400869
870 eth3_addr: mac-address@24 {
871 reg = <24 6>;
872 };
Simon Glass7df766e2014-12-10 08:55:55 -0700873 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200874
Simon Glass336b2952015-05-22 15:42:17 -0600875 rtc_0: rtc@43 {
Sean Anderson5768e8b2022-05-05 13:11:43 -0400876 #address-cells = <1>;
877 #size-cells = <1>;
Simon Glass336b2952015-05-22 15:42:17 -0600878 reg = <0x43>;
879 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700880 sandbox,emul = <&emul0>;
Sean Anderson5768e8b2022-05-05 13:11:43 -0400881
882 eth4_addr: mac-address@40 {
883 reg = <0x40 6>;
884 };
Simon Glass336b2952015-05-22 15:42:17 -0600885 };
886
887 rtc_1: rtc@61 {
888 reg = <0x61>;
889 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700890 sandbox,emul = <&emul1>;
891 };
892
893 i2c_emul: emul {
894 reg = <0xff>;
895 compatible = "sandbox,i2c-emul-parent";
896 emul_eeprom: emul-eeprom {
897 compatible = "sandbox,i2c-eeprom";
898 sandbox,filename = "i2c.bin";
899 sandbox,size = <256>;
900 };
901 emul0: emul0 {
Simon Glass98af3742021-02-03 06:01:17 -0700902 compatible = "sandbox,i2c-rtc-emul";
Simon Glass17b56f62018-11-18 08:14:34 -0700903 };
904 emul1: emull {
Simon Glass98af3742021-02-03 06:01:17 -0700905 compatible = "sandbox,i2c-rtc-emul";
Simon Glass336b2952015-05-22 15:42:17 -0600906 };
907 };
908
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200909 sandbox_pmic: sandbox_pmic {
910 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700911 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200912 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200913
914 mc34708: pmic@41 {
915 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700916 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200917 };
Simon Glass7df766e2014-12-10 08:55:55 -0700918 };
919
Philipp Tomsich1fc53302018-12-14 21:14:29 +0100920 bootcount@0 {
921 compatible = "u-boot,bootcount-rtc";
922 rtc = <&rtc_1>;
923 offset = <0x13>;
924 };
925
Michal Simek4f18f922020-05-28 11:48:55 +0200926 bootcount {
927 compatible = "u-boot,bootcount-i2c-eeprom";
928 i2c-eeprom = <&bootcount_i2c>;
929 };
930
Nandor Han88895812021-06-10 15:40:38 +0300931 bootcount_4@0 {
932 compatible = "u-boot,bootcount-syscon";
933 syscon = <&syscon0>;
934 reg = <0x0 0x04>, <0x0 0x04>;
935 reg-names = "syscon_reg", "offset";
936 };
937
938 bootcount_2@0 {
939 compatible = "u-boot,bootcount-syscon";
940 syscon = <&syscon0>;
941 reg = <0x0 0x04>, <0x0 0x02> ;
942 reg-names = "syscon_reg", "offset";
943 };
944
Marek Szyprowskiad398592021-02-18 11:33:18 +0100945 adc: adc@0 {
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100946 compatible = "sandbox,adc";
Marek Szyprowskiad398592021-02-18 11:33:18 +0100947 #io-channel-cells = <1>;
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100948 vdd-supply = <&buck2>;
949 vss-microvolts = <0>;
950 };
951
Mark Kettenis67748ee2021-10-23 16:58:02 +0200952 iommu: iommu@0 {
953 compatible = "sandbox,iommu";
954 #iommu-cells = <0>;
955 };
956
Simon Glass515dcff2020-02-06 09:55:00 -0700957 irq: irq {
Simon Glass54028bc2019-12-06 21:41:59 -0700958 compatible = "sandbox,irq";
Simon Glass515dcff2020-02-06 09:55:00 -0700959 interrupt-controller;
960 #interrupt-cells = <2>;
Simon Glass54028bc2019-12-06 21:41:59 -0700961 };
962
Simon Glass90b6fef2016-01-18 19:52:26 -0700963 lcd {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700964 bootph-all;
Simon Glass90b6fef2016-01-18 19:52:26 -0700965 compatible = "sandbox,lcd-sdl";
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200966 pinctrl-names = "default";
967 pinctrl-0 = <&pinmux_lcd_pins>;
Simon Glass90b6fef2016-01-18 19:52:26 -0700968 xres = <1366>;
969 yres = <768>;
970 };
971
Simon Glassd783eb32015-07-06 12:54:34 -0600972 leds {
973 compatible = "gpio-leds";
974
975 iracibble {
976 gpios = <&gpio_a 1 0>;
977 label = "sandbox:red";
978 };
979
980 martinet {
981 gpios = <&gpio_a 2 0>;
982 label = "sandbox:green";
983 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200984
985 default_on {
986 gpios = <&gpio_a 5 0>;
987 label = "sandbox:default_on";
988 default-state = "on";
989 };
990
991 default_off {
992 gpios = <&gpio_a 6 0>;
Sean Andersonfbf8d652020-09-14 11:02:03 -0400993 /* label intentionally omitted */
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200994 default-state = "off";
995 };
Simon Glassd783eb32015-07-06 12:54:34 -0600996 };
997
Paul Doelle709f0372022-07-04 09:00:25 +0000998 wdt-gpio-toggle {
Simon Glasse0f8cd22023-08-10 09:53:13 -0600999 gpios = <&gpio_a 8 0>;
Rasmus Villemoes2b673872021-08-19 11:57:05 +02001000 compatible = "linux,wdt-gpio";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +02001001 hw_margin_ms = <100>;
Paul Doelle709f0372022-07-04 09:00:25 +00001002 hw_algo = "toggle";
1003 always-running;
1004 };
1005
1006 wdt-gpio-level {
1007 gpios = <&gpio_a 7 0>;
1008 compatible = "linux,wdt-gpio";
1009 hw_margin_ms = <100>;
1010 hw_algo = "level";
Rasmus Villemoes2b673872021-08-19 11:57:05 +02001011 always-running;
1012 };
1013
Stephen Warren62f2c902016-05-16 17:41:37 -06001014 mbox: mbox {
1015 compatible = "sandbox,mbox";
1016 #mbox-cells = <1>;
1017 };
1018
1019 mbox-test {
1020 compatible = "sandbox,mbox-test";
1021 mboxes = <&mbox 100>, <&mbox 1>;
1022 mbox-names = "other", "test";
1023 };
1024
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001025 cpus {
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +02001026 #address-cells = <1>;
1027 #size-cells = <0>;
Sean Anderson79d3bba2020-09-28 10:52:23 -04001028 timebase-frequency = <2000000>;
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +02001029 cpu1: cpu@1 {
1030 device_type = "cpu";
1031 reg = <0x1>;
Sean Anderson79d3bba2020-09-28 10:52:23 -04001032 timebase-frequency = <3000000>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001033 compatible = "sandbox,cpu_sandbox";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001034 bootph-all;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001035 };
Mario Sixdea5df72018-08-06 10:23:44 +02001036
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +02001037 cpu2: cpu@2 {
1038 device_type = "cpu";
1039 reg = <0x2>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001040 compatible = "sandbox,cpu_sandbox";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001041 bootph-all;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001042 };
Mario Sixdea5df72018-08-06 10:23:44 +02001043
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +02001044 cpu3: cpu@3 {
1045 device_type = "cpu";
1046 reg = <0x3>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001047 compatible = "sandbox,cpu_sandbox";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001048 bootph-all;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001049 };
Mario Sixdea5df72018-08-06 10:23:44 +02001050 };
1051
Dave Gerlach75dbdfc2020-07-15 23:39:58 -05001052 chipid: chipid {
1053 compatible = "sandbox,soc";
1054 };
1055
Simon Glassc953aaf2018-12-10 10:37:34 -07001056 i2s: i2s {
1057 compatible = "sandbox,i2s";
1058 #sound-dai-cells = <1>;
Simon Glass4d5814c2019-02-16 20:24:56 -07001059 sandbox,silent; /* Don't emit sounds while testing */
Simon Glassc953aaf2018-12-10 10:37:34 -07001060 };
1061
Jean-Jacques Hiblotdb97c7f2019-07-05 09:33:57 +02001062 nop-test_0 {
1063 compatible = "sandbox,nop_sandbox1";
1064 nop-test_1 {
1065 compatible = "sandbox,nop_sandbox2";
1066 bind = "True";
1067 };
1068 nop-test_2 {
1069 compatible = "sandbox,nop_sandbox2";
1070 bind = "False";
1071 };
1072 };
1073
Roger Quadrosb0679a72022-10-20 16:30:46 +03001074 memory-controller {
1075 compatible = "sandbox,memory";
1076 };
1077
Mario Sixa8ce0ee2018-07-31 14:24:14 +02001078 misc-test {
Sean Anderson13652b82022-05-05 13:11:44 -04001079 #address-cells = <1>;
1080 #size-cells = <1>;
Mario Sixa8ce0ee2018-07-31 14:24:14 +02001081 compatible = "sandbox,misc_sandbox";
Sean Anderson13652b82022-05-05 13:11:44 -04001082
1083 eth5_addr: mac-address@10 {
1084 reg = <0x10 6>;
1085 };
Mario Sixa8ce0ee2018-07-31 14:24:14 +02001086 };
1087
Simon Glasse4fef742017-04-23 20:02:07 -06001088 mmc2 {
1089 compatible = "sandbox,mmc";
Simon Glass965cd402021-07-05 16:32:58 -06001090 non-removable;
Simon Glasse4fef742017-04-23 20:02:07 -06001091 };
1092
Simon Glassb255efc2022-04-24 23:31:24 -06001093 /* This is used for the bootdev tests */
Simon Glasse4fef742017-04-23 20:02:07 -06001094 mmc1 {
1095 compatible = "sandbox,mmc";
Simon Glassb255efc2022-04-24 23:31:24 -06001096 filename = "mmc1.img";
Simon Glasse4fef742017-04-23 20:02:07 -06001097 };
1098
Simon Glassb255efc2022-04-24 23:31:24 -06001099 /* This is used for the fastboot tests */
Sughosh Ganu77079e72022-10-21 18:16:05 +05301100 mmc0: mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -06001101 compatible = "sandbox,mmc";
1102 };
1103
Simon Glassf1eba352022-10-20 18:23:20 -06001104 /* This is used for VBE VPL tests */
1105 mmc3 {
1106 status = "disabled";
1107 compatible = "sandbox,mmc";
1108 filename = "image.bin";
1109 non-removable;
1110 };
1111
Simon Glassd2bc33ed2023-01-06 08:52:41 -06001112 /* This is used for bootstd bootmenu tests */
1113 mmc4 {
1114 status = "disabled";
1115 compatible = "sandbox,mmc";
1116 filename = "mmc4.img";
1117 };
1118
Simon Glassfff928c2023-08-24 13:55:41 -06001119 /* This is used for ChromiumOS tests */
1120 mmc5 {
1121 status = "disabled";
1122 compatible = "sandbox,mmc";
1123 filename = "mmc5.img";
1124 };
1125
Alexander Gendin038cb022023-10-09 01:24:36 +00001126 /* This is used for mbr tests */
1127 mmc6 {
1128 status = "disabled";
1129 compatible = "sandbox,mmc";
1130 filename = "mmc6.img";
1131 };
1132
Mattijs Korpershoekd77f8152024-07-10 10:40:06 +02001133 /* This is used for Android tests */
1134 mmc7 {
1135 status = "disabled";
1136 compatible = "sandbox,mmc";
1137 filename = "mmc7.img";
1138 };
1139
Simon Glass53a68b32019-02-16 20:24:50 -07001140 pch {
1141 compatible = "sandbox,pch";
1142 };
1143
Tom Rini4a3ca482020-02-11 12:41:23 -05001144 pci0: pci@0 {
Simon Glass3a6eae62015-03-05 12:25:34 -07001145 compatible = "sandbox,pci";
1146 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001147 bus-range = <0x00 0xff>;
Simon Glass3a6eae62015-03-05 12:25:34 -07001148 #address-cells = <3>;
1149 #size-cells = <2>;
Simon Glass35464f72019-09-25 08:56:08 -06001150 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glass3a6eae62015-03-05 12:25:34 -07001151 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Mark Kettenis5dfd4ec2023-01-21 20:27:57 +01001152 iommu-map = <0x0010 &iommu 0 1>;
1153 iommu-map-mask = <0xfffffff8>;
Bin Mengcbf071b2018-08-03 01:14:39 -07001154 pci@0,0 {
1155 compatible = "pci-generic";
1156 reg = <0x0000 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001157 sandbox,emul = <&swap_case_emul0_0>;
Bin Mengcbf071b2018-08-03 01:14:39 -07001158 };
Alex Margineanf1274432019-06-07 11:24:24 +03001159 pci@1,0 {
1160 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -06001161 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
Simon Glass4289c262023-09-26 08:14:58 -06001162 reg = <0x02000814 0 0 0x80 0
1163 0x01000810 0 0 0xc0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001164 sandbox,emul = <&swap_case_emul0_1>;
Alex Margineanf1274432019-06-07 11:24:24 +03001165 };
Simon Glass937bb472019-12-06 21:41:57 -07001166 p2sb-pci@2,0 {
1167 compatible = "sandbox,p2sb";
1168 reg = <0x02001010 0 0 0 0>;
1169 sandbox,emul = <&p2sb_emul>;
1170
1171 adder {
1172 intel,p2sb-port-id = <3>;
1173 compatible = "sandbox,adder";
1174 };
1175 };
Simon Glass8c501022019-12-06 21:41:54 -07001176 pci@1e,0 {
1177 compatible = "sandbox,pmc";
1178 reg = <0xf000 0 0 0 0>;
1179 sandbox,emul = <&pmc_emul1e>;
1180 acpi-base = <0x400>;
1181 gpe0-dwx-mask = <0xf>;
1182 gpe0-dwx-shift-base = <4>;
1183 gpe0-dw = <6 7 9>;
1184 gpe0-sts = <0x20>;
1185 gpe0-en = <0x30>;
1186 };
Simon Glass3a6eae62015-03-05 12:25:34 -07001187 pci@1f,0 {
1188 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -06001189 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
Simon Glass4289c262023-09-26 08:14:58 -06001190 reg = <0x0100f810 0 0 0x100 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001191 sandbox,emul = <&swap_case_emul0_1f>;
Simon Glass3a6eae62015-03-05 12:25:34 -07001192 };
1193 };
1194
Simon Glassb98ba4c2019-09-25 08:56:10 -06001195 pci-emul0 {
1196 compatible = "sandbox,pci-emul-parent";
1197 swap_case_emul0_0: emul0@0,0 {
1198 compatible = "sandbox,swap-case";
1199 };
1200 swap_case_emul0_1: emul0@1,0 {
1201 compatible = "sandbox,swap-case";
1202 use-ea;
1203 };
1204 swap_case_emul0_1f: emul0@1f,0 {
1205 compatible = "sandbox,swap-case";
1206 };
Simon Glass937bb472019-12-06 21:41:57 -07001207 p2sb_emul: emul@2,0 {
1208 compatible = "sandbox,p2sb-emul";
1209 };
Simon Glass8c501022019-12-06 21:41:54 -07001210 pmc_emul1e: emul@1e,0 {
1211 compatible = "sandbox,pmc-emul";
1212 };
Simon Glassb98ba4c2019-09-25 08:56:10 -06001213 };
1214
Tom Rini4a3ca482020-02-11 12:41:23 -05001215 pci1: pci@1 {
Bin Meng408e5902018-08-03 01:14:41 -07001216 compatible = "sandbox,pci";
1217 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001218 bus-range = <0x00 0xff>;
Bin Meng408e5902018-08-03 01:14:41 -07001219 #address-cells = <3>;
1220 #size-cells = <2>;
Suneel Garapati3ac3aec2019-10-19 17:10:20 -07001221 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
Andrew Scullc7456a42022-04-21 16:11:09 +00001222 0x02000000 0 0x31000000 0x3e000000 0 0x2000 // MEM1
Suneel Garapati3ac3aec2019-10-19 17:10:20 -07001223 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -07001224 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +02001225 0x0c 0x00 0x1234 0x5678
1226 0x10 0x00 0x1234 0x5678>;
1227 pci@10,0 {
1228 reg = <0x8000 0 0 0 0>;
1229 };
Bin Meng408e5902018-08-03 01:14:41 -07001230 };
1231
Tom Rini4a3ca482020-02-11 12:41:23 -05001232 pci2: pci@2 {
Bin Meng510dddb2018-08-03 01:14:50 -07001233 compatible = "sandbox,pci";
1234 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001235 bus-range = <0x00 0xff>;
Bin Meng510dddb2018-08-03 01:14:50 -07001236 #address-cells = <3>;
1237 #size-cells = <2>;
1238 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
1239 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
1240 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
1241 pci@1f,0 {
1242 compatible = "pci-generic";
1243 reg = <0xf800 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001244 sandbox,emul = <&swap_case_emul2_1f>;
1245 };
1246 };
1247
1248 pci-emul2 {
1249 compatible = "sandbox,pci-emul-parent";
1250 swap_case_emul2_1f: emul2@1f,0 {
1251 compatible = "sandbox,swap-case";
Bin Meng510dddb2018-08-03 01:14:50 -07001252 };
1253 };
1254
Ramon Friedc64f19b2019-04-27 11:15:23 +03001255 pci_ep: pci_ep {
1256 compatible = "sandbox,pci_ep";
1257 };
1258
Simon Glass9c433fe2017-04-23 20:10:44 -06001259 probing {
1260 compatible = "simple-bus";
1261 test1 {
1262 compatible = "denx,u-boot-probe-test";
1263 };
1264
1265 test2 {
1266 compatible = "denx,u-boot-probe-test";
1267 };
1268
1269 test3 {
1270 compatible = "denx,u-boot-probe-test";
1271 };
1272
1273 test4 {
1274 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001275 first-syscon = <&syscon0>;
1276 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunayee010432019-03-07 09:57:13 +01001277 third-syscon = <&syscon2>;
Simon Glass9c433fe2017-04-23 20:10:44 -06001278 };
1279 };
1280
Stephen Warren92c67fa2016-07-13 13:45:31 -06001281 pwrdom: power-domain {
1282 compatible = "sandbox,power-domain";
1283 #power-domain-cells = <1>;
1284 };
1285
1286 power-domain-test {
1287 compatible = "sandbox,power-domain-test";
1288 power-domains = <&pwrdom 2>;
1289 };
1290
Simon Glass5620cf82018-10-01 12:22:40 -06001291 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -06001292 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001293 #pwm-cells = <2>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001294 pinctrl-names = "default";
1295 pinctrl-0 = <&pinmux_pwm_pins>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001296 };
1297
1298 pwm2 {
1299 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001300 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001301 };
1302
Simon Glass3d355e62015-07-06 12:54:31 -06001303 ram {
1304 compatible = "sandbox,ram";
1305 };
1306
Simon Glassd860f222015-07-06 12:54:29 -06001307 reset@0 {
1308 compatible = "sandbox,warm-reset";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001309 bootph-some-ram;
Simon Glassd860f222015-07-06 12:54:29 -06001310 };
1311
1312 reset@1 {
1313 compatible = "sandbox,reset";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001314 bootph-some-ram;
Simon Glassd860f222015-07-06 12:54:29 -06001315 };
1316
Stephen Warren6488e642016-06-17 09:43:59 -06001317 resetc: reset-ctl {
1318 compatible = "sandbox,reset-ctl";
1319 #reset-cells = <1>;
1320 };
1321
1322 reset-ctl-test {
1323 compatible = "sandbox,reset-ctl-test";
Neil Armstrong9b4cdef2021-04-20 10:42:25 +02001324 resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>;
1325 reset-names = "other", "test", "test2", "test3";
Stephen Warren6488e642016-06-17 09:43:59 -06001326 };
1327
Sughosh Ganu23e37512019-12-28 23:58:31 +05301328 rng {
1329 compatible = "sandbox,sandbox-rng";
1330 };
1331
Nishanth Menonedf85812015-09-17 15:42:41 -05001332 rproc_1: rproc@1 {
1333 compatible = "sandbox,test-processor";
1334 remoteproc-name = "remoteproc-test-dev1";
1335 };
1336
1337 rproc_2: rproc@2 {
1338 compatible = "sandbox,test-processor";
1339 internal-memory-mapped;
1340 remoteproc-name = "remoteproc-test-dev2";
1341 };
1342
Simon Glass5620cf82018-10-01 12:22:40 -06001343 panel {
1344 compatible = "simple-panel";
1345 backlight = <&backlight 0 100>;
1346 };
1347
Simon Glass509f32e2022-09-21 16:21:47 +02001348 scsi {
1349 compatible = "sandbox,scsi";
1350 sandbox,filepath = "scsi.img";
1351 };
1352
Ramon Fried26ed32e2018-07-02 02:57:59 +03001353 smem@0 {
1354 compatible = "sandbox,smem";
1355 };
1356
Simon Glass76072ac2018-12-10 10:37:36 -07001357 sound {
1358 compatible = "sandbox,sound";
1359 cpu {
1360 sound-dai = <&i2s 0>;
1361 };
1362
1363 codec {
1364 sound-dai = <&audio 0>;
1365 };
1366 };
1367
Simon Glass25348a42014-10-13 23:42:11 -06001368 spi@0 {
1369 #address-cells = <1>;
1370 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -06001371 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -06001372 compatible = "sandbox,spi";
Ovidiu Panaitae734732020-12-14 19:06:47 +02001373 cs-gpios = <0>, <0>, <&gpio_a 0>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001374 pinctrl-names = "default";
1375 pinctrl-0 = <&pinmux_spi0_pins>;
1376
Simon Glass25348a42014-10-13 23:42:11 -06001377 spi.bin@0 {
1378 reg = <0>;
Neil Armstronga009fa72019-02-10 10:16:20 +00001379 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass25348a42014-10-13 23:42:11 -06001380 spi-max-frequency = <40000000>;
1381 sandbox,filename = "spi.bin";
1382 };
Ovidiu Panaitae734732020-12-14 19:06:47 +02001383 spi.bin@1 {
1384 reg = <1>;
1385 compatible = "spansion,m25p16", "jedec,spi-nor";
1386 spi-max-frequency = <50000000>;
1387 sandbox,filename = "spi.bin";
1388 spi-cpol;
1389 spi-cpha;
1390 };
Simon Glass25348a42014-10-13 23:42:11 -06001391 };
1392
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001393 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -06001394 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +02001395 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -06001396 };
1397
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001398 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -06001399 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -06001400 reg = <0x20 5
1401 0x28 6
1402 0x30 7
1403 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -06001404 };
1405
Patrick Delaunayee010432019-03-07 09:57:13 +01001406 syscon2: syscon@2 {
Masahiro Yamada42ab1072018-04-23 13:26:53 +09001407 compatible = "simple-mfd", "syscon";
1408 reg = <0x40 5
1409 0x48 6
1410 0x50 7
1411 0x58 8>;
1412 };
1413
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +05301414 syscon3: syscon@3 {
1415 compatible = "simple-mfd", "syscon";
1416 reg = <0x000100 0x10>;
1417
1418 muxcontroller0: a-mux-controller {
1419 compatible = "mmio-mux";
1420 #mux-control-cells = <1>;
1421
1422 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
1423 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
1424 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
1425 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
1426 u-boot,mux-autoprobe;
1427 };
1428 };
1429
1430 muxcontroller1: emul-mux-controller {
1431 compatible = "mux-emul";
1432 #mux-control-cells = <0>;
1433 u-boot,mux-autoprobe;
1434 idle-state = <0xabcd>;
1435 };
1436
Simon Glass791a17f2020-12-16 21:20:27 -07001437 testfdtm0 {
1438 compatible = "denx,u-boot-fdtm-test";
1439 };
1440
1441 testfdtm1: testfdtm1 {
1442 compatible = "denx,u-boot-fdtm-test";
1443 };
1444
1445 testfdtm2 {
1446 compatible = "denx,u-boot-fdtm-test";
1447 };
1448
Sean Anderson79d3bba2020-09-28 10:52:23 -04001449 timer@0 {
Thomas Chou6f2cfbf2015-12-11 16:27:34 +08001450 compatible = "sandbox,timer";
1451 clock-frequency = <1000000>;
1452 };
1453
Sean Anderson79d3bba2020-09-28 10:52:23 -04001454 timer@1 {
1455 compatible = "sandbox,timer";
1456 sandbox,timebase-frequency-fallback;
1457 };
1458
Miquel Raynal80938c12018-05-15 11:57:27 +02001459 tpm2 {
1460 compatible = "sandbox,tpm2";
Eddie James1a55a7a2023-10-24 10:43:51 -05001461 memory-region = <&event_log>;
Miquel Raynal80938c12018-05-15 11:57:27 +02001462 };
1463
Simon Glasseef107e2023-02-21 06:24:51 -07001464 tpm {
1465 compatible = "google,sandbox-tpm";
1466 };
1467
Simon Glass5b968632015-05-22 15:42:15 -06001468 uart0: serial {
1469 compatible = "sandbox,serial";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001470 bootph-all;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001471 pinctrl-names = "default";
1472 pinctrl-0 = <&pinmux_uart0_pins>;
Joe Hershberger4c197242015-03-22 17:09:15 -05001473 };
1474
Simon Glass31680482015-03-25 12:23:05 -06001475 usb_0: usb@0 {
1476 compatible = "sandbox,usb";
1477 status = "disabled";
1478 hub {
1479 compatible = "sandbox,usb-hub";
1480 #address-cells = <1>;
1481 #size-cells = <0>;
1482 flash-stick {
1483 reg = <0>;
1484 compatible = "sandbox,usb-flash";
1485 };
1486 };
1487 };
1488
1489 usb_1: usb@1 {
1490 compatible = "sandbox,usb";
Mark Kettenis67748ee2021-10-23 16:58:02 +02001491 iommus = <&iommu>;
Simon Glass31680482015-03-25 12:23:05 -06001492 hub {
1493 compatible = "usb-hub";
1494 usb,device-class = <9>;
Michael Walle7c961322020-06-02 01:47:07 +02001495 #address-cells = <1>;
1496 #size-cells = <0>;
Simon Glass31680482015-03-25 12:23:05 -06001497 hub-emul {
1498 compatible = "sandbox,usb-hub";
1499 #address-cells = <1>;
1500 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -07001501 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -06001502 reg = <0>;
1503 compatible = "sandbox,usb-flash";
1504 sandbox,filepath = "testflash.bin";
1505 };
1506
Simon Glass4700fe52015-11-08 23:48:01 -07001507 flash-stick@1 {
1508 reg = <1>;
1509 compatible = "sandbox,usb-flash";
1510 sandbox,filepath = "testflash1.bin";
1511 };
1512
1513 flash-stick@2 {
1514 reg = <2>;
1515 compatible = "sandbox,usb-flash";
1516 sandbox,filepath = "testflash2.bin";
1517 };
1518
Simon Glassc0ccc722015-11-08 23:48:08 -07001519 keyb@3 {
1520 reg = <3>;
1521 compatible = "sandbox,usb-keyb";
1522 };
1523
Simon Glass31680482015-03-25 12:23:05 -06001524 };
Michael Walle7c961322020-06-02 01:47:07 +02001525
1526 usbstor@1 {
1527 reg = <1>;
1528 };
1529 usbstor@3 {
1530 reg = <3>;
1531 };
Simon Glass31680482015-03-25 12:23:05 -06001532 };
1533 };
1534
1535 usb_2: usb@2 {
1536 compatible = "sandbox,usb";
1537 status = "disabled";
1538 };
1539
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001540 spmi: spmi@0 {
1541 compatible = "sandbox,spmi";
1542 #address-cells = <0x1>;
1543 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001544 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001545 pm8916@0 {
1546 compatible = "qcom,spmi-pmic";
1547 reg = <0x0 0x1>;
1548 #address-cells = <0x1>;
1549 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001550 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001551
1552 spmi_gpios: gpios@c000 {
1553 compatible = "qcom,pm8916-gpio";
1554 reg = <0xc000 0x400>;
Caleb Connolly1edc45f2024-01-08 15:30:51 +00001555 gpio-ranges = <&spmi_gpios 0 0 4>;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001556 gpio-controller;
1557 gpio-count = <4>;
1558 #gpio-cells = <2>;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001559 };
1560 };
1561 };
maxims@google.comdaea6d42017-04-17 12:00:21 -07001562
1563 wdt0: wdt@0 {
1564 compatible = "sandbox,wdt";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +02001565 hw_margin_ms = <200>;
maxims@google.comdaea6d42017-04-17 12:00:21 -07001566 };
Rob Clarka471b672018-01-10 11:33:30 +01001567
Mario Six95922152018-08-09 14:51:19 +02001568 axi: axi@0 {
1569 compatible = "sandbox,axi";
1570 #address-cells = <0x1>;
1571 #size-cells = <0x1>;
1572 store@0 {
1573 compatible = "sandbox,sandbox_store";
1574 reg = <0x0 0x400>;
1575 };
1576 };
1577
Rob Clarka471b672018-01-10 11:33:30 +01001578 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -07001579 #address-cells = <1>;
1580 #size-cells = <1>;
Simon Glassf3455962020-01-27 08:49:43 -07001581 setting = "sunrise ohoka";
1582 other-node = "/some-bus/c-test@5";
Simon Glasse09223c2020-01-27 08:49:46 -07001583 int-values = <0x1937 72993>;
Simon Glass3c601b12020-07-07 13:12:06 -06001584 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Algapally Santosh Sagardf178992023-09-21 16:50:43 +05301585 stdout-path = "serial0:115200n8";
Rob Clarka471b672018-01-10 11:33:30 +01001586 chosen-test {
1587 compatible = "denx,u-boot-fdt-test";
1588 reg = <9 1>;
1589 };
1590 };
Mario Six35616ef2018-03-12 14:53:33 +01001591
1592 translation-test@8000 {
1593 compatible = "simple-bus";
1594 reg = <0x8000 0x4000>;
1595
1596 #address-cells = <0x2>;
1597 #size-cells = <0x1>;
1598
1599 ranges = <0 0x0 0x8000 0x1000
1600 1 0x100 0x9000 0x1000
1601 2 0x200 0xA000 0x1000
1602 3 0x300 0xB000 0x1000
1603 >;
1604
Fabien Dessenne22236e02019-05-31 15:11:30 +02001605 dma-ranges = <0 0x000 0x10000000 0x1000
1606 1 0x100 0x20000000 0x1000
1607 >;
1608
Mario Six35616ef2018-03-12 14:53:33 +01001609 dev@0,0 {
1610 compatible = "denx,u-boot-fdt-dummy";
1611 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojasa3181152018-12-03 19:37:09 +01001612 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +01001613 };
1614
1615 dev@1,100 {
1616 compatible = "denx,u-boot-fdt-dummy";
1617 reg = <1 0x100 0x1000>;
1618
1619 };
1620
1621 dev@2,200 {
1622 compatible = "denx,u-boot-fdt-dummy";
1623 reg = <2 0x200 0x1000>;
1624 };
1625
1626
1627 noxlatebus@3,300 {
1628 compatible = "simple-bus";
1629 reg = <3 0x300 0x1000>;
1630
1631 #address-cells = <0x1>;
1632 #size-cells = <0x0>;
1633
1634 dev@42 {
1635 compatible = "denx,u-boot-fdt-dummy";
1636 reg = <0x42>;
1637 };
1638 };
1639 };
Mario Six02ad6fb2018-09-27 09:19:31 +02001640
Dzmitry Sankouski54f4c832023-01-22 18:21:23 +03001641 ofnode-foreach {
1642 compatible = "foreach";
1643
1644 first {
1645 prop1 = <1>;
1646 prop2 = <2>;
1647 };
1648
1649 second {
1650 prop1 = <1>;
1651 prop2 = <2>;
1652 };
1653 };
1654
Mario Six02ad6fb2018-09-27 09:19:31 +02001655 osd {
1656 compatible = "sandbox,sandbox_osd";
1657 };
Tom Rinib93eea72018-09-30 18:16:51 -04001658
Jens Wiklander86afaa62018-09-25 16:40:16 +02001659 sandbox_tee {
1660 compatible = "sandbox,tee";
1661 };
Bin Meng1bb290d2018-10-15 02:21:26 -07001662
1663 sandbox_virtio1 {
1664 compatible = "sandbox,virtio1";
Simon Glass8de5a542023-01-17 10:47:51 -07001665 virtio-type = <4>; /* rng */
Bin Meng1bb290d2018-10-15 02:21:26 -07001666 };
1667
1668 sandbox_virtio2 {
1669 compatible = "sandbox,virtio2";
1670 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001671
Simon Glass8de5a542023-01-17 10:47:51 -07001672 sandbox-virtio-blk {
1673 compatible = "sandbox,virtio1";
1674 virtio-type = <2>; /* block */
1675 };
1676
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001677 sandbox_scmi {
1678 compatible = "sandbox,scmi-devices";
AKASHI Takahiro535a7bd2023-10-16 14:39:45 +09001679 power-domains = <&pwrdom_scmi 2>;
Etienne Carrierebf1f1322022-02-21 09:22:41 +01001680 clocks = <&clk_scmi 2>, <&clk_scmi 0>;
Etienne Carriere09665cb2022-02-21 09:22:39 +01001681 resets = <&reset_scmi 3>;
1682 regul0-supply = <&regul0_scmi>;
1683 regul1-supply = <&regul1_scmi>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001684 };
1685
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001686 pinctrl {
1687 compatible = "sandbox,pinctrl";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001688
Sean Anderson3438e3b2020-09-14 11:01:57 -04001689 pinctrl-names = "default", "alternate";
1690 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1691 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001692
Sean Anderson3438e3b2020-09-14 11:01:57 -04001693 pinctrl_gpios: gpios {
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001694 gpio0 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001695 pins = "P5";
1696 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001697 bias-pull-up;
1698 input-disable;
1699 };
1700 gpio1 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001701 pins = "P6";
1702 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001703 output-high;
1704 drive-open-drain;
1705 };
1706 gpio2 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001707 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001708 bias-pull-down;
1709 input-enable;
1710 };
1711 gpio3 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001712 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001713 bias-disable;
1714 };
1715 };
Sean Anderson3438e3b2020-09-14 11:01:57 -04001716
1717 pinctrl_i2c: i2c {
1718 groups {
1719 groups = "I2C_UART";
1720 function = "I2C";
1721 };
1722
1723 pins {
1724 pins = "P0", "P1";
1725 drive-open-drain;
1726 };
1727 };
1728
1729 pinctrl_i2s: i2s {
1730 groups = "SPI_I2S";
1731 function = "I2S";
1732 };
1733
1734 pinctrl_spi: spi {
1735 groups = "SPI_I2S";
1736 function = "SPI";
1737
1738 cs {
1739 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1740 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1741 };
1742 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001743 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001744
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001745 pinctrl-single-no-width {
1746 compatible = "pinctrl-single";
1747 reg = <0x0000 0x238>;
1748 #pinctrl-cells = <1>;
1749 pinctrl-single,function-mask = <0x7f>;
1750 };
1751
1752 pinctrl-single-pins {
1753 compatible = "pinctrl-single";
1754 reg = <0x0000 0x238>;
1755 #pinctrl-cells = <1>;
1756 pinctrl-single,register-width = <32>;
1757 pinctrl-single,function-mask = <0x7f>;
1758
1759 pinmux_pwm_pins: pinmux_pwm_pins {
1760 pinctrl-single,pins = < 0x48 0x06 >;
1761 };
1762
1763 pinmux_spi0_pins: pinmux_spi0_pins {
1764 pinctrl-single,pins = <
1765 0x190 0x0c
1766 0x194 0x0c
1767 0x198 0x23
1768 0x19c 0x0c
1769 >;
1770 };
1771
1772 pinmux_uart0_pins: pinmux_uart0_pins {
1773 pinctrl-single,pins = <
1774 0x70 0x30
1775 0x74 0x00
1776 >;
1777 };
1778 };
1779
1780 pinctrl-single-bits {
1781 compatible = "pinctrl-single";
1782 reg = <0x0000 0x50>;
1783 #pinctrl-cells = <2>;
1784 pinctrl-single,bit-per-mux;
1785 pinctrl-single,register-width = <32>;
1786 pinctrl-single,function-mask = <0xf>;
1787
1788 pinmux_i2c0_pins: pinmux_i2c0_pins {
1789 pinctrl-single,bits = <
1790 0x10 0x00002200 0x0000ff00
1791 >;
1792 };
1793
1794 pinmux_lcd_pins: pinmux_lcd_pins {
1795 pinctrl-single,bits = <
1796 0x40 0x22222200 0xffffff00
1797 0x44 0x22222222 0xffffffff
1798 0x48 0x00000022 0x000000ff
1799 0x48 0x02000000 0x0f000000
1800 0x4c 0x02000022 0x0f0000ff
1801 >;
1802 };
1803 };
1804
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001805 hwspinlock@0 {
1806 compatible = "sandbox,hwspinlock";
1807 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +01001808
1809 dma: dma {
1810 compatible = "sandbox,dma";
1811 #dma-cells = <1>;
1812
1813 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1814 dma-names = "m2m", "tx0", "rx0";
1815 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001816
Alex Marginean0649be52019-07-12 10:13:53 +03001817 /*
1818 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1819 * end of the test. If parent mdio is removed first, clean-up of the
1820 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1821 * active at the end of the test. That it turn doesn't allow the mdio
1822 * class to be destroyed, triggering an error.
1823 */
1824 mdio-mux-test {
1825 compatible = "sandbox,mdio-mux";
1826 #address-cells = <1>;
1827 #size-cells = <0>;
1828 mdio-parent-bus = <&mdio>;
1829
1830 mdio-ch-test@0 {
1831 reg = <0>;
1832 };
1833 mdio-ch-test@1 {
1834 reg = <1>;
1835 };
1836 };
1837
1838 mdio: mdio-test {
Alex Marginean0daa53a2019-06-03 19:12:28 +03001839 compatible = "sandbox,mdio";
Marek Behúnf4f1ddc2022-04-07 00:32:57 +02001840 #address-cells = <1>;
1841 #size-cells = <0>;
1842
1843 ethphy1: ethernet-phy@1 {
1844 reg = <1>;
1845 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001846 };
Sean Andersonb7860542020-06-24 06:41:12 -04001847
1848 pm-bus-test {
1849 compatible = "simple-pm-bus";
1850 clocks = <&clk_sandbox 4>;
1851 power-domains = <&pwrdom 1>;
1852 };
Sean Anderson0c1f6bf2020-06-24 06:41:14 -04001853
1854 resetc2: syscon-reset {
1855 compatible = "syscon-reset";
1856 #reset-cells = <1>;
1857 regmap = <&syscon0>;
1858 offset = <1>;
1859 mask = <0x27FFFFFF>;
1860 assert-high = <0>;
1861 };
1862
1863 syscon-reset-test {
1864 compatible = "sandbox,misc_sandbox";
1865 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1866 reset-names = "valid", "no_mask", "out_of_range";
1867 };
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301868
Simon Glass458b66a2020-11-05 06:32:05 -07001869 sysinfo {
1870 compatible = "sandbox,sysinfo-sandbox";
1871 };
1872
Sean Anderson1c830672021-04-20 10:50:58 -04001873 sysinfo-gpio {
1874 compatible = "gpio-sysinfo";
1875 gpios = <&gpio_a 15>, <&gpio_a 16>, <&gpio_a 17>;
1876 revisions = <19>, <5>;
1877 names = "rev_a", "foo";
1878 };
1879
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301880 some_regmapped-bus {
1881 #address-cells = <0x1>;
1882 #size-cells = <0x1>;
1883
1884 ranges = <0x0 0x0 0x10>;
1885 compatible = "simple-bus";
1886
1887 regmap-test_0 {
1888 reg = <0 0x10>;
1889 compatible = "sandbox,regmap_test";
1890 };
1891 };
Robert Marko9cf87122022-09-06 13:30:35 +02001892
1893 thermal {
1894 compatible = "sandbox,thermal";
1895 };
Sughosh Ganu77079e72022-10-21 18:16:05 +05301896
1897 fwu-mdata {
1898 compatible = "u-boot,fwu-mdata-gpt";
1899 fwu-mdata-store = <&mmc0>;
1900 };
Abdellatif El Khlifi6b005872023-04-17 10:11:55 +01001901
1902 nvmxip-qspi1@08000000 {
1903 compatible = "nvmxip,qspi";
1904 reg = <0x08000000 0x00200000>;
1905 lba_shift = <9>;
1906 lba = <4096>;
1907 };
1908
1909 nvmxip-qspi2@08200000 {
1910 compatible = "nvmxip,qspi";
1911 reg = <0x08200000 0x00100000>;
1912 lba_shift = <9>;
1913 lba = <2048>;
1914 };
Svyatoslav Ryhel669f5c82023-04-25 10:57:21 +03001915
1916 extcon {
1917 compatible = "sandbox,extcon";
1918 };
Abdellatif El Khlifi4970d5b2023-08-04 14:33:41 +01001919
1920 arm-ffa-emul {
1921 compatible = "sandbox,arm-ffa-emul";
1922
1923 sandbox-arm-ffa {
1924 compatible = "sandbox,arm-ffa";
1925 };
1926 };
Sean Anderson326422b2023-11-04 16:37:52 -04001927
1928 nand-controller {
1929 #address-cells = <1>;
1930 #size-cells = <0>;
1931 compatible = "sandbox,nand";
1932
1933 nand@0 {
1934 reg = <0>;
1935 nand-ecc-mode = "soft";
1936 sandbox,id = [00 e3];
1937 sandbox,erasesize = <(8 * 1024)>;
1938 sandbox,oobsize = <16>;
1939 sandbox,pagesize = <512>;
1940 sandbox,pages = <0x2000>;
1941 sandbox,err-count = <1>;
1942 sandbox,err-step-size = <512>;
1943 };
1944
1945 /* MT29F64G08AKABA */
1946 nand@1 {
1947 reg = <1>;
1948 nand-ecc-mode = "soft_bch";
1949 sandbox,id = [2C 48 00 26 89 00 00 00];
1950 sandbox,onfi = [
1951 4f 4e 46 49 0e 00 5a 00
1952 ff 01 00 00 00 00 03 00
1953 00 00 00 00 00 00 00 00
1954 00 00 00 00 00 00 00 00
1955 4d 49 43 52 4f 4e 20 20
1956 20 20 20 20 4d 54 32 39
1957 46 36 34 47 30 38 41 4b
1958 41 42 41 43 35 20 20 20
1959 2c 00 00 00 00 00 00 00
1960 00 00 00 00 00 00 00 00
1961 00 10 00 00 e0 00 00 02
1962 00 00 1c 00 80 00 00 00
1963 00 10 00 00 02 23 01 50
1964 00 01 05 01 00 00 04 00
1965 04 01 1e 00 00 00 00 00
1966 00 00 00 00 00 00 00 00
1967 0e 1f 00 1f 00 f4 01 ac
1968 0d 19 00 c8 00 00 00 00
1969 00 00 00 00 00 00 0a 07
1970 19 00 00 00 00 00 00 00
1971 00 00 00 00 01 00 01 00
1972 00 00 04 10 01 81 04 02
1973 02 01 1e 90 00 00 00 00
1974 00 00 00 00 00 00 00 00
1975 00 00 00 00 00 00 00 00
1976 00 00 00 00 00 00 00 00
1977 00 00 00 00 00 00 00 00
1978 00 00 00 00 00 00 00 00
1979 00 00 00 00 00 00 00 00
1980 00 00 00 00 00 00 00 00
1981 00 00 00 00 00 00 00 00
1982 00 00 00 00 00 03 20 7d
1983 ];
1984 sandbox,erasesize = <(512 * 1024)>;
1985 sandbox,oobsize = <224>;
1986 sandbox,pagesize = <4096>;
1987 sandbox,pages = <0x200000>;
1988 sandbox,err-count = <3>;
1989 sandbox,err-step-size = <512>;
1990 };
1991 };
Simon Glassb2c1cac2014-02-26 15:59:21 -07001992};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +02001993
1994#include "sandbox_pmic.dtsi"
Heinrich Schuchardte24fdef2021-02-18 13:01:35 +01001995#include "cros-ec-keyboard.dtsi"
Simon Glass5e135d32022-10-20 18:23:15 -06001996
1997#ifdef CONFIG_SANDBOX_VPL
1998#include "sandbox_vpl.dtsi"
1999#endif
Simon Glass61300722023-06-01 10:23:01 -06002000
Sughosh Ganu05137922024-03-27 16:19:00 +05302001#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)
2002#include "sandbox_capsule.dtsi"
2003#endif
2004
Simon Glass61300722023-06-01 10:23:01 -06002005#include "cedit.dtsi"