Blame - arch/arm/cpu/armv7/ls102xa/Kconfig - filogic/uboot

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York Sun	149eb33	2016-09-26 08:09:27 -0700	[diff] [blame]	1	config ARCH_LS1021A
York Sun	fcd0e74	2016-10-04 14:31:47 -0700	[diff] [blame]	2	bool
Tom Rini	2e15b4a	2022-11-19 18:45:10 -0500	[diff] [blame]	3	select FSL_DEVICE_DISABLE
Tom Rini	05b419e	2021-12-11 14:55:49 -0500	[diff] [blame]	4	select FSL_IFC if !QSPI_BOOT && !SD_BOOT_QSPI
Tom Rini	370e11c	2022-11-19 18:45:25 -0500	[diff] [blame]	5	select LS102XA_STREAM_ID
Michal Simek	7e7ba3b	2018-07-23 15:55:15 +0200	[diff] [blame]	6	select SYS_FSL_DDR_BE if SYS_FSL_DDR
				7	select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
Tom Rini	f4ec713	2022-07-23 13:05:09 -0400	[diff] [blame]	8	select SYS_FSL_IFC_BE
York Sun	1dc61ca	2016-12-28 08:43:41 -0800	[diff] [blame]	9	select SYS_FSL_ERRATUM_A008378
				10	select SYS_FSL_ERRATUM_A008407
Tom Rini	5618460	2022-02-25 11:19:53 -0500	[diff] [blame]	11	select SYS_FSL_ERRATUM_A008850 if SYS_FSL_DDR
Aleksandar Gerasimovski	58aeddc	2020-11-26 10:52:41 +0000	[diff] [blame]	12	select SYS_FSL_ERRATUM_A008997 if USB
Aleksandar Gerasimovski	58aeddc	2020-11-26 10:52:41 +0000	[diff] [blame]	13	select SYS_FSL_ERRATUM_A009008 if USB
York Sun	1dc61ca	2016-12-28 08:43:41 -0800	[diff] [blame]	14	select SYS_FSL_ERRATUM_A009663
Aleksandar Gerasimovski	58aeddc	2020-11-26 10:52:41 +0000	[diff] [blame]	15	select SYS_FSL_ERRATUM_A009798 if USB
York Sun	1dc61ca	2016-12-28 08:43:41 -0800	[diff] [blame]	16	select SYS_FSL_ERRATUM_A009942
York Sun	149eb33	2016-09-26 08:09:27 -0700	[diff] [blame]	17	select SYS_FSL_ERRATUM_A010315
Tom Rini	f4ec713	2022-07-23 13:05:09 -0400	[diff] [blame]	18	select SYS_FSL_ESDHC_BE
Ashish Kumar	1123406	2017-08-11 11:09:14 +0530	[diff] [blame]	19	select SYS_FSL_HAS_CCI400
York Sun	d297d39	2016-12-28 08:43:40 -0800	[diff] [blame]	20	select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR
				21	select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR
York Sun	92c36e2	2016-12-28 08:43:30 -0800	[diff] [blame]	22	select SYS_FSL_HAS_SEC
				23	select SYS_FSL_SEC_COMPAT_5
York Sun	fa419942	2016-12-28 08:43:31 -0800	[diff] [blame]	24	select SYS_FSL_SEC_LE
Michal Simek	7e7ba3b	2018-07-23 15:55:15 +0200	[diff] [blame]	25	select SYS_FSL_SRDS_1
				26	select SYS_HAS_SERDES
Tom Rini	1a19588	2021-08-18 23:12:33 -0400	[diff] [blame]	27	select SYS_I2C_MXC
Michal Simek	7e7ba3b	2018-07-23 15:55:15 +0200	[diff] [blame]	28	imply CMD_PCI
Simon Glass	0e5faf0	2017-06-14 21:28:21 -0600	[diff] [blame]	29	imply SCSI
Tuomas Tynkkynen	edf9f62	2017-12-08 15:36:19 +0200	[diff] [blame]	30	imply SCSI_AHCI
York Sun	4de7e93	2016-09-26 08:09:29 -0700	[diff] [blame]	31
York Sun	4dd8c61	2016-10-04 14:31:48 -0700	[diff] [blame]	32	menu "LS102xA architecture"
				33	depends on ARCH_LS1021A
				34
Tom Rini	2e15b4a	2022-11-19 18:45:10 -0500	[diff] [blame]	35	config FSL_DEVICE_DISABLE
				36	bool
				37
York Sun	4de7e93	2016-09-26 08:09:29 -0700	[diff] [blame]	38	config LS1_DEEP_SLEEP
York Sun	fcd0e74	2016-10-04 14:31:47 -0700	[diff] [blame]	39	bool "Deep sleep"
York Sun	4dd8c61	2016-10-04 14:31:48 -0700	[diff] [blame]	40
Tom Rini	370e11c	2022-11-19 18:45:25 -0500	[diff] [blame]	41	config LS102XA_STREAM_ID
				42	bool
				43
York Sun	f188d22	2016-10-04 14:45:01 -0700	[diff] [blame]	44	config MAX_CPUS
				45	int "Maximum number of CPUs permitted for LS102xA"
York Sun	f188d22	2016-10-04 14:45:01 -0700	[diff] [blame]	46	default 2
				47	help
				48	Set this number to the maximum number of possible CPUs in the SoC.
				49	SoCs may have multiple clusters with each cluster may have multiple
				50	ports. If some ports are reserved but higher ports are used for
				51	cores, count the reserved ports. This will allocate enough memory
				52	in spin table to properly handle all cores.
				53
Tom Rini	d7b177e	2022-12-02 16:42:40 -0500	[diff] [blame]	54	config PEN_ADDR_BIG_ENDIAN
				55	bool
				56
Ashish Kumar	1123406	2017-08-11 11:09:14 +0530	[diff] [blame]	57	config SYS_CCI400_OFFSET
				58	hex "Offset for CCI400 base"
				59	depends on SYS_FSL_HAS_CCI400
				60	default 0x180000
				61	help
				62	Offset for CCI400 base.
				63	CCI400 base addr = CCSRBAR + CCI400_OFFSET
				64
Alison Wang	d6be97b	2019-03-06 14:49:14 +0800	[diff] [blame]	65	config SYS_FSL_ERRATUM_A008850
				66	bool
				67	help
				68	Workaround for DDR erratum A008850
				69
Ran Wang	373a7b0	2017-09-04 18:46:54 +0800	[diff] [blame]	70	config SYS_FSL_ERRATUM_A008997
				71	bool
				72	help
				73	Workaround for USB PHY erratum A008997
				74
Ran Wang	2eb4898	2017-09-04 18:46:55 +0800	[diff] [blame]	75	config SYS_FSL_ERRATUM_A009007
				76	bool
				77	help
				78	Workaround for USB PHY erratum A009007
				79
Ran Wang	1509c8a	2017-09-04 18:46:52 +0800	[diff] [blame]	80	config SYS_FSL_ERRATUM_A009008
				81	bool
				82	help
				83	Workaround for USB PHY erratum A009008
				84
Ran Wang	d2b711b7	2017-09-04 18:46:53 +0800	[diff] [blame]	85	config SYS_FSL_ERRATUM_A009798
				86	bool
				87	help
				88	Workaround for USB PHY erratum A009798
				89
York Sun	4dd8c61	2016-10-04 14:31:48 -0700	[diff] [blame]	90	config SYS_FSL_ERRATUM_A010315
				91	bool "Workaround for PCIe erratum A010315"
				92
Ashish Kumar	1123406	2017-08-11 11:09:14 +0530	[diff] [blame]	93	config SYS_FSL_HAS_CCI400
				94	bool
				95
York Sun	1dc61ca	2016-12-28 08:43:41 -0800	[diff] [blame]	96	config SYS_FSL_ERRATUM_A008407
				97	bool
				98
Mario Kicherer	03ee72a	2023-02-01 14:16:22 +0800	[diff] [blame]	99	config SYS_FSL_QSPI_SKIP_CLKSEL
				100	bool "Skip setting QSPI clock during SoC init"
				101	default 0
				102	help
				103	To improve startup times when booting from QSPI flash, the QSPI
				104	frequency can be set very early in the boot process. If this option
				105	is enabled, the QSPI frequency will not be changed by U-Boot during
				106	SoC initialization.
				107
York Sun	4dd8c61	2016-10-04 14:31:48 -0700	[diff] [blame]	108	endmenu