| commit | 1345c9ea6a6b44dc7e3b3945cb1c61a54f31b72c | [log] [tgz] |
|---|---|---|
| author | Xingyu Wu <xingyu.wu@starfivetech.com> | Fri Jul 07 18:50:09 2023 +0800 |
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | Mon Jul 24 13:21:06 2023 +0800 |
| tree | 8ccc2d154642e6b2e3f3a3b76a93e6957f495904 | |
| parent | 7ae81bb4715594fa334db8c6eb3505f22f7bc0c3 [diff] |
riscv: dts: jh7110: Add clock source from PLL Change the PLL clock source from syscrg to sys_syscon child node. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Reviewed-by: Torsten Duwe <duwe@suse.de> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>