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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Rohit Mathew3dc3cad2022-11-11 18:45:11 +00002 * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
Varun Wadekar423045d2022-05-25 12:45:22 +01003 * Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01004 *
dp-armfa3cf0b2017-05-03 09:38:09 +01005 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01006 */
7
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +01008#ifndef ARCH_H
9#define ARCH_H
Achin Gupta4f6ad662013-10-25 09:08:21 +010010
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <lib/utils_def.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010012
13/*******************************************************************************
14 * MIDR bit definitions
15 ******************************************************************************/
Varun Wadekarc6a11f62017-05-25 18:04:48 -070016#define MIDR_IMPL_MASK U(0xff)
17#define MIDR_IMPL_SHIFT U(0x18)
18#define MIDR_VAR_SHIFT U(20)
19#define MIDR_VAR_BITS U(4)
20#define MIDR_VAR_MASK U(0xf)
21#define MIDR_REV_SHIFT U(0)
22#define MIDR_REV_BITS U(4)
23#define MIDR_REV_MASK U(0xf)
24#define MIDR_PN_MASK U(0xfff)
25#define MIDR_PN_SHIFT U(0x4)
Achin Gupta4f6ad662013-10-25 09:08:21 +010026
27/*******************************************************************************
28 * MPIDR macros
29 ******************************************************************************/
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010030#define MPIDR_MT_MASK (ULL(1) << 24)
Achin Gupta4f6ad662013-10-25 09:08:21 +010031#define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK
Varun Wadekarc6a11f62017-05-25 18:04:48 -070032#define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS)
33#define MPIDR_AFFINITY_BITS U(8)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010034#define MPIDR_AFFLVL_MASK ULL(0xff)
Varun Wadekarc6a11f62017-05-25 18:04:48 -070035#define MPIDR_AFF0_SHIFT U(0)
36#define MPIDR_AFF1_SHIFT U(8)
37#define MPIDR_AFF2_SHIFT U(16)
38#define MPIDR_AFF3_SHIFT U(32)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000039#define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010040#define MPIDR_AFFINITY_MASK ULL(0xff00ffffff)
Varun Wadekarc6a11f62017-05-25 18:04:48 -070041#define MPIDR_AFFLVL_SHIFT U(3)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000042#define MPIDR_AFFLVL0 ULL(0x0)
43#define MPIDR_AFFLVL1 ULL(0x1)
44#define MPIDR_AFFLVL2 ULL(0x2)
45#define MPIDR_AFFLVL3 ULL(0x3)
46#define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000047#define MPIDR_AFFLVL0_VAL(mpidr) \
Antonio Nino Diaz34235a32018-07-11 16:45:49 +010048 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK)
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000049#define MPIDR_AFFLVL1_VAL(mpidr) \
Antonio Nino Diaz34235a32018-07-11 16:45:49 +010050 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK)
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000051#define MPIDR_AFFLVL2_VAL(mpidr) \
Antonio Nino Diaz34235a32018-07-11 16:45:49 +010052 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK)
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000053#define MPIDR_AFFLVL3_VAL(mpidr) \
Antonio Nino Diaz34235a32018-07-11 16:45:49 +010054 (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK)
Soby Mathewe2b2d8f2014-12-04 14:14:12 +000055/*
56 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to
57 * add one while using this macro to define array sizes.
58 * TODO: Support only the first 3 affinity levels for now.
59 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070060#define MPIDR_MAX_AFFLVL U(2)
Achin Gupta4f6ad662013-10-25 09:08:21 +010061
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000062#define MPID_MASK (MPIDR_MT_MASK | \
63 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \
64 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \
65 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \
66 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT))
67
68#define MPIDR_AFF_ID(mpid, n) \
69 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK)
70
71/*
72 * An invalid MPID. This value can be used by functions that return an MPID to
73 * indicate an error.
74 */
75#define INVALID_MPID U(0xFFFFFFFF)
Achin Gupta4f6ad662013-10-25 09:08:21 +010076
77/*******************************************************************************
Manish Pandey067087f2023-12-08 20:13:29 +000078 * Definitions for Exception vector offsets
79 ******************************************************************************/
80#define CURRENT_EL_SP0 0x0
81#define CURRENT_EL_SPX 0x200
82#define LOWER_EL_AARCH64 0x400
83#define LOWER_EL_AARCH32 0x600
84
85#define SYNC_EXCEPTION 0x0
86#define IRQ_EXCEPTION 0x80
87#define FIQ_EXCEPTION 0x100
88#define SERROR_EXCEPTION 0x180
89
90/*******************************************************************************
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010091 * Definitions for CPU system register interface to GICv3
92 ******************************************************************************/
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000093#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7
94#define ICC_SGI1R S3_0_C12_C11_5
Florian Lugoud4e25032021-09-08 12:40:24 +020095#define ICC_ASGI1R S3_0_C12_C11_6
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000096#define ICC_SRE_EL1 S3_0_C12_C12_5
97#define ICC_SRE_EL2 S3_4_C12_C9_5
98#define ICC_SRE_EL3 S3_6_C12_C12_5
99#define ICC_CTLR_EL1 S3_0_C12_C12_4
100#define ICC_CTLR_EL3 S3_6_C12_C12_4
101#define ICC_PMR_EL1 S3_0_C4_C6_0
102#define ICC_RPR_EL1 S3_0_C12_C11_3
103#define ICC_IGRPEN1_EL3 S3_6_c12_c12_7
104#define ICC_IGRPEN0_EL1 S3_0_c12_c12_6
105#define ICC_HPPIR0_EL1 S3_0_c12_c8_2
106#define ICC_HPPIR1_EL1 S3_0_c12_c12_2
107#define ICC_IAR0_EL1 S3_0_c12_c8_0
108#define ICC_IAR1_EL1 S3_0_c12_c12_0
109#define ICC_EOIR0_EL1 S3_0_c12_c8_1
110#define ICC_EOIR1_EL1 S3_0_c12_c12_1
111#define ICC_SGI0R_EL1 S3_0_c12_c11_7
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100112
113/*******************************************************************************
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000114 * Definitions for EL2 system registers for save/restore routine
115 ******************************************************************************/
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000116#define CNTPOFF_EL2 S3_4_C14_C0_6
117#define HAFGRTR_EL2 S3_4_C3_C1_6
118#define HDFGRTR_EL2 S3_4_C3_C1_4
119#define HDFGWTR_EL2 S3_4_C3_C1_5
120#define HFGITR_EL2 S3_4_C1_C1_6
121#define HFGRTR_EL2 S3_4_C1_C1_4
122#define HFGWTR_EL2 S3_4_C1_C1_5
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000123#define ICH_HCR_EL2 S3_4_C12_C11_0
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000124#define ICH_VMCR_EL2 S3_4_C12_C11_7
Varun Wadekar423045d2022-05-25 12:45:22 +0100125#define MPAMVPM0_EL2 S3_4_C10_C6_0
126#define MPAMVPM1_EL2 S3_4_C10_C6_1
127#define MPAMVPM2_EL2 S3_4_C10_C6_2
128#define MPAMVPM3_EL2 S3_4_C10_C6_3
129#define MPAMVPM4_EL2 S3_4_C10_C6_4
130#define MPAMVPM5_EL2 S3_4_C10_C6_5
131#define MPAMVPM6_EL2 S3_4_C10_C6_6
132#define MPAMVPM7_EL2 S3_4_C10_C6_7
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000133#define MPAMVPMV_EL2 S3_4_C10_C4_1
Max Shvetsovc9e2c922020-02-17 16:15:47 +0000134#define TRFCR_EL2 S3_4_C1_C2_1
Andre Przywaraedc449d2023-01-27 14:09:20 +0000135#define VNCR_EL2 S3_4_C2_C2_0
Max Shvetsovc9e2c922020-02-17 16:15:47 +0000136#define PMSCR_EL2 S3_4_C9_C9_0
137#define TFSR_EL2 S3_4_C5_C6_0
Andre Przywara98908b32022-11-17 16:42:09 +0000138#define CONTEXTIDR_EL2 S3_4_C13_C0_1
139#define TTBR1_EL2 S3_4_C2_C0_1
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000140
141/*******************************************************************************
Achin Guptac2b43af2013-10-31 11:27:43 +0000142 * Generic timer memory mapped registers & offsets
143 ******************************************************************************/
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700144#define CNTCR_OFF U(0x000)
Yann Gautier007d7452019-04-17 13:47:07 +0200145#define CNTCV_OFF U(0x008)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700146#define CNTFID_OFF U(0x020)
Achin Guptac2b43af2013-10-31 11:27:43 +0000147
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700148#define CNTCR_EN (U(1) << 0)
149#define CNTCR_HDBG (U(1) << 1)
Sandrine Bailleux3fa98472014-03-31 11:25:18 +0100150#define CNTCR_FCREQ(x) ((x) << 8)
Achin Guptac2b43af2013-10-31 11:27:43 +0000151
152/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +0100153 * System register bit definitions
154 ******************************************************************************/
155/* CLIDR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700156#define LOUIS_SHIFT U(21)
157#define LOC_SHIFT U(24)
Alexei Fedorova95a5892019-07-29 17:22:53 +0100158#define CTYPE_SHIFT(n) U(3 * (n - 1))
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700159#define CLIDR_FIELD_WIDTH U(3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100160
161/* CSSELR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700162#define LEVEL_SHIFT U(1)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100163
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100164/* Data cache set/way op type defines */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700165#define DCISW U(0x0)
166#define DCCISW U(0x1)
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +0000167#if ERRATA_A53_827319
168#define DCCSW DCCISW
169#else
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700170#define DCCSW U(0x2)
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +0000171#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100172
Andre Przywara0dda4242023-04-18 16:58:36 +0100173#define ID_REG_FIELD_MASK ULL(0xf)
174
Achin Gupta4f6ad662013-10-25 09:08:21 +0100175/* ID_AA64PFR0_EL1 definitions */
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000176#define ID_AA64PFR0_EL0_SHIFT U(0)
177#define ID_AA64PFR0_EL1_SHIFT U(4)
178#define ID_AA64PFR0_EL2_SHIFT U(8)
179#define ID_AA64PFR0_EL3_SHIFT U(12)
180
181#define ID_AA64PFR0_AMU_SHIFT U(44)
182#define ID_AA64PFR0_AMU_MASK ULL(0xf)
183#define ID_AA64PFR0_AMU_NOT_SUPPORTED U(0x0)
184#define ID_AA64PFR0_AMU_V1 ULL(0x1)
185#define ID_AA64PFR0_AMU_V1P1 U(0x2)
186
187#define ID_AA64PFR0_ELX_MASK ULL(0xf)
188
189#define ID_AA64PFR0_GIC_SHIFT U(24)
190#define ID_AA64PFR0_GIC_WIDTH U(4)
191#define ID_AA64PFR0_GIC_MASK ULL(0xf)
192
193#define ID_AA64PFR0_SVE_SHIFT U(32)
194#define ID_AA64PFR0_SVE_MASK ULL(0xf)
195#define ID_AA64PFR0_SVE_SUPPORTED ULL(0x1)
196#define ID_AA64PFR0_SVE_LENGTH U(4)
197
198#define ID_AA64PFR0_SEL2_SHIFT U(36)
199#define ID_AA64PFR0_SEL2_MASK ULL(0xf)
200
201#define ID_AA64PFR0_MPAM_SHIFT U(40)
202#define ID_AA64PFR0_MPAM_MASK ULL(0xf)
203
204#define ID_AA64PFR0_DIT_SHIFT U(48)
205#define ID_AA64PFR0_DIT_MASK ULL(0xf)
206#define ID_AA64PFR0_DIT_LENGTH U(4)
207#define ID_AA64PFR0_DIT_SUPPORTED U(1)
208
209#define ID_AA64PFR0_CSV2_SHIFT U(56)
210#define ID_AA64PFR0_CSV2_MASK ULL(0xf)
211#define ID_AA64PFR0_CSV2_LENGTH U(4)
212#define ID_AA64PFR0_CSV2_2_SUPPORTED ULL(0x2)
Sona Mathew3b84c962023-10-25 16:48:19 -0500213#define ID_AA64PFR0_CSV2_3_SUPPORTED ULL(0x3)
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000214
Zelalem Aweke79e3d292021-07-08 16:51:14 -0500215#define ID_AA64PFR0_FEAT_RME_SHIFT U(52)
216#define ID_AA64PFR0_FEAT_RME_MASK ULL(0xf)
217#define ID_AA64PFR0_FEAT_RME_LENGTH U(4)
218#define ID_AA64PFR0_FEAT_RME_NOT_SUPPORTED U(0)
219#define ID_AA64PFR0_FEAT_RME_V1 U(1)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100220
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000221#define ID_AA64PFR0_RAS_SHIFT U(28)
222#define ID_AA64PFR0_RAS_MASK ULL(0xf)
223#define ID_AA64PFR0_RAS_NOT_SUPPORTED ULL(0x0)
224#define ID_AA64PFR0_RAS_LENGTH U(4)
225
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100226/* Exception level handling */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100227#define EL_IMPL_NONE ULL(0)
228#define EL_IMPL_A64ONLY ULL(1)
229#define EL_IMPL_A64_A32 ULL(2)
Jeenu Viswambharan2a9b8822017-02-21 14:40:44 +0000230
Manish V Badarkhef7ee0642021-07-07 16:27:10 +0100231/* ID_AA64DFR0_EL1.TraceVer definitions */
232#define ID_AA64DFR0_TRACEVER_SHIFT U(4)
233#define ID_AA64DFR0_TRACEVER_MASK ULL(0xf)
234#define ID_AA64DFR0_TRACEVER_SUPPORTED ULL(1)
235#define ID_AA64DFR0_TRACEVER_LENGTH U(4)
Manish V Badarkhe8ce33942021-07-18 02:26:27 +0100236#define ID_AA64DFR0_TRACEFILT_SHIFT U(40)
237#define ID_AA64DFR0_TRACEFILT_MASK U(0xf)
238#define ID_AA64DFR0_TRACEFILT_SUPPORTED U(1)
239#define ID_AA64DFR0_TRACEFILT_LENGTH U(4)
Boyan Karatotev05504ba2023-02-15 13:21:50 +0000240#define ID_AA64DFR0_PMUVER_LENGTH U(4)
241#define ID_AA64DFR0_PMUVER_SHIFT U(8)
242#define ID_AA64DFR0_PMUVER_MASK U(0xf)
243#define ID_AA64DFR0_PMUVER_PMUV3 U(1)
244#define ID_AA64DFR0_PMUVER_PMUV3P7 U(7)
245#define ID_AA64DFR0_PMUVER_IMP_DEF U(0xf)
Manish V Badarkhef7ee0642021-07-07 16:27:10 +0100246
Manish Pandey5cfe5152024-01-09 15:55:20 +0000247/* ID_AA64DFR0_EL1.SEBEP definitions */
248#define ID_AA64DFR0_SEBEP_SHIFT U(24)
249#define ID_AA64DFR0_SEBEP_MASK ULL(0xf)
250#define SEBEP_IMPLEMENTED ULL(1)
251
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100252/* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000253#define ID_AA64DFR0_PMS_SHIFT U(32)
254#define ID_AA64DFR0_PMS_MASK ULL(0xf)
255#define ID_AA64DFR0_SPE_SUPPORTED ULL(0x1)
256#define ID_AA64DFR0_SPE_NOT_SUPPORTED ULL(0x0)
Achin Gupta92712a52015-09-03 14:18:02 +0100257
Manish V Badarkhe20df29c2021-07-02 09:10:56 +0100258/* ID_AA64DFR0_EL1.TraceBuffer definitions */
259#define ID_AA64DFR0_TRACEBUFFER_SHIFT U(44)
260#define ID_AA64DFR0_TRACEBUFFER_MASK ULL(0xf)
261#define ID_AA64DFR0_TRACEBUFFER_SUPPORTED ULL(1)
262
Javier Almansa Sobrinof3a4c542020-11-23 18:38:15 +0000263/* ID_AA64DFR0_EL1.MTPMU definitions (for ARMv8.6+) */
264#define ID_AA64DFR0_MTPMU_SHIFT U(48)
265#define ID_AA64DFR0_MTPMU_MASK ULL(0xf)
266#define ID_AA64DFR0_MTPMU_SUPPORTED ULL(1)
Boyan Karatotev677ed8a2023-02-16 09:45:29 +0000267#define ID_AA64DFR0_MTPMU_DISABLED ULL(15)
Javier Almansa Sobrinof3a4c542020-11-23 18:38:15 +0000268
johpow0181865962022-01-28 17:06:20 -0600269/* ID_AA64DFR0_EL1.BRBE definitions */
270#define ID_AA64DFR0_BRBE_SHIFT U(52)
271#define ID_AA64DFR0_BRBE_MASK ULL(0xf)
272#define ID_AA64DFR0_BRBE_SUPPORTED ULL(1)
273
Manish Pandey5cfe5152024-01-09 15:55:20 +0000274/* ID_AA64DFR1_EL1 definitions */
275#define ID_AA64DFR1_EBEP_SHIFT U(48)
276#define ID_AA64DFR1_EBEP_MASK ULL(0xf)
277#define EBEP_IMPLEMENTED ULL(1)
278
Tomas Pilar6fd816e2020-10-28 15:34:12 +0000279/* ID_AA64ISAR0_EL1 definitions */
johpow019baade32021-07-08 14:14:00 -0500280#define ID_AA64ISAR0_RNDR_SHIFT U(60)
281#define ID_AA64ISAR0_RNDR_MASK ULL(0xf)
Tomas Pilar6fd816e2020-10-28 15:34:12 +0000282
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000283/* ID_AA64ISAR1_EL1 definitions */
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000284#define ID_AA64ISAR1_EL1 S3_0_C0_C6_1
285
286#define ID_AA64ISAR1_GPI_SHIFT U(28)
287#define ID_AA64ISAR1_GPI_MASK ULL(0xf)
288#define ID_AA64ISAR1_GPA_SHIFT U(24)
289#define ID_AA64ISAR1_GPA_MASK ULL(0xf)
290
291#define ID_AA64ISAR1_API_SHIFT U(8)
292#define ID_AA64ISAR1_API_MASK ULL(0xf)
293#define ID_AA64ISAR1_APA_SHIFT U(4)
294#define ID_AA64ISAR1_APA_MASK ULL(0xf)
295
296#define ID_AA64ISAR1_SB_SHIFT U(36)
297#define ID_AA64ISAR1_SB_MASK ULL(0xf)
298#define ID_AA64ISAR1_SB_SUPPORTED ULL(0x1)
299#define ID_AA64ISAR1_SB_NOT_SUPPORTED ULL(0x0)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000300
Juan Pablo Condee089a172022-06-29 17:44:43 -0400301/* ID_AA64ISAR2_EL1 definitions */
302#define ID_AA64ISAR2_EL1 S3_0_C0_C6_2
303
Maksims Svecovsdf4ad842023-03-24 13:05:09 +0000304/* ID_AA64PFR2_EL1 definitions */
305#define ID_AA64PFR2_EL1 S3_0_C0_C4_2
306
Juan Pablo Condee089a172022-06-29 17:44:43 -0400307#define ID_AA64ISAR2_GPA3_SHIFT U(8)
308#define ID_AA64ISAR2_GPA3_MASK ULL(0xf)
309
310#define ID_AA64ISAR2_APA3_SHIFT U(12)
311#define ID_AA64ISAR2_APA3_MASK ULL(0xf)
312
Antonio Nino Diazc326c342019-01-11 11:20:10 +0000313/* ID_AA64MMFR0_EL1 definitions */
314#define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0)
315#define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf)
316
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700317#define PARANGE_0000 U(32)
318#define PARANGE_0001 U(36)
319#define PARANGE_0010 U(40)
320#define PARANGE_0011 U(42)
321#define PARANGE_0100 U(44)
322#define PARANGE_0101 U(48)
Antonio Nino Diazb9ef6642017-11-17 09:52:53 +0000323#define PARANGE_0110 U(52)
Antonio Nino Diazd1beee22016-12-13 15:28:54 +0000324
Jimmy Brisson83573892020-04-16 10:48:02 -0500325#define ID_AA64MMFR0_EL1_ECV_SHIFT U(60)
326#define ID_AA64MMFR0_EL1_ECV_MASK ULL(0xf)
327#define ID_AA64MMFR0_EL1_ECV_NOT_SUPPORTED ULL(0x0)
328#define ID_AA64MMFR0_EL1_ECV_SUPPORTED ULL(0x1)
329#define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2)
330
Jimmy Brissonecc3c672020-04-16 10:47:56 -0500331#define ID_AA64MMFR0_EL1_FGT_SHIFT U(56)
332#define ID_AA64MMFR0_EL1_FGT_MASK ULL(0xf)
333#define ID_AA64MMFR0_EL1_FGT_SUPPORTED ULL(0x1)
334#define ID_AA64MMFR0_EL1_FGT_NOT_SUPPORTED ULL(0x0)
335
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100336#define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100337#define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf)
338#define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0)
Javier Almansa Sobrino8c8107e2023-05-03 12:16:11 +0100339#define ID_AA64MMFR0_EL1_TGRAN4_52B_SUPPORTED ULL(0x1)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100340#define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100341
342#define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100343#define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf)
344#define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED ULL(0x0)
345#define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED ULL(0xf)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100346
347#define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100348#define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf)
349#define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1)
350#define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0)
Javier Almansa Sobrino8c8107e2023-05-03 12:16:11 +0100351#define ID_AA64MMFR0_EL1_TGRAN16_52B_SUPPORTED ULL(0x2)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100352
johpow013e24c162020-04-22 14:05:13 -0500353/* ID_AA64MMFR1_EL1 definitions */
354#define ID_AA64MMFR1_EL1_TWED_SHIFT U(32)
355#define ID_AA64MMFR1_EL1_TWED_MASK ULL(0xf)
356#define ID_AA64MMFR1_EL1_TWED_SUPPORTED ULL(0x1)
357#define ID_AA64MMFR1_EL1_TWED_NOT_SUPPORTED ULL(0x0)
358
Alexei Fedorovc082f032020-11-25 14:07:05 +0000359#define ID_AA64MMFR1_EL1_PAN_SHIFT U(20)
360#define ID_AA64MMFR1_EL1_PAN_MASK ULL(0xf)
361#define ID_AA64MMFR1_EL1_PAN_NOT_SUPPORTED ULL(0x0)
362#define ID_AA64MMFR1_EL1_PAN_SUPPORTED ULL(0x1)
363#define ID_AA64MMFR1_EL1_PAN2_SUPPORTED ULL(0x2)
364#define ID_AA64MMFR1_EL1_PAN3_SUPPORTED ULL(0x3)
365
Daniel Boulby44b43332020-11-25 16:36:46 +0000366#define ID_AA64MMFR1_EL1_VHE_SHIFT U(8)
367#define ID_AA64MMFR1_EL1_VHE_MASK ULL(0xf)
368
johpow019baade32021-07-08 14:14:00 -0500369#define ID_AA64MMFR1_EL1_HCX_SHIFT U(40)
370#define ID_AA64MMFR1_EL1_HCX_MASK ULL(0xf)
371#define ID_AA64MMFR1_EL1_HCX_SUPPORTED ULL(0x1)
372#define ID_AA64MMFR1_EL1_HCX_NOT_SUPPORTED ULL(0x0)
johpow01f91e59f2021-08-04 19:38:18 -0500373
Antonio Nino Diazc326c342019-01-11 11:20:10 +0000374/* ID_AA64MMFR2_EL1 definitions */
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000375#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2
Sathees Balya74155972019-01-25 11:36:01 +0000376
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000377#define ID_AA64MMFR2_EL1_ST_SHIFT U(28)
378#define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf)
Sathees Balya74155972019-01-25 11:36:01 +0000379
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000380#define ID_AA64MMFR2_EL1_CCIDX_SHIFT U(20)
381#define ID_AA64MMFR2_EL1_CCIDX_MASK ULL(0xf)
382#define ID_AA64MMFR2_EL1_CCIDX_LENGTH U(4)
383
Manish Pandey5cfe5152024-01-09 15:55:20 +0000384#define ID_AA64MMFR2_EL1_UAO_SHIFT U(4)
385#define ID_AA64MMFR2_EL1_UAO_MASK ULL(0xf)
386
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000387#define ID_AA64MMFR2_EL1_CNP_SHIFT U(0)
388#define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf)
johpow0174b7e442021-12-01 13:18:30 -0600389
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000390#define ID_AA64MMFR2_EL1_NV_SHIFT U(24)
391#define ID_AA64MMFR2_EL1_NV_MASK ULL(0xf)
392#define ID_AA64MMFR2_EL1_NV_NOT_SUPPORTED ULL(0x0)
393#define ID_AA64MMFR2_EL1_NV_SUPPORTED ULL(0x1)
394#define ID_AA64MMFR2_EL1_NV2_SUPPORTED ULL(0x2)
Antonio Nino Diazc326c342019-01-11 11:20:10 +0000395
Mark Brownc37eee72023-03-14 20:13:03 +0000396/* ID_AA64MMFR3_EL1 definitions */
397#define ID_AA64MMFR3_EL1 S3_0_C0_C7_3
398
Mark Brown293a6612023-03-14 20:48:43 +0000399#define ID_AA64MMFR3_EL1_S2POE_SHIFT U(20)
400#define ID_AA64MMFR3_EL1_S2POE_MASK ULL(0xf)
401
402#define ID_AA64MMFR3_EL1_S1POE_SHIFT U(16)
403#define ID_AA64MMFR3_EL1_S1POE_MASK ULL(0xf)
404
405#define ID_AA64MMFR3_EL1_S2PIE_SHIFT U(12)
406#define ID_AA64MMFR3_EL1_S2PIE_MASK ULL(0xf)
407
408#define ID_AA64MMFR3_EL1_S1PIE_SHIFT U(8)
409#define ID_AA64MMFR3_EL1_S1PIE_MASK ULL(0xf)
410
Mark Brownc37eee72023-03-14 20:13:03 +0000411#define ID_AA64MMFR3_EL1_TCRX_SHIFT U(0)
412#define ID_AA64MMFR3_EL1_TCRX_MASK ULL(0xf)
413
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000414/* ID_AA64PFR1_EL1 definitions */
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000415
Alexei Fedorov90f2e882019-05-24 12:17:09 +0100416#define ID_AA64PFR1_EL1_BT_SHIFT U(0)
417#define ID_AA64PFR1_EL1_BT_MASK ULL(0xf)
Alexei Fedorov90f2e882019-05-24 12:17:09 +0100418#define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */
419
Manish Pandey5cfe5152024-01-09 15:55:20 +0000420#define ID_AA64PFR1_EL1_SSBS_SHIFT U(4)
421#define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf)
422#define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */
423
Soby Mathew830f0ad2019-07-12 09:23:38 +0100424#define ID_AA64PFR1_EL1_MTE_SHIFT U(8)
425#define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf)
426
Juan Pablo Conde42305f22022-07-12 16:40:29 -0400427#define ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT U(28)
428#define ID_AA64PFR1_EL1_RNDR_TRAP_MASK U(0xf)
429
Manish Pandey5cfe5152024-01-09 15:55:20 +0000430#define ID_AA64PFR1_EL1_NMI_SHIFT U(36)
431#define ID_AA64PFR1_EL1_NMI_MASK ULL(0xf)
432#define NMI_IMPLEMENTED ULL(1)
433
434#define ID_AA64PFR1_EL1_GCS_SHIFT U(44)
435#define ID_AA64PFR1_EL1_GCS_MASK ULL(0xf)
436#define GCS_IMPLEMENTED ULL(1)
437
Juan Pablo Conde42305f22022-07-12 16:40:29 -0400438#define ID_AA64PFR1_EL1_RNG_TRAP_SUPPORTED ULL(0x1)
439#define ID_AA64PFR1_EL1_RNG_TRAP_NOT_SUPPORTED ULL(0x0)
440
Maksims Svecovsdf4ad842023-03-24 13:05:09 +0000441/* ID_AA64PFR2_EL1 definitions */
442#define ID_AA64PFR2_EL1_MTEPERM_SHIFT U(0)
443#define ID_AA64PFR2_EL1_MTEPERM_MASK ULL(0xf)
444
445#define ID_AA64PFR2_EL1_MTESTOREONLY_SHIFT U(4)
446#define ID_AA64PFR2_EL1_MTESTOREONLY_MASK ULL(0xf)
447
448#define ID_AA64PFR2_EL1_MTEFAR_SHIFT U(8)
449#define ID_AA64PFR2_EL1_MTEFAR_MASK ULL(0xf)
450
Andre Przywara870627e2023-01-27 12:25:49 +0000451#define VDISR_EL2 S3_4_C12_C1_1
452#define VSESR_EL2 S3_4_C5_C2_3
453
Alexei Fedorovaf54f6e2020-12-01 13:22:25 +0000454/* Memory Tagging Extension is not implemented */
455#define MTE_UNIMPLEMENTED U(0)
456/* FEAT_MTE: MTE instructions accessible at EL0 are implemented */
457#define MTE_IMPLEMENTED_EL0 U(1)
458/* FEAT_MTE2: Full MTE is implemented */
459#define MTE_IMPLEMENTED_ELX U(2)
460/*
461 * FEAT_MTE3: MTE is implemented with support for
462 * asymmetric Tag Check Fault handling
463 */
464#define MTE_IMPLEMENTED_ASY U(3)
Soby Mathew830f0ad2019-07-12 09:23:38 +0100465
Alexei Fedorov19933552020-05-26 13:16:41 +0100466#define ID_AA64PFR1_MPAM_FRAC_SHIFT ULL(16)
467#define ID_AA64PFR1_MPAM_FRAC_MASK ULL(0xf)
468
Jayanth Dodderi Chidanand605419a2023-03-06 23:56:14 +0000469#define ID_AA64PFR1_EL1_SME_SHIFT U(24)
470#define ID_AA64PFR1_EL1_SME_MASK ULL(0xf)
Juan Pablo Condeefdfe362023-08-14 16:20:52 -0500471#define ID_AA64PFR1_EL1_SME_WIDTH U(4)
Jayanth Dodderi Chidanand605419a2023-03-06 23:56:14 +0000472#define ID_AA64PFR1_EL1_SME_NOT_SUPPORTED ULL(0x0)
473#define ID_AA64PFR1_EL1_SME_SUPPORTED ULL(0x1)
Jayanth Dodderi Chidanandcfe053a2022-11-08 10:31:07 +0000474#define ID_AA64PFR1_EL1_SME2_SUPPORTED ULL(0x2)
johpow019baade32021-07-08 14:14:00 -0500475
Achin Gupta4f6ad662013-10-25 09:08:21 +0100476/* ID_PFR1_EL1 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700477#define ID_PFR1_VIRTEXT_SHIFT U(12)
478#define ID_PFR1_VIRTEXT_MASK U(0xf)
Antonio Nino Diaz34235a32018-07-11 16:45:49 +0100479#define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \
Achin Gupta4f6ad662013-10-25 09:08:21 +0100480 & ID_PFR1_VIRTEXT_MASK)
481
482/* SCTLR definitions */
David Cunadofee86532017-04-13 22:38:29 +0100483#define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700484 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
485 (U(1) << 11) | (U(1) << 5) | (U(1) << 4))
Achin Gupta4f6ad662013-10-25 09:08:21 +0100486
John Powella5c66362020-03-20 14:21:05 -0500487#define SCTLR_EL1_RES1 ((UL(1) << 29) | (UL(1) << 28) | (UL(1) << 23) | \
488 (UL(1) << 22) | (UL(1) << 20) | (UL(1) << 11))
Alexei Fedorovc082f032020-11-25 14:07:05 +0000489
Jens Wiklanderc93c9df2014-09-04 10:23:27 +0200490#define SCTLR_AARCH32_EL1_RES1 \
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700491 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \
492 (U(1) << 4) | (U(1) << 3))
Jens Wiklanderc93c9df2014-09-04 10:23:27 +0200493
David Cunadofee86532017-04-13 22:38:29 +0100494#define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
495 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
496 (U(1) << 11) | (U(1) << 5) | (U(1) << 4))
497
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000498#define SCTLR_M_BIT (ULL(1) << 0)
499#define SCTLR_A_BIT (ULL(1) << 1)
500#define SCTLR_C_BIT (ULL(1) << 2)
501#define SCTLR_SA_BIT (ULL(1) << 3)
502#define SCTLR_SA0_BIT (ULL(1) << 4)
503#define SCTLR_CP15BEN_BIT (ULL(1) << 5)
Alexei Fedorovc082f032020-11-25 14:07:05 +0000504#define SCTLR_nAA_BIT (ULL(1) << 6)
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000505#define SCTLR_ITD_BIT (ULL(1) << 7)
506#define SCTLR_SED_BIT (ULL(1) << 8)
507#define SCTLR_UMA_BIT (ULL(1) << 9)
Alexei Fedorovc082f032020-11-25 14:07:05 +0000508#define SCTLR_EnRCTX_BIT (ULL(1) << 10)
509#define SCTLR_EOS_BIT (ULL(1) << 11)
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000510#define SCTLR_I_BIT (ULL(1) << 12)
Alexei Fedorovc31ab382019-07-10 10:49:12 +0100511#define SCTLR_EnDB_BIT (ULL(1) << 13)
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000512#define SCTLR_DZE_BIT (ULL(1) << 14)
513#define SCTLR_UCT_BIT (ULL(1) << 15)
514#define SCTLR_NTWI_BIT (ULL(1) << 16)
515#define SCTLR_NTWE_BIT (ULL(1) << 18)
516#define SCTLR_WXN_BIT (ULL(1) << 19)
Alexei Fedorovc082f032020-11-25 14:07:05 +0000517#define SCTLR_TSCXT_BIT (ULL(1) << 20)
Louis Mayencourt78a0aed2019-02-20 12:11:41 +0000518#define SCTLR_IESB_BIT (ULL(1) << 21)
Alexei Fedorovc082f032020-11-25 14:07:05 +0000519#define SCTLR_EIS_BIT (ULL(1) << 22)
520#define SCTLR_SPAN_BIT (ULL(1) << 23)
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000521#define SCTLR_E0E_BIT (ULL(1) << 24)
522#define SCTLR_EE_BIT (ULL(1) << 25)
523#define SCTLR_UCI_BIT (ULL(1) << 26)
Alexei Fedorovc31ab382019-07-10 10:49:12 +0100524#define SCTLR_EnDA_BIT (ULL(1) << 27)
Alexei Fedorovc082f032020-11-25 14:07:05 +0000525#define SCTLR_nTLSMD_BIT (ULL(1) << 28)
526#define SCTLR_LSMAOE_BIT (ULL(1) << 29)
Alexei Fedorovc31ab382019-07-10 10:49:12 +0100527#define SCTLR_EnIB_BIT (ULL(1) << 30)
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000528#define SCTLR_EnIA_BIT (ULL(1) << 31)
Alexei Fedorov90f2e882019-05-24 12:17:09 +0100529#define SCTLR_BT0_BIT (ULL(1) << 35)
530#define SCTLR_BT1_BIT (ULL(1) << 36)
531#define SCTLR_BT_BIT (ULL(1) << 36)
Alexei Fedorovc082f032020-11-25 14:07:05 +0000532#define SCTLR_ITFSB_BIT (ULL(1) << 37)
533#define SCTLR_TCF0_SHIFT U(38)
534#define SCTLR_TCF0_MASK ULL(3)
johpow019baade32021-07-08 14:14:00 -0500535#define SCTLR_ENTP2_BIT (ULL(1) << 60)
Manish Pandey5cfe5152024-01-09 15:55:20 +0000536#define SCTLR_SPINTMASK_BIT (ULL(1) << 62)
Alexei Fedorovc082f032020-11-25 14:07:05 +0000537
538/* Tag Check Faults in EL0 have no effect on the PE */
539#define SCTLR_TCF0_NO_EFFECT U(0)
540/* Tag Check Faults in EL0 cause a synchronous exception */
541#define SCTLR_TCF0_SYNC U(1)
542/* Tag Check Faults in EL0 are asynchronously accumulated */
543#define SCTLR_TCF0_ASYNC U(2)
544/*
545 * Tag Check Faults in EL0 cause a synchronous exception on reads,
546 * and are asynchronously accumulated on writes
547 */
548#define SCTLR_TCF0_SYNCR_ASYNCW U(3)
549
550#define SCTLR_TCF_SHIFT U(40)
551#define SCTLR_TCF_MASK ULL(3)
552
553/* Tag Check Faults in EL1 have no effect on the PE */
554#define SCTLR_TCF_NO_EFFECT U(0)
555/* Tag Check Faults in EL1 cause a synchronous exception */
556#define SCTLR_TCF_SYNC U(1)
557/* Tag Check Faults in EL1 are asynchronously accumulated */
558#define SCTLR_TCF_ASYNC U(2)
559/*
560 * Tag Check Faults in EL1 cause a synchronous exception on reads,
561 * and are asynchronously accumulated on writes
562 */
563#define SCTLR_TCF_SYNCR_ASYNCW U(3)
564
565#define SCTLR_ATA0_BIT (ULL(1) << 42)
566#define SCTLR_ATA_BIT (ULL(1) << 43)
Daniel Boulby44b43332020-11-25 16:36:46 +0000567#define SCTLR_DSSBS_SHIFT U(44)
568#define SCTLR_DSSBS_BIT (ULL(1) << SCTLR_DSSBS_SHIFT)
Alexei Fedorovc082f032020-11-25 14:07:05 +0000569#define SCTLR_TWEDEn_BIT (ULL(1) << 45)
570#define SCTLR_TWEDEL_SHIFT U(46)
571#define SCTLR_TWEDEL_MASK ULL(0xf)
572#define SCTLR_EnASR_BIT (ULL(1) << 54)
573#define SCTLR_EnAS0_BIT (ULL(1) << 55)
574#define SCTLR_EnALS_BIT (ULL(1) << 56)
575#define SCTLR_EPAN_BIT (ULL(1) << 57)
David Cunadofee86532017-04-13 22:38:29 +0100576#define SCTLR_RESET_VAL SCTLR_EL3_RES1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100577
Alexei Fedorovc082f032020-11-25 14:07:05 +0000578/* CPACR_EL1 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700579#define CPACR_EL1_FPEN(x) ((x) << 20)
Jimmy Brissoned202072020-08-04 16:18:52 -0500580#define CPACR_EL1_FP_TRAP_EL0 UL(0x1)
581#define CPACR_EL1_FP_TRAP_ALL UL(0x2)
582#define CPACR_EL1_FP_TRAP_NONE UL(0x3)
Jayanth Dodderi Chidanandcfe053a2022-11-08 10:31:07 +0000583#define CPACR_EL1_SMEN_SHIFT U(24)
584#define CPACR_EL1_SMEN_MASK ULL(0x3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100585
586/* SCR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700587#define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5))
Zelalem Aweke79e3d292021-07-08 16:51:14 -0500588#define SCR_NSE_SHIFT U(62)
589#define SCR_NSE_BIT (ULL(1) << SCR_NSE_SHIFT)
590#define SCR_GPF_BIT (UL(1) << 48)
johpow013e24c162020-04-22 14:05:13 -0500591#define SCR_TWEDEL_SHIFT U(30)
592#define SCR_TWEDEL_MASK ULL(0xf)
Mark Brown293a6612023-03-14 20:48:43 +0000593#define SCR_PIEN_BIT (UL(1) << 45)
Mark Brownc37eee72023-03-14 20:13:03 +0000594#define SCR_TCR2EN_BIT (UL(1) << 43)
Juan Pablo Conde42305f22022-07-12 16:40:29 -0400595#define SCR_TRNDR_BIT (UL(1) << 40)
Mark Brown326f2952023-03-14 21:33:04 +0000596#define SCR_GCSEn_BIT (UL(1) << 39)
johpow019baade32021-07-08 14:14:00 -0500597#define SCR_HXEn_BIT (UL(1) << 38)
598#define SCR_ENTP2_SHIFT U(41)
599#define SCR_ENTP2_BIT (UL(1) << SCR_ENTP2_SHIFT)
John Powellcc799272022-03-29 00:25:59 -0500600#define SCR_AMVOFFEN_SHIFT U(35)
601#define SCR_AMVOFFEN_BIT (UL(1) << SCR_AMVOFFEN_SHIFT)
johpow013e24c162020-04-22 14:05:13 -0500602#define SCR_TWEDEn_BIT (UL(1) << 29)
johpow01fa59c6f2020-10-02 13:41:11 -0500603#define SCR_ECVEN_BIT (UL(1) << 28)
604#define SCR_FGTEN_BIT (UL(1) << 27)
Jimmy Brissoned202072020-08-04 16:18:52 -0500605#define SCR_ATA_BIT (UL(1) << 26)
Zelalem Aweke13dc8f12021-07-09 14:20:03 -0500606#define SCR_EnSCXT_BIT (UL(1) << 25)
Jimmy Brissoned202072020-08-04 16:18:52 -0500607#define SCR_FIEN_BIT (UL(1) << 21)
608#define SCR_EEL2_BIT (UL(1) << 18)
609#define SCR_API_BIT (UL(1) << 17)
610#define SCR_APK_BIT (UL(1) << 16)
611#define SCR_TERR_BIT (UL(1) << 15)
612#define SCR_TWE_BIT (UL(1) << 13)
613#define SCR_TWI_BIT (UL(1) << 12)
614#define SCR_ST_BIT (UL(1) << 11)
615#define SCR_RW_BIT (UL(1) << 10)
616#define SCR_SIF_BIT (UL(1) << 9)
617#define SCR_HCE_BIT (UL(1) << 8)
618#define SCR_SMD_BIT (UL(1) << 7)
619#define SCR_EA_BIT (UL(1) << 3)
620#define SCR_FIQ_BIT (UL(1) << 2)
621#define SCR_IRQ_BIT (UL(1) << 1)
622#define SCR_NS_BIT (UL(1) << 0)
johpow019baade32021-07-08 14:14:00 -0500623#define SCR_VALID_BIT_MASK U(0x24000002F8F)
David Cunadofee86532017-04-13 22:38:29 +0100624#define SCR_RESET_VAL SCR_RES1_BITS
Achin Gupta4f6ad662013-10-25 09:08:21 +0100625
David Cunadofee86532017-04-13 22:38:29 +0100626/* MDCR_EL3 definitions */
Alexei Fedorov307f34b2021-05-14 11:21:56 +0100627#define MDCR_EnPMSN_BIT (ULL(1) << 36)
628#define MDCR_MPMX_BIT (ULL(1) << 35)
629#define MDCR_MCCD_BIT (ULL(1) << 34)
johpow0181865962022-01-28 17:06:20 -0600630#define MDCR_SBRBE_SHIFT U(32)
631#define MDCR_SBRBE_MASK ULL(0x3)
Manish V Badarkhee1cccb42021-06-23 20:02:39 +0100632#define MDCR_NSTB(x) ((x) << 24)
633#define MDCR_NSTB_EL1 ULL(0x3)
Boyan Karatotev919d3c82023-02-13 16:32:47 +0000634#define MDCR_NSTBE_BIT (ULL(1) << 26)
Javier Almansa Sobrinof3a4c542020-11-23 18:38:15 +0000635#define MDCR_MTPME_BIT (ULL(1) << 28)
Alexei Fedorov307f34b2021-05-14 11:21:56 +0100636#define MDCR_TDCC_BIT (ULL(1) << 27)
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100637#define MDCR_SCCD_BIT (ULL(1) << 23)
Alexei Fedorov307f34b2021-05-14 11:21:56 +0100638#define MDCR_EPMAD_BIT (ULL(1) << 21)
639#define MDCR_EDAD_BIT (ULL(1) << 20)
640#define MDCR_TTRF_BIT (ULL(1) << 19)
641#define MDCR_STE_BIT (ULL(1) << 18)
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100642#define MDCR_SPME_BIT (ULL(1) << 17)
643#define MDCR_SDD_BIT (ULL(1) << 16)
dp-arm595d0d52017-02-08 11:51:50 +0000644#define MDCR_SPD32(x) ((x) << 14)
Antonio Nino Diaz3fbd3f52019-02-18 16:55:43 +0000645#define MDCR_SPD32_LEGACY ULL(0x0)
646#define MDCR_SPD32_DISABLE ULL(0x2)
647#define MDCR_SPD32_ENABLE ULL(0x3)
dp-armee3457b2017-05-23 09:32:49 +0100648#define MDCR_NSPB(x) ((x) << 12)
Antonio Nino Diaz3fbd3f52019-02-18 16:55:43 +0000649#define MDCR_NSPB_EL1 ULL(0x3)
Boyan Karatotev6e2fd8b2023-02-13 16:38:37 +0000650#define MDCR_NSPBE_BIT (ULL(1) << 11)
Antonio Nino Diaz3fbd3f52019-02-18 16:55:43 +0000651#define MDCR_TDOSA_BIT (ULL(1) << 10)
652#define MDCR_TDA_BIT (ULL(1) << 9)
653#define MDCR_TPM_BIT (ULL(1) << 6)
Boyan Karatotevb7e74432023-06-15 14:46:20 +0100654#define MDCR_EL3_RESET_VAL MDCR_MTPME_BIT
dp-arm595d0d52017-02-08 11:51:50 +0000655
David Cunadofee86532017-04-13 22:38:29 +0100656/* MDCR_EL2 definitions */
Javier Almansa Sobrinof3a4c542020-11-23 18:38:15 +0000657#define MDCR_EL2_MTPME (U(1) << 28)
Boyan Karatotev05504ba2023-02-15 13:21:50 +0000658#define MDCR_EL2_HLP_BIT (U(1) << 26)
Manish V Badarkhee1cccb42021-06-23 20:02:39 +0100659#define MDCR_EL2_E2TB(x) ((x) << 24)
660#define MDCR_EL2_E2TB_EL1 U(0x3)
Boyan Karatotev05504ba2023-02-15 13:21:50 +0000661#define MDCR_EL2_HCCD_BIT (U(1) << 23)
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100662#define MDCR_EL2_TTRF (U(1) << 19)
Boyan Karatotev05504ba2023-02-15 13:21:50 +0000663#define MDCR_EL2_HPMD_BIT (U(1) << 17)
dp-armee3457b2017-05-23 09:32:49 +0100664#define MDCR_EL2_TPMS (U(1) << 14)
665#define MDCR_EL2_E2PB(x) ((x) << 12)
666#define MDCR_EL2_E2PB_EL1 U(0x3)
David Cunadofee86532017-04-13 22:38:29 +0100667#define MDCR_EL2_TDRA_BIT (U(1) << 11)
668#define MDCR_EL2_TDOSA_BIT (U(1) << 10)
669#define MDCR_EL2_TDA_BIT (U(1) << 9)
670#define MDCR_EL2_TDE_BIT (U(1) << 8)
671#define MDCR_EL2_HPME_BIT (U(1) << 7)
672#define MDCR_EL2_TPM_BIT (U(1) << 6)
673#define MDCR_EL2_TPMCR_BIT (U(1) << 5)
Boyan Karatotev05504ba2023-02-15 13:21:50 +0000674#define MDCR_EL2_HPMN_MASK U(0x1f)
David Cunadofee86532017-04-13 22:38:29 +0100675#define MDCR_EL2_RESET_VAL U(0x0)
676
677/* HSTR_EL2 definitions */
678#define HSTR_EL2_RESET_VAL U(0x0)
679#define HSTR_EL2_T_MASK U(0xff)
680
681/* CNTHP_CTL_EL2 definitions */
682#define CNTHP_CTL_ENABLE_BIT (U(1) << 0)
683#define CNTHP_CTL_RESET_VAL U(0x0)
684
685/* VTTBR_EL2 definitions */
686#define VTTBR_RESET_VAL ULL(0x0)
687#define VTTBR_VMID_MASK ULL(0xff)
688#define VTTBR_VMID_SHIFT U(48)
689#define VTTBR_BADDR_MASK ULL(0xffffffffffff)
690#define VTTBR_BADDR_SHIFT U(0)
dp-arm595d0d52017-02-08 11:51:50 +0000691
Achin Gupta4f6ad662013-10-25 09:08:21 +0100692/* HCR definitions */
Gary Morrison3d7f6542021-01-27 13:08:47 -0600693#define HCR_RESET_VAL ULL(0x0)
Chris Kaya5fde282021-05-26 11:58:23 +0100694#define HCR_AMVOFFEN_SHIFT U(51)
695#define HCR_AMVOFFEN_BIT (ULL(1) << HCR_AMVOFFEN_SHIFT)
Gary Morrison3d7f6542021-01-27 13:08:47 -0600696#define HCR_TEA_BIT (ULL(1) << 47)
Jeenu Viswambharancbad6612018-08-15 14:29:29 +0100697#define HCR_API_BIT (ULL(1) << 41)
698#define HCR_APK_BIT (ULL(1) << 40)
Manish V Badarkhe2801ed42020-04-28 04:53:32 +0100699#define HCR_E2H_BIT (ULL(1) << 34)
Gary Morrison3d7f6542021-01-27 13:08:47 -0600700#define HCR_HCD_BIT (ULL(1) << 29)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000701#define HCR_TGE_BIT (ULL(1) << 27)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700702#define HCR_RW_SHIFT U(31)
703#define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT)
Gary Morrison3d7f6542021-01-27 13:08:47 -0600704#define HCR_TWE_BIT (ULL(1) << 14)
705#define HCR_TWI_BIT (ULL(1) << 13)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100706#define HCR_AMO_BIT (ULL(1) << 5)
707#define HCR_IMO_BIT (ULL(1) << 4)
708#define HCR_FMO_BIT (ULL(1) << 3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100709
Gerald Lejeune851dc7e2016-03-22 11:11:46 +0100710/* ISR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700711#define ISR_A_SHIFT U(8)
712#define ISR_I_SHIFT U(7)
713#define ISR_F_SHIFT U(6)
Gerald Lejeune851dc7e2016-03-22 11:11:46 +0100714
Achin Gupta4f6ad662013-10-25 09:08:21 +0100715/* CNTHCTL_EL2 definitions */
David Cunadofee86532017-04-13 22:38:29 +0100716#define CNTHCTL_RESET_VAL U(0x0)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700717#define EVNTEN_BIT (U(1) << 2)
718#define EL1PCEN_BIT (U(1) << 1)
719#define EL1PCTEN_BIT (U(1) << 0)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100720
721/* CNTKCTL_EL1 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700722#define EL0PTEN_BIT (U(1) << 9)
723#define EL0VTEN_BIT (U(1) << 8)
724#define EL0PCTEN_BIT (U(1) << 0)
725#define EL0VCTEN_BIT (U(1) << 1)
726#define EVNTEN_BIT (U(1) << 2)
727#define EVNTDIR_BIT (U(1) << 3)
728#define EVNTI_SHIFT U(4)
729#define EVNTI_MASK U(0xf)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100730
731/* CPTR_EL3 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700732#define TCPAC_BIT (U(1) << 31)
Chris Kaya5fde282021-05-26 11:58:23 +0100733#define TAM_SHIFT U(30)
734#define TAM_BIT (U(1) << TAM_SHIFT)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700735#define TTA_BIT (U(1) << 20)
johpow019baade32021-07-08 14:14:00 -0500736#define ESM_BIT (U(1) << 12)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700737#define TFP_BIT (U(1) << 10)
David Cunadoce88eee2017-10-20 11:30:57 +0100738#define CPTR_EZ_BIT (U(1) << 8)
johpow019baade32021-07-08 14:14:00 -0500739#define CPTR_EL3_RESET_VAL ((TCPAC_BIT | TAM_BIT | TTA_BIT | TFP_BIT) & \
740 ~(CPTR_EZ_BIT | ESM_BIT))
David Cunadofee86532017-04-13 22:38:29 +0100741
742/* CPTR_EL2 definitions */
743#define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff)))
744#define CPTR_EL2_TCPAC_BIT (U(1) << 31)
Chris Kaya5fde282021-05-26 11:58:23 +0100745#define CPTR_EL2_TAM_SHIFT U(30)
746#define CPTR_EL2_TAM_BIT (U(1) << CPTR_EL2_TAM_SHIFT)
johpow019baade32021-07-08 14:14:00 -0500747#define CPTR_EL2_SMEN_MASK ULL(0x3)
748#define CPTR_EL2_SMEN_SHIFT U(24)
David Cunadofee86532017-04-13 22:38:29 +0100749#define CPTR_EL2_TTA_BIT (U(1) << 20)
johpow019baade32021-07-08 14:14:00 -0500750#define CPTR_EL2_TSM_BIT (U(1) << 12)
David Cunadofee86532017-04-13 22:38:29 +0100751#define CPTR_EL2_TFP_BIT (U(1) << 10)
David Cunadoce88eee2017-10-20 11:30:57 +0100752#define CPTR_EL2_TZ_BIT (U(1) << 8)
David Cunadofee86532017-04-13 22:38:29 +0100753#define CPTR_EL2_RESET_VAL CPTR_EL2_RES1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100754
Manish Pandey5693afe2021-10-06 17:28:09 +0100755/* VTCR_EL2 definitions */
johpow019baade32021-07-08 14:14:00 -0500756#define VTCR_RESET_VAL U(0x0)
757#define VTCR_EL2_MSA (U(1) << 31)
Manish Pandey5693afe2021-10-06 17:28:09 +0100758
Achin Gupta4f6ad662013-10-25 09:08:21 +0100759/* CPSR/SPSR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700760#define DAIF_FIQ_BIT (U(1) << 0)
761#define DAIF_IRQ_BIT (U(1) << 1)
762#define DAIF_ABT_BIT (U(1) << 2)
763#define DAIF_DBG_BIT (U(1) << 3)
Manish Pandey5cfe5152024-01-09 15:55:20 +0000764#define SPSR_V_BIT (U(1) << 28)
765#define SPSR_C_BIT (U(1) << 29)
766#define SPSR_Z_BIT (U(1) << 30)
767#define SPSR_N_BIT (U(1) << 31)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700768#define SPSR_DAIF_SHIFT U(6)
769#define SPSR_DAIF_MASK U(0xf)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100770
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700771#define SPSR_AIF_SHIFT U(6)
772#define SPSR_AIF_MASK U(0x7)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100773
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700774#define SPSR_E_SHIFT U(9)
775#define SPSR_E_MASK U(0x1)
776#define SPSR_E_LITTLE U(0x0)
777#define SPSR_E_BIG U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100778
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700779#define SPSR_T_SHIFT U(5)
780#define SPSR_T_MASK U(0x1)
781#define SPSR_T_ARM U(0x0)
782#define SPSR_T_THUMB U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100783
Dimitris Papastamosc52ebdc2017-12-18 13:46:21 +0000784#define SPSR_M_SHIFT U(4)
785#define SPSR_M_MASK U(0x1)
786#define SPSR_M_AARCH64 U(0x0)
787#define SPSR_M_AARCH32 U(0x1)
Manish Pandey5cfe5152024-01-09 15:55:20 +0000788#define SPSR_M_EL1H U(0x5)
Zelalem Aweke13dc8f12021-07-09 14:20:03 -0500789#define SPSR_M_EL2H U(0x9)
Dimitris Papastamosc52ebdc2017-12-18 13:46:21 +0000790
Alexei Fedorov813c9f92020-03-03 13:31:58 +0000791#define SPSR_EL_SHIFT U(2)
792#define SPSR_EL_WIDTH U(2)
793
Manish Pandey5cfe5152024-01-09 15:55:20 +0000794#define SPSR_BTYPE_SHIFT_AARCH64 U(10)
795#define SPSR_BTYPE_MASK_AARCH64 U(0x3)
796#define SPSR_SSBS_SHIFT_AARCH64 U(12)
Daniel Boulby44b43332020-11-25 16:36:46 +0000797#define SPSR_SSBS_BIT_AARCH64 (ULL(1) << SPSR_SSBS_SHIFT_AARCH64)
798#define SPSR_SSBS_SHIFT_AARCH32 U(23)
799#define SPSR_SSBS_BIT_AARCH32 (ULL(1) << SPSR_SSBS_SHIFT_AARCH32)
Manish Pandey5cfe5152024-01-09 15:55:20 +0000800#define SPSR_ALLINT_BIT_AARCH64 BIT_64(13)
801#define SPSR_IL_BIT BIT_64(20)
802#define SPSR_SS_BIT BIT_64(21)
Daniel Boulby44b43332020-11-25 16:36:46 +0000803#define SPSR_PAN_BIT BIT_64(22)
Manish Pandey5cfe5152024-01-09 15:55:20 +0000804#define SPSR_UAO_BIT_AARCH64 BIT_64(23)
Daniel Boulby44b43332020-11-25 16:36:46 +0000805#define SPSR_DIT_BIT BIT(24)
Daniel Boulby44b43332020-11-25 16:36:46 +0000806#define SPSR_TCO_BIT_AARCH64 BIT_64(25)
Manish Pandey5cfe5152024-01-09 15:55:20 +0000807#define SPSR_PM_BIT_AARCH64 BIT_64(32)
808#define SPSR_PPEND_BIT BIT(33)
809#define SPSR_EXLOCK_BIT_AARCH64 BIT_64(34)
810#define SPSR_NZCV (SPSR_V_BIT | SPSR_C_BIT | SPSR_Z_BIT | SPSR_N_BIT)
John Tsichritzis55534172019-07-23 11:12:41 +0100811
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100812#define DISABLE_ALL_EXCEPTIONS \
813 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000814#define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT)
815
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000816/*
817 * RMR_EL3 definitions
818 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700819#define RMR_EL3_RR_BIT (U(1) << 1)
820#define RMR_EL3_AA64_BIT (U(1) << 0)
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000821
822/*
823 * HI-VECTOR address for AArch32 state
824 */
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000825#define HI_VECTOR_BASE U(0xFFFF0000)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100826
827/*
Elyes Haouas2be03c02023-02-13 09:14:48 +0100828 * TCR definitions
Achin Gupta4f6ad662013-10-25 09:08:21 +0100829 */
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000830#define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23))
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100831#define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23))
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700832#define TCR_EL1_IPS_SHIFT U(32)
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100833#define TCR_EL2_PS_SHIFT U(16)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700834#define TCR_EL3_PS_SHIFT U(16)
Lin Ma741a3822014-06-27 16:56:30 -0700835
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100836#define TCR_TxSZ_MIN ULL(16)
837#define TCR_TxSZ_MAX ULL(39)
Sathees Balya74155972019-01-25 11:36:01 +0000838#define TCR_TxSZ_MAX_TTST ULL(48)
Antonio Nino Diazd48ae612016-08-02 09:21:41 +0100839
Antonio Nino Diaz37f97a52019-03-27 11:10:31 +0000840#define TCR_T0SZ_SHIFT U(0)
841#define TCR_T1SZ_SHIFT U(16)
842
Lin Ma741a3822014-06-27 16:56:30 -0700843/* (internal) physical address size bits in EL3/EL1 */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100844#define TCR_PS_BITS_4GB ULL(0x0)
845#define TCR_PS_BITS_64GB ULL(0x1)
846#define TCR_PS_BITS_1TB ULL(0x2)
847#define TCR_PS_BITS_4TB ULL(0x3)
848#define TCR_PS_BITS_16TB ULL(0x4)
849#define TCR_PS_BITS_256TB ULL(0x5)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100850
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700851#define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000)
852#define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000)
853#define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000)
854#define ADDR_MASK_40_TO_41 ULL(0x0000030000000000)
855#define ADDR_MASK_36_TO_39 ULL(0x000000F000000000)
856#define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100857
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100858#define TCR_RGN_INNER_NC (ULL(0x0) << 8)
859#define TCR_RGN_INNER_WBA (ULL(0x1) << 8)
860#define TCR_RGN_INNER_WT (ULL(0x2) << 8)
861#define TCR_RGN_INNER_WBNA (ULL(0x3) << 8)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100862
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100863#define TCR_RGN_OUTER_NC (ULL(0x0) << 10)
864#define TCR_RGN_OUTER_WBA (ULL(0x1) << 10)
865#define TCR_RGN_OUTER_WT (ULL(0x2) << 10)
866#define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100867
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100868#define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12)
869#define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12)
870#define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100871
Antonio Nino Diaz37f97a52019-03-27 11:10:31 +0000872#define TCR_RGN1_INNER_NC (ULL(0x0) << 24)
873#define TCR_RGN1_INNER_WBA (ULL(0x1) << 24)
874#define TCR_RGN1_INNER_WT (ULL(0x2) << 24)
875#define TCR_RGN1_INNER_WBNA (ULL(0x3) << 24)
876
877#define TCR_RGN1_OUTER_NC (ULL(0x0) << 26)
878#define TCR_RGN1_OUTER_WBA (ULL(0x1) << 26)
879#define TCR_RGN1_OUTER_WT (ULL(0x2) << 26)
880#define TCR_RGN1_OUTER_WBNA (ULL(0x3) << 26)
881
882#define TCR_SH1_NON_SHAREABLE (ULL(0x0) << 28)
883#define TCR_SH1_OUTER_SHAREABLE (ULL(0x2) << 28)
884#define TCR_SH1_INNER_SHAREABLE (ULL(0x3) << 28)
885
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100886#define TCR_TG0_SHIFT U(14)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100887#define TCR_TG0_MASK ULL(3)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100888#define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT)
889#define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT)
890#define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT)
891
Antonio Nino Diaz37f97a52019-03-27 11:10:31 +0000892#define TCR_TG1_SHIFT U(30)
893#define TCR_TG1_MASK ULL(3)
894#define TCR_TG1_16K (ULL(1) << TCR_TG1_SHIFT)
895#define TCR_TG1_4K (ULL(2) << TCR_TG1_SHIFT)
896#define TCR_TG1_64K (ULL(3) << TCR_TG1_SHIFT)
897
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100898#define TCR_EPD0_BIT (ULL(1) << 7)
899#define TCR_EPD1_BIT (ULL(1) << 23)
Antonio Nino Diazc8274a82017-09-15 10:30:34 +0100900
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700901#define MODE_SP_SHIFT U(0x0)
902#define MODE_SP_MASK U(0x1)
903#define MODE_SP_EL0 U(0x0)
904#define MODE_SP_ELX U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100905
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700906#define MODE_RW_SHIFT U(0x4)
907#define MODE_RW_MASK U(0x1)
908#define MODE_RW_64 U(0x0)
909#define MODE_RW_32 U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100910
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700911#define MODE_EL_SHIFT U(0x2)
912#define MODE_EL_MASK U(0x3)
Alexei Fedorov813c9f92020-03-03 13:31:58 +0000913#define MODE_EL_WIDTH U(0x2)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700914#define MODE_EL3 U(0x3)
915#define MODE_EL2 U(0x2)
916#define MODE_EL1 U(0x1)
917#define MODE_EL0 U(0x0)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100918
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700919#define MODE32_SHIFT U(0)
920#define MODE32_MASK U(0xf)
921#define MODE32_usr U(0x0)
922#define MODE32_fiq U(0x1)
923#define MODE32_irq U(0x2)
924#define MODE32_svc U(0x3)
925#define MODE32_mon U(0x6)
926#define MODE32_abt U(0x7)
927#define MODE32_hyp U(0xa)
928#define MODE32_und U(0xb)
929#define MODE32_sys U(0xf)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100930
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100931#define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK)
932#define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK)
933#define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK)
934#define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100935
John Tsichritzis55534172019-07-23 11:12:41 +0100936#define SPSR_64(el, sp, daif) \
937 (((MODE_RW_64 << MODE_RW_SHIFT) | \
938 (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \
939 (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \
940 (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) & \
941 (~(SPSR_SSBS_BIT_AARCH64)))
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100942
943#define SPSR_MODE32(mode, isa, endian, aif) \
John Tsichritzis55534172019-07-23 11:12:41 +0100944 (((MODE_RW_32 << MODE_RW_SHIFT) | \
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700945 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \
946 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \
947 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \
John Tsichritzis55534172019-07-23 11:12:41 +0100948 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) & \
949 (~(SPSR_SSBS_BIT_AARCH32)))
Achin Gupta4f6ad662013-10-25 09:08:21 +0100950
Dan Handley0cdebbd2015-03-30 17:15:16 +0100951/*
Isla Mitchellc4a1a072017-08-07 11:20:13 +0100952 * TTBR Definitions
953 */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100954#define TTBR_CNP_BIT ULL(0x1)
Isla Mitchellc4a1a072017-08-07 11:20:13 +0100955
956/*
Dan Handley0cdebbd2015-03-30 17:15:16 +0100957 * CTR_EL0 definitions
958 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700959#define CTR_CWG_SHIFT U(24)
960#define CTR_CWG_MASK U(0xf)
961#define CTR_ERG_SHIFT U(20)
962#define CTR_ERG_MASK U(0xf)
963#define CTR_DMINLINE_SHIFT U(16)
964#define CTR_DMINLINE_MASK U(0xf)
965#define CTR_L1IP_SHIFT U(14)
966#define CTR_L1IP_MASK U(0x3)
967#define CTR_IMINLINE_SHIFT U(0)
968#define CTR_IMINLINE_MASK U(0xf)
Dan Handley0cdebbd2015-03-30 17:15:16 +0100969
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700970#define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100971
Achin Gupta405406d2014-05-09 12:00:17 +0100972/* Physical timer control register bit fields shifts and masks */
johpow01fa59c6f2020-10-02 13:41:11 -0500973#define CNTP_CTL_ENABLE_SHIFT U(0)
974#define CNTP_CTL_IMASK_SHIFT U(1)
975#define CNTP_CTL_ISTATUS_SHIFT U(2)
Achin Gupta405406d2014-05-09 12:00:17 +0100976
johpow01fa59c6f2020-10-02 13:41:11 -0500977#define CNTP_CTL_ENABLE_MASK U(1)
978#define CNTP_CTL_IMASK_MASK U(1)
979#define CNTP_CTL_ISTATUS_MASK U(1)
Achin Gupta405406d2014-05-09 12:00:17 +0100980
Varun Wadekar787a1292018-06-18 16:15:51 -0700981/* Physical timer control macros */
982#define CNTP_CTL_ENABLE_BIT (U(1) << CNTP_CTL_ENABLE_SHIFT)
983#define CNTP_CTL_IMASK_BIT (U(1) << CNTP_CTL_IMASK_SHIFT)
984
Achin Gupta4f6ad662013-10-25 09:08:21 +0100985/* Exception Syndrome register bits and bobs */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700986#define ESR_EC_SHIFT U(26)
987#define ESR_EC_MASK U(0x3f)
988#define ESR_EC_LENGTH U(6)
Justin Chadwell83e04882019-08-20 11:01:52 +0100989#define ESR_ISS_SHIFT U(0)
990#define ESR_ISS_LENGTH U(25)
Manish Pandey5cfe5152024-01-09 15:55:20 +0000991#define ESR_IL_BIT (U(1) << 25)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700992#define EC_UNKNOWN U(0x0)
993#define EC_WFE_WFI U(0x1)
994#define EC_AARCH32_CP15_MRC_MCR U(0x3)
995#define EC_AARCH32_CP15_MRRC_MCRR U(0x4)
996#define EC_AARCH32_CP14_MRC_MCR U(0x5)
997#define EC_AARCH32_CP14_LDC_STC U(0x6)
998#define EC_FP_SIMD U(0x7)
999#define EC_AARCH32_CP10_MRC U(0x8)
1000#define EC_AARCH32_CP14_MRRC_MCRR U(0xc)
1001#define EC_ILLEGAL U(0xe)
1002#define EC_AARCH32_SVC U(0x11)
1003#define EC_AARCH32_HVC U(0x12)
1004#define EC_AARCH32_SMC U(0x13)
1005#define EC_AARCH64_SVC U(0x15)
1006#define EC_AARCH64_HVC U(0x16)
1007#define EC_AARCH64_SMC U(0x17)
1008#define EC_AARCH64_SYS U(0x18)
Manish Pandeya4752e22023-10-11 11:52:24 +01001009#define EC_IMP_DEF_EL3 U(0x1f)
Varun Wadekarc6a11f62017-05-25 18:04:48 -07001010#define EC_IABORT_LOWER_EL U(0x20)
1011#define EC_IABORT_CUR_EL U(0x21)
1012#define EC_PC_ALIGN U(0x22)
1013#define EC_DABORT_LOWER_EL U(0x24)
1014#define EC_DABORT_CUR_EL U(0x25)
1015#define EC_SP_ALIGN U(0x26)
1016#define EC_AARCH32_FP U(0x28)
1017#define EC_AARCH64_FP U(0x2c)
1018#define EC_SERROR U(0x2f)
Justin Chadwell83e04882019-08-20 11:01:52 +01001019#define EC_BRK U(0x3c)
Achin Gupta4f6ad662013-10-25 09:08:21 +01001020
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +00001021/*
1022 * External Abort bit in Instruction and Data Aborts synchronous exception
1023 * syndromes.
1024 */
1025#define ESR_ISS_EABORT_EA_BIT U(9)
1026
Varun Wadekarc6a11f62017-05-25 18:04:48 -07001027#define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK)
Achin Gupta4f6ad662013-10-25 09:08:21 +01001028
Vignesh Radhakrishnanb4a72942017-03-03 10:58:05 -08001029/* Reset bit inside the Reset management register for EL3 (RMR_EL3) */
Varun Wadekarc6a11f62017-05-25 18:04:48 -07001030#define RMR_RESET_REQUEST_SHIFT U(0x1)
1031#define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT)
Vignesh Radhakrishnanb4a72942017-03-03 10:58:05 -08001032
Dan Handleyed6ff952014-05-14 17:44:19 +01001033/*******************************************************************************
Antonio Nino Diazac998032017-02-27 17:23:54 +00001034 * Definitions of register offsets, fields and macros for CPU system
1035 * instructions.
1036 ******************************************************************************/
1037
Varun Wadekarc6a11f62017-05-25 18:04:48 -07001038#define TLBI_ADDR_SHIFT U(12)
Antonio Nino Diazac998032017-02-27 17:23:54 +00001039#define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF)
1040#define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK)
1041
1042/*******************************************************************************
Dan Handleyed6ff952014-05-14 17:44:19 +01001043 * Definitions of register offsets and fields in the CNTCTLBase Frame of the
1044 * system level implementation of the Generic Timer.
1045 ******************************************************************************/
Soby Mathew2d9f7952018-06-11 16:21:30 +01001046#define CNTCTLBASE_CNTFRQ U(0x0)
Varun Wadekarc6a11f62017-05-25 18:04:48 -07001047#define CNTNSAR U(0x4)
1048#define CNTNSAR_NS_SHIFT(x) (x)
Dan Handleyed6ff952014-05-14 17:44:19 +01001049
Varun Wadekarc6a11f62017-05-25 18:04:48 -07001050#define CNTACR_BASE(x) (U(0x40) + ((x) << 2))
1051#define CNTACR_RPCT_SHIFT U(0x0)
1052#define CNTACR_RVCT_SHIFT U(0x1)
1053#define CNTACR_RFRQ_SHIFT U(0x2)
1054#define CNTACR_RVOFF_SHIFT U(0x3)
1055#define CNTACR_RWVT_SHIFT U(0x4)
1056#define CNTACR_RWPT_SHIFT U(0x5)
Dan Handleyed6ff952014-05-14 17:44:19 +01001057
Soby Mathew2d9f7952018-06-11 16:21:30 +01001058/*******************************************************************************
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +00001059 * Definitions of register offsets and fields in the CNTBaseN Frame of the
Soby Mathew2d9f7952018-06-11 16:21:30 +01001060 * system level implementation of the Generic Timer.
1061 ******************************************************************************/
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +00001062/* Physical Count register. */
1063#define CNTPCT_LO U(0x0)
1064/* Counter Frequency register. */
1065#define CNTBASEN_CNTFRQ U(0x10)
1066/* Physical Timer CompareValue register. */
1067#define CNTP_CVAL_LO U(0x20)
1068/* Physical Timer Control register. */
1069#define CNTP_CTL U(0x2c)
Soby Mathew2d9f7952018-06-11 16:21:30 +01001070
David Cunado5f55e282016-10-31 17:37:34 +00001071/* PMCR_EL0 definitions */
David Cunado4168f2f2017-10-02 17:41:39 +01001072#define PMCR_EL0_RESET_VAL U(0x0)
Varun Wadekarc6a11f62017-05-25 18:04:48 -07001073#define PMCR_EL0_N_SHIFT U(11)
1074#define PMCR_EL0_N_MASK U(0x1f)
David Cunado5f55e282016-10-31 17:37:34 +00001075#define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT)
Alexei Fedorov503bbf32019-08-13 15:17:53 +01001076#define PMCR_EL0_LP_BIT (U(1) << 7)
David Cunado4168f2f2017-10-02 17:41:39 +01001077#define PMCR_EL0_LC_BIT (U(1) << 6)
1078#define PMCR_EL0_DP_BIT (U(1) << 5)
1079#define PMCR_EL0_X_BIT (U(1) << 4)
1080#define PMCR_EL0_D_BIT (U(1) << 3)
Alexei Fedorov503bbf32019-08-13 15:17:53 +01001081#define PMCR_EL0_C_BIT (U(1) << 2)
1082#define PMCR_EL0_P_BIT (U(1) << 1)
1083#define PMCR_EL0_E_BIT (U(1) << 0)
David Cunado5f55e282016-10-31 17:37:34 +00001084
Isla Mitchell02c63072017-07-21 14:44:36 +01001085/*******************************************************************************
David Cunadoce88eee2017-10-20 11:30:57 +01001086 * Definitions for system register interface to SVE
1087 ******************************************************************************/
1088#define ZCR_EL3 S3_6_C1_C2_0
1089#define ZCR_EL2 S3_4_C1_C2_0
1090
1091/* ZCR_EL3 definitions */
1092#define ZCR_EL3_LEN_MASK U(0xf)
1093
1094/* ZCR_EL2 definitions */
1095#define ZCR_EL2_LEN_MASK U(0xf)
1096
1097/*******************************************************************************
johpow019baade32021-07-08 14:14:00 -05001098 * Definitions for system register interface to SME as needed in EL3
1099 ******************************************************************************/
1100#define ID_AA64SMFR0_EL1 S3_0_C0_C4_5
1101#define SMCR_EL3 S3_6_C1_C2_6
1102
1103/* ID_AA64SMFR0_EL1 definitions */
Jayanth Dodderi Chidanand605419a2023-03-06 23:56:14 +00001104#define ID_AA64SMFR0_EL1_SME_FA64_SHIFT U(63)
1105#define ID_AA64SMFR0_EL1_SME_FA64_MASK U(0x1)
1106#define ID_AA64SMFR0_EL1_SME_FA64_SUPPORTED U(0x1)
Jayanth Dodderi Chidanandcfe053a2022-11-08 10:31:07 +00001107#define ID_AA64SMFR0_EL1_SME_VER_SHIFT U(55)
1108#define ID_AA64SMFR0_EL1_SME_VER_MASK ULL(0xf)
1109#define ID_AA64SMFR0_EL1_SME_INST_SUPPORTED ULL(0x0)
1110#define ID_AA64SMFR0_EL1_SME2_INST_SUPPORTED ULL(0x1)
johpow019baade32021-07-08 14:14:00 -05001111
1112/* SMCR_ELx definitions */
1113#define SMCR_ELX_LEN_SHIFT U(0)
Jayanth Dodderi Chidanandcfe053a2022-11-08 10:31:07 +00001114#define SMCR_ELX_LEN_MAX U(0x1ff)
johpow019baade32021-07-08 14:14:00 -05001115#define SMCR_ELX_FA64_BIT (U(1) << 31)
Jayanth Dodderi Chidanandcfe053a2022-11-08 10:31:07 +00001116#define SMCR_ELX_EZT0_BIT (U(1) << 30)
johpow019baade32021-07-08 14:14:00 -05001117
1118/*******************************************************************************
Isla Mitchell02c63072017-07-21 14:44:36 +01001119 * Definitions of MAIR encodings for device and normal memory
1120 ******************************************************************************/
1121/*
1122 * MAIR encodings for device memory attributes.
1123 */
1124#define MAIR_DEV_nGnRnE ULL(0x0)
1125#define MAIR_DEV_nGnRE ULL(0x4)
1126#define MAIR_DEV_nGRE ULL(0x8)
1127#define MAIR_DEV_GRE ULL(0xc)
1128
1129/*
1130 * MAIR encodings for normal memory attributes.
1131 *
1132 * Cache Policy
1133 * WT: Write Through
1134 * WB: Write Back
1135 * NC: Non-Cacheable
1136 *
1137 * Transient Hint
1138 * NTR: Non-Transient
1139 * TR: Transient
1140 *
1141 * Allocation Policy
1142 * RA: Read Allocate
1143 * WA: Write Allocate
1144 * RWA: Read and Write Allocate
1145 * NA: No Allocation
1146 */
1147#define MAIR_NORM_WT_TR_WA ULL(0x1)
1148#define MAIR_NORM_WT_TR_RA ULL(0x2)
1149#define MAIR_NORM_WT_TR_RWA ULL(0x3)
1150#define MAIR_NORM_NC ULL(0x4)
1151#define MAIR_NORM_WB_TR_WA ULL(0x5)
1152#define MAIR_NORM_WB_TR_RA ULL(0x6)
1153#define MAIR_NORM_WB_TR_RWA ULL(0x7)
1154#define MAIR_NORM_WT_NTR_NA ULL(0x8)
1155#define MAIR_NORM_WT_NTR_WA ULL(0x9)
1156#define MAIR_NORM_WT_NTR_RA ULL(0xa)
1157#define MAIR_NORM_WT_NTR_RWA ULL(0xb)
1158#define MAIR_NORM_WB_NTR_NA ULL(0xc)
1159#define MAIR_NORM_WB_NTR_WA ULL(0xd)
1160#define MAIR_NORM_WB_NTR_RA ULL(0xe)
1161#define MAIR_NORM_WB_NTR_RWA ULL(0xf)
1162
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +01001163#define MAIR_NORM_OUTER_SHIFT U(4)
Isla Mitchell02c63072017-07-21 14:44:36 +01001164
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +01001165#define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \
1166 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT))
Isla Mitchell02c63072017-07-21 14:44:36 +01001167
Jeenu Viswambharan1dc771b2017-10-19 09:15:15 +01001168/* PAR_EL1 fields */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +01001169#define PAR_F_SHIFT U(0)
1170#define PAR_F_MASK ULL(0x1)
1171#define PAR_ADDR_SHIFT U(12)
1172#define PAR_ADDR_MASK (BIT(40) - ULL(1)) /* 40-bits-wide page address */
Jeenu Viswambharan1dc771b2017-10-19 09:15:15 +01001173
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +01001174/*******************************************************************************
1175 * Definitions for system register interface to SPE
1176 ******************************************************************************/
1177#define PMBLIMITR_EL1 S3_0_C9_C10_0
1178
Dimitris Papastamose08005a2017-10-12 13:02:29 +01001179/*******************************************************************************
Rohit Mathew3dc3cad2022-11-11 18:45:11 +00001180 * Definitions for system register interface, shifts and masks for MPAM
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +01001181 ******************************************************************************/
1182#define MPAMIDR_EL1 S3_0_C10_C4_4
1183#define MPAM2_EL2 S3_4_C10_C5_0
1184#define MPAMHCR_EL2 S3_4_C10_C4_0
1185#define MPAM3_EL3 S3_6_C10_C5_0
1186
Andre Przywara84b86532022-11-17 16:42:09 +00001187#define MPAMIDR_EL1_VPMR_MAX_SHIFT ULL(18)
1188#define MPAMIDR_EL1_VPMR_MAX_MASK ULL(0x7)
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +01001189/*******************************************************************************
johpow01fa59c6f2020-10-02 13:41:11 -05001190 * Definitions for system register interface to AMU for FEAT_AMUv1
Dimitris Papastamose08005a2017-10-12 13:02:29 +01001191 ******************************************************************************/
1192#define AMCR_EL0 S3_3_C13_C2_0
1193#define AMCFGR_EL0 S3_3_C13_C2_1
1194#define AMCGCR_EL0 S3_3_C13_C2_2
1195#define AMUSERENR_EL0 S3_3_C13_C2_3
1196#define AMCNTENCLR0_EL0 S3_3_C13_C2_4
1197#define AMCNTENSET0_EL0 S3_3_C13_C2_5
1198#define AMCNTENCLR1_EL0 S3_3_C13_C3_0
1199#define AMCNTENSET1_EL0 S3_3_C13_C3_1
1200
1201/* Activity Monitor Group 0 Event Counter Registers */
1202#define AMEVCNTR00_EL0 S3_3_C13_C4_0
1203#define AMEVCNTR01_EL0 S3_3_C13_C4_1
1204#define AMEVCNTR02_EL0 S3_3_C13_C4_2
1205#define AMEVCNTR03_EL0 S3_3_C13_C4_3
1206
1207/* Activity Monitor Group 0 Event Type Registers */
1208#define AMEVTYPER00_EL0 S3_3_C13_C6_0
1209#define AMEVTYPER01_EL0 S3_3_C13_C6_1
1210#define AMEVTYPER02_EL0 S3_3_C13_C6_2
1211#define AMEVTYPER03_EL0 S3_3_C13_C6_3
1212
Dimitris Papastamos525c37a2017-11-13 09:49:45 +00001213/* Activity Monitor Group 1 Event Counter Registers */
1214#define AMEVCNTR10_EL0 S3_3_C13_C12_0
1215#define AMEVCNTR11_EL0 S3_3_C13_C12_1
1216#define AMEVCNTR12_EL0 S3_3_C13_C12_2
1217#define AMEVCNTR13_EL0 S3_3_C13_C12_3
1218#define AMEVCNTR14_EL0 S3_3_C13_C12_4
1219#define AMEVCNTR15_EL0 S3_3_C13_C12_5
1220#define AMEVCNTR16_EL0 S3_3_C13_C12_6
1221#define AMEVCNTR17_EL0 S3_3_C13_C12_7
1222#define AMEVCNTR18_EL0 S3_3_C13_C13_0
1223#define AMEVCNTR19_EL0 S3_3_C13_C13_1
1224#define AMEVCNTR1A_EL0 S3_3_C13_C13_2
1225#define AMEVCNTR1B_EL0 S3_3_C13_C13_3
1226#define AMEVCNTR1C_EL0 S3_3_C13_C13_4
1227#define AMEVCNTR1D_EL0 S3_3_C13_C13_5
1228#define AMEVCNTR1E_EL0 S3_3_C13_C13_6
1229#define AMEVCNTR1F_EL0 S3_3_C13_C13_7
1230
1231/* Activity Monitor Group 1 Event Type Registers */
1232#define AMEVTYPER10_EL0 S3_3_C13_C14_0
1233#define AMEVTYPER11_EL0 S3_3_C13_C14_1
1234#define AMEVTYPER12_EL0 S3_3_C13_C14_2
1235#define AMEVTYPER13_EL0 S3_3_C13_C14_3
1236#define AMEVTYPER14_EL0 S3_3_C13_C14_4
1237#define AMEVTYPER15_EL0 S3_3_C13_C14_5
1238#define AMEVTYPER16_EL0 S3_3_C13_C14_6
1239#define AMEVTYPER17_EL0 S3_3_C13_C14_7
1240#define AMEVTYPER18_EL0 S3_3_C13_C15_0
1241#define AMEVTYPER19_EL0 S3_3_C13_C15_1
1242#define AMEVTYPER1A_EL0 S3_3_C13_C15_2
1243#define AMEVTYPER1B_EL0 S3_3_C13_C15_3
1244#define AMEVTYPER1C_EL0 S3_3_C13_C15_4
1245#define AMEVTYPER1D_EL0 S3_3_C13_C15_5
1246#define AMEVTYPER1E_EL0 S3_3_C13_C15_6
1247#define AMEVTYPER1F_EL0 S3_3_C13_C15_7
1248
Chris Kaya5fde282021-05-26 11:58:23 +01001249/* AMCNTENSET0_EL0 definitions */
1250#define AMCNTENSET0_EL0_Pn_SHIFT U(0)
1251#define AMCNTENSET0_EL0_Pn_MASK ULL(0xffff)
1252
1253/* AMCNTENSET1_EL0 definitions */
1254#define AMCNTENSET1_EL0_Pn_SHIFT U(0)
1255#define AMCNTENSET1_EL0_Pn_MASK ULL(0xffff)
1256
1257/* AMCNTENCLR0_EL0 definitions */
1258#define AMCNTENCLR0_EL0_Pn_SHIFT U(0)
1259#define AMCNTENCLR0_EL0_Pn_MASK ULL(0xffff)
1260
1261/* AMCNTENCLR1_EL0 definitions */
1262#define AMCNTENCLR1_EL0_Pn_SHIFT U(0)
1263#define AMCNTENCLR1_EL0_Pn_MASK ULL(0xffff)
1264
Alexei Fedorov7e6306b2020-07-14 08:17:56 +01001265/* AMCFGR_EL0 definitions */
1266#define AMCFGR_EL0_NCG_SHIFT U(28)
1267#define AMCFGR_EL0_NCG_MASK U(0xf)
1268#define AMCFGR_EL0_N_SHIFT U(0)
1269#define AMCFGR_EL0_N_MASK U(0xff)
1270
Dimitris Papastamos525c37a2017-11-13 09:49:45 +00001271/* AMCGCR_EL0 definitions */
Chris Kaya40141d2021-05-25 12:33:18 +01001272#define AMCGCR_EL0_CG0NC_SHIFT U(0)
1273#define AMCGCR_EL0_CG0NC_MASK U(0xff)
Dimitris Papastamos525c37a2017-11-13 09:49:45 +00001274#define AMCGCR_EL0_CG1NC_SHIFT U(8)
Dimitris Papastamos525c37a2017-11-13 09:49:45 +00001275#define AMCGCR_EL0_CG1NC_MASK U(0xff)
1276
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +01001277/* MPAM register definitions */
1278#define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63)
Arvind Ram Prakashab28d4b2023-10-11 12:10:56 -05001279#define MPAM3_EL3_TRAPLOWER_BIT (ULL(1) << 62)
Louis Mayencourtbdfa1032019-02-11 11:25:50 +00001280#define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31)
Arvind Ram Prakashab28d4b2023-10-11 12:10:56 -05001281#define MPAM3_EL3_RESET_VAL MPAM3_EL3_TRAPLOWER_BIT
Louis Mayencourtbdfa1032019-02-11 11:25:50 +00001282
1283#define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49)
1284#define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48)
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +01001285
1286#define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17)
1287
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +01001288/*******************************************************************************
johpow01fa59c6f2020-10-02 13:41:11 -05001289 * Definitions for system register interface to AMU for FEAT_AMUv1p1
1290 ******************************************************************************/
1291
1292/* Definition for register defining which virtual offsets are implemented. */
1293#define AMCG1IDR_EL0 S3_3_C13_C2_6
1294#define AMCG1IDR_CTR_MASK ULL(0xffff)
1295#define AMCG1IDR_CTR_SHIFT U(0)
1296#define AMCG1IDR_VOFF_MASK ULL(0xffff)
1297#define AMCG1IDR_VOFF_SHIFT U(16)
1298
1299/* New bit added to AMCR_EL0 */
Chris Kaya5fde282021-05-26 11:58:23 +01001300#define AMCR_CG1RZ_SHIFT U(17)
1301#define AMCR_CG1RZ_BIT (ULL(0x1) << AMCR_CG1RZ_SHIFT)
johpow01fa59c6f2020-10-02 13:41:11 -05001302
1303/*
1304 * Definitions for virtual offset registers for architected activity monitor
1305 * event counters.
1306 * AMEVCNTVOFF01_EL2 intentionally left undefined, as it does not exist.
1307 */
1308#define AMEVCNTVOFF00_EL2 S3_4_C13_C8_0
1309#define AMEVCNTVOFF02_EL2 S3_4_C13_C8_2
1310#define AMEVCNTVOFF03_EL2 S3_4_C13_C8_3
1311
1312/*
1313 * Definitions for virtual offset registers for auxiliary activity monitor event
1314 * counters.
1315 */
1316#define AMEVCNTVOFF10_EL2 S3_4_C13_C10_0
1317#define AMEVCNTVOFF11_EL2 S3_4_C13_C10_1
1318#define AMEVCNTVOFF12_EL2 S3_4_C13_C10_2
1319#define AMEVCNTVOFF13_EL2 S3_4_C13_C10_3
1320#define AMEVCNTVOFF14_EL2 S3_4_C13_C10_4
1321#define AMEVCNTVOFF15_EL2 S3_4_C13_C10_5
1322#define AMEVCNTVOFF16_EL2 S3_4_C13_C10_6
1323#define AMEVCNTVOFF17_EL2 S3_4_C13_C10_7
1324#define AMEVCNTVOFF18_EL2 S3_4_C13_C11_0
1325#define AMEVCNTVOFF19_EL2 S3_4_C13_C11_1
1326#define AMEVCNTVOFF1A_EL2 S3_4_C13_C11_2
1327#define AMEVCNTVOFF1B_EL2 S3_4_C13_C11_3
1328#define AMEVCNTVOFF1C_EL2 S3_4_C13_C11_4
1329#define AMEVCNTVOFF1D_EL2 S3_4_C13_C11_5
1330#define AMEVCNTVOFF1E_EL2 S3_4_C13_C11_6
1331#define AMEVCNTVOFF1F_EL2 S3_4_C13_C11_7
1332
1333/*******************************************************************************
Zelalem Aweke79e3d292021-07-08 16:51:14 -05001334 * Realm management extension register definitions
1335 ******************************************************************************/
Zelalem Aweke79e3d292021-07-08 16:51:14 -05001336#define GPCCR_EL3 S3_6_C2_C1_6
Zelalem Aweke79e3d292021-07-08 16:51:14 -05001337#define GPTBR_EL3 S3_6_C2_C1_4
1338
Andre Przywara3edbfa72023-03-28 16:55:06 +01001339#define SCXTNUM_EL2 S3_4_C13_C0_7
1340
Zelalem Aweke79e3d292021-07-08 16:51:14 -05001341/*******************************************************************************
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +01001342 * RAS system registers
Sathees Balya0911df12018-12-06 13:33:24 +00001343 ******************************************************************************/
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +01001344#define DISR_EL1 S3_0_C12_C1_1
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +01001345#define DISR_A_BIT U(31)
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +01001346
Jeenu Viswambharan19f6cf22017-12-07 08:43:05 +00001347#define ERRIDR_EL1 S3_0_C5_C3_0
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +01001348#define ERRIDR_MASK U(0xffff)
Jeenu Viswambharan19f6cf22017-12-07 08:43:05 +00001349
1350#define ERRSELR_EL1 S3_0_C5_C3_1
1351
1352/* System register access to Standard Error Record registers */
1353#define ERXFR_EL1 S3_0_C5_C4_0
1354#define ERXCTLR_EL1 S3_0_C5_C4_1
1355#define ERXSTATUS_EL1 S3_0_C5_C4_2
1356#define ERXADDR_EL1 S3_0_C5_C4_3
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +00001357#define ERXPFGF_EL1 S3_0_C5_C4_4
1358#define ERXPFGCTL_EL1 S3_0_C5_C4_5
1359#define ERXPFGCDN_EL1 S3_0_C5_C4_6
Jan Dabros82ef8bf2018-08-30 13:52:23 +02001360#define ERXMISC0_EL1 S3_0_C5_C5_0
1361#define ERXMISC1_EL1 S3_0_C5_C5_1
Jeenu Viswambharan19f6cf22017-12-07 08:43:05 +00001362
johpow017d52a8f2022-03-09 16:23:04 -06001363#define ERXCTLR_ED_SHIFT U(0)
1364#define ERXCTLR_ED_BIT (U(1) << ERXCTLR_ED_SHIFT)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +00001365#define ERXCTLR_UE_BIT (U(1) << 4)
1366
1367#define ERXPFGCTL_UC_BIT (U(1) << 1)
1368#define ERXPFGCTL_UEU_BIT (U(1) << 2)
1369#define ERXPFGCTL_CDEN_BIT (U(1) << 31)
1370
1371/*******************************************************************************
1372 * Armv8.3 Pointer Authentication Registers
Sathees Balya0911df12018-12-06 13:33:24 +00001373 ******************************************************************************/
Antonio Nino Diaz594811b2019-01-31 11:58:00 +00001374#define APIAKeyLo_EL1 S3_0_C2_C1_0
1375#define APIAKeyHi_EL1 S3_0_C2_C1_1
1376#define APIBKeyLo_EL1 S3_0_C2_C1_2
1377#define APIBKeyHi_EL1 S3_0_C2_C1_3
1378#define APDAKeyLo_EL1 S3_0_C2_C2_0
1379#define APDAKeyHi_EL1 S3_0_C2_C2_1
1380#define APDBKeyLo_EL1 S3_0_C2_C2_2
1381#define APDBKeyHi_EL1 S3_0_C2_C2_3
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +00001382#define APGAKeyLo_EL1 S3_0_C2_C3_0
Antonio Nino Diaz594811b2019-01-31 11:58:00 +00001383#define APGAKeyHi_EL1 S3_0_C2_C3_1
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +00001384
Sathees Balya0911df12018-12-06 13:33:24 +00001385/*******************************************************************************
1386 * Armv8.4 Data Independent Timing Registers
1387 ******************************************************************************/
1388#define DIT S3_3_C4_C2_5
1389#define DIT_BIT BIT(24)
1390
John Tsichritzis1f9ff492019-03-04 16:41:26 +00001391/*******************************************************************************
1392 * Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field
1393 ******************************************************************************/
1394#define SSBS S3_3_C4_C2_6
1395
Justin Chadwell1c7c13a2019-07-18 14:25:33 +01001396/*******************************************************************************
1397 * Armv8.5 - Memory Tagging Extension Registers
1398 ******************************************************************************/
1399#define TFSRE0_EL1 S3_0_C5_C6_1
1400#define TFSR_EL1 S3_0_C5_C6_0
1401#define RGSR_EL1 S3_0_C1_C0_5
1402#define GCR_EL1 S3_0_C1_C0_6
1403
Madhukar Pappireddy90d65322019-10-30 14:24:39 -05001404/*******************************************************************************
Andre Przywarabdc76f12022-11-21 17:07:25 +00001405 * Armv8.5 - Random Number Generator Registers
1406 ******************************************************************************/
1407#define RNDR S3_3_C2_C4_0
1408#define RNDRRS S3_3_C2_C4_1
1409
1410/*******************************************************************************
johpow01f91e59f2021-08-04 19:38:18 -05001411 * FEAT_HCX - Extended Hypervisor Configuration Register
1412 ******************************************************************************/
johpow019baade32021-07-08 14:14:00 -05001413#define HCRX_EL2 S3_4_C1_C2_2
Juan Pablo Conde72e0da12023-02-22 10:09:52 -06001414#define HCRX_EL2_MSCEn_BIT (UL(1) << 11)
1415#define HCRX_EL2_MCE2_BIT (UL(1) << 10)
1416#define HCRX_EL2_CMOW_BIT (UL(1) << 9)
1417#define HCRX_EL2_VFNMI_BIT (UL(1) << 8)
1418#define HCRX_EL2_VINMI_BIT (UL(1) << 7)
1419#define HCRX_EL2_TALLINT_BIT (UL(1) << 6)
1420#define HCRX_EL2_SMPME_BIT (UL(1) << 5)
johpow019baade32021-07-08 14:14:00 -05001421#define HCRX_EL2_FGTnXS_BIT (UL(1) << 4)
1422#define HCRX_EL2_FnXS_BIT (UL(1) << 3)
1423#define HCRX_EL2_EnASR_BIT (UL(1) << 2)
1424#define HCRX_EL2_EnALS_BIT (UL(1) << 1)
1425#define HCRX_EL2_EnAS0_BIT (UL(1) << 0)
Juan Pablo Conde72e0da12023-02-22 10:09:52 -06001426#define HCRX_EL2_INIT_VAL ULL(0x0)
johpow01f91e59f2021-08-04 19:38:18 -05001427
1428/*******************************************************************************
Juan Pablo Condef7252982023-07-10 16:00:41 -05001429 * FEAT_FGT - Definitions for Fine-Grained Trap registers
1430 ******************************************************************************/
1431#define HFGITR_EL2_INIT_VAL ULL(0x180000000000000)
1432#define HFGRTR_EL2_INIT_VAL ULL(0xC4000000000000)
1433#define HFGWTR_EL2_INIT_VAL ULL(0xC4000000000000)
1434
1435/*******************************************************************************
Mark Brownc37eee72023-03-14 20:13:03 +00001436 * FEAT_TCR2 - Extended Translation Control Register
1437 ******************************************************************************/
1438#define TCR2_EL2 S3_4_C2_C0_3
1439
1440/*******************************************************************************
Mark Brown293a6612023-03-14 20:48:43 +00001441 * Permission indirection and overlay
1442 ******************************************************************************/
1443
1444#define PIRE0_EL2 S3_4_C10_C2_2
1445#define PIR_EL2 S3_4_C10_C2_3
1446#define POR_EL2 S3_4_C10_C2_4
1447#define S2PIR_EL2 S3_4_C10_C2_5
1448
1449/*******************************************************************************
Mark Brown326f2952023-03-14 21:33:04 +00001450 * FEAT_GCS - Guarded Control Stack Registers
1451 ******************************************************************************/
1452#define GCSCR_EL2 S3_4_C2_C5_0
1453#define GCSPR_EL2 S3_4_C2_C5_1
Manish Pandey5cfe5152024-01-09 15:55:20 +00001454#define GCSCR_EL1 S3_0_C2_C5_0
1455
1456#define GCSCR_EXLOCK_EN_BIT (UL(1) << 6)
Mark Brown326f2952023-03-14 21:33:04 +00001457
1458/*******************************************************************************
Madhukar Pappireddy90d65322019-10-30 14:24:39 -05001459 * Definitions for DynamicIQ Shared Unit registers
1460 ******************************************************************************/
1461#define CLUSTERPWRDN_EL1 S3_0_c15_c3_6
1462
1463/* CLUSTERPWRDN_EL1 register definitions */
1464#define DSU_CLUSTER_PWR_OFF 0
1465#define DSU_CLUSTER_PWR_ON 1
1466#define DSU_CLUSTER_PWR_MASK U(1)
Jacky Baidc4ed332023-09-13 09:21:40 +08001467#define DSU_CLUSTER_MEM_RET BIT(1)
Madhukar Pappireddy90d65322019-10-30 14:24:39 -05001468
Chris Kay03be39d2021-05-05 13:38:30 +01001469/*******************************************************************************
1470 * Definitions for CPU Power/Performance Management registers
1471 ******************************************************************************/
1472
1473#define CPUPPMCR_EL3 S3_6_C15_C2_0
1474#define CPUPPMCR_EL3_MPMMPINCTL_SHIFT UINT64_C(0)
1475#define CPUPPMCR_EL3_MPMMPINCTL_MASK UINT64_C(0x1)
1476
1477#define CPUMPMMCR_EL3 S3_6_C15_C2_1
1478#define CPUMPMMCR_EL3_MPMM_EN_SHIFT UINT64_C(0)
1479#define CPUMPMMCR_EL3_MPMM_EN_MASK UINT64_C(0x1)
1480
Andre Przywarac735f1c2022-11-25 14:10:13 +00001481/* alternative system register encoding for the "sb" speculation barrier */
1482#define SYSREG_SB S0_3_C3_C0_7
1483
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +01001484#endif /* ARCH_H */