blob: 5e21673740495fe4eb47509648c14026416b7632 [file] [log] [blame]
Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __ARCH_H__
32#define __ARCH_H__
33
Achin Gupta4f6ad662013-10-25 09:08:21 +010034
35/*******************************************************************************
36 * MIDR bit definitions
37 ******************************************************************************/
Soby Mathewc704cbc2014-08-14 11:33:56 +010038#define MIDR_IMPL_MASK 0xff
39#define MIDR_IMPL_SHIFT 0x18
Soby Mathew802f8652014-08-14 16:19:29 +010040#define MIDR_VAR_SHIFT 20
Soby Mathewc0884332014-09-22 12:11:36 +010041#define MIDR_VAR_BITS 4
Soby Mathew802f8652014-08-14 16:19:29 +010042#define MIDR_REV_SHIFT 0
Soby Mathewc0884332014-09-22 12:11:36 +010043#define MIDR_REV_BITS 4
Achin Gupta4f6ad662013-10-25 09:08:21 +010044#define MIDR_PN_MASK 0xfff
45#define MIDR_PN_SHIFT 0x4
Achin Gupta4f6ad662013-10-25 09:08:21 +010046
47/*******************************************************************************
48 * MPIDR macros
49 ******************************************************************************/
50#define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK
51#define MPIDR_CLUSTER_MASK MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS
52#define MPIDR_AFFINITY_BITS 8
53#define MPIDR_AFFLVL_MASK 0xff
54#define MPIDR_AFF0_SHIFT 0
55#define MPIDR_AFF1_SHIFT 8
56#define MPIDR_AFF2_SHIFT 16
57#define MPIDR_AFF3_SHIFT 32
58#define MPIDR_AFFINITY_MASK 0xff00ffffff
59#define MPIDR_AFFLVL_SHIFT 3
60#define MPIDR_AFFLVL0 0
61#define MPIDR_AFFLVL1 1
62#define MPIDR_AFFLVL2 2
63#define MPIDR_AFFLVL3 3
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000064#define MPIDR_AFFLVL0_VAL(mpidr) \
65 ((mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK)
66#define MPIDR_AFFLVL1_VAL(mpidr) \
67 ((mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK)
68#define MPIDR_AFFLVL2_VAL(mpidr) \
69 ((mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK)
70#define MPIDR_AFFLVL3_VAL(mpidr) \
71 ((mpidr >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK)
Soby Mathewe2b2d8f2014-12-04 14:14:12 +000072/*
73 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to
74 * add one while using this macro to define array sizes.
75 * TODO: Support only the first 3 affinity levels for now.
76 */
Achin Gupta4f6ad662013-10-25 09:08:21 +010077#define MPIDR_MAX_AFFLVL 2
78
79/* Constant to highlight the assumption that MPIDR allocation starts from 0 */
80#define FIRST_MPIDR 0
81
82/*******************************************************************************
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010083 * Definitions for CPU system register interface to GICv3
84 ******************************************************************************/
85#define ICC_SRE_EL1 S3_0_C12_C12_5
86#define ICC_SRE_EL2 S3_4_C12_C9_5
87#define ICC_SRE_EL3 S3_6_C12_C12_5
88#define ICC_CTLR_EL1 S3_0_C12_C12_4
89#define ICC_CTLR_EL3 S3_6_C12_C12_4
90#define ICC_PMR_EL1 S3_0_C4_C6_0
91
92/*******************************************************************************
Achin Guptac2b43af2013-10-31 11:27:43 +000093 * Generic timer memory mapped registers & offsets
94 ******************************************************************************/
95#define CNTCR_OFF 0x000
96#define CNTFID_OFF 0x020
97
98#define CNTCR_EN (1 << 0)
99#define CNTCR_HDBG (1 << 1)
Sandrine Bailleux3fa98472014-03-31 11:25:18 +0100100#define CNTCR_FCREQ(x) ((x) << 8)
Achin Guptac2b43af2013-10-31 11:27:43 +0000101
102/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +0100103 * System register bit definitions
104 ******************************************************************************/
105/* CLIDR definitions */
106#define LOUIS_SHIFT 21
107#define LOC_SHIFT 24
108#define CLIDR_FIELD_WIDTH 3
109
110/* CSSELR definitions */
111#define LEVEL_SHIFT 1
112
113/* D$ set/way op type defines */
114#define DCISW 0x0
115#define DCCISW 0x1
116#define DCCSW 0x2
117
118/* ID_AA64PFR0_EL1 definitions */
119#define ID_AA64PFR0_EL0_SHIFT 0
120#define ID_AA64PFR0_EL1_SHIFT 4
121#define ID_AA64PFR0_EL2_SHIFT 8
122#define ID_AA64PFR0_EL3_SHIFT 12
123#define ID_AA64PFR0_ELX_MASK 0xf
124
125/* ID_PFR1_EL1 definitions */
126#define ID_PFR1_VIRTEXT_SHIFT 12
127#define ID_PFR1_VIRTEXT_MASK 0xf
128#define GET_VIRT_EXT(id) ((id >> ID_PFR1_VIRTEXT_SHIFT) \
129 & ID_PFR1_VIRTEXT_MASK)
130
131/* SCTLR definitions */
132#define SCTLR_EL2_RES1 ((1 << 29) | (1 << 28) | (1 << 23) | (1 << 22) | \
133 (1 << 18) | (1 << 16) | (1 << 11) | (1 << 5) | \
134 (1 << 4))
135
136#define SCTLR_EL1_RES1 ((1 << 29) | (1 << 28) | (1 << 23) | (1 << 22) | \
137 (1 << 11))
Jens Wiklanderc93c9df2014-09-04 10:23:27 +0200138#define SCTLR_AARCH32_EL1_RES1 \
139 ((1 << 23) | (1 << 22) | (1 << 11) | (1 << 4) | \
140 (1 << 3))
141
Achin Gupta4f6ad662013-10-25 09:08:21 +0100142#define SCTLR_M_BIT (1 << 0)
143#define SCTLR_A_BIT (1 << 1)
144#define SCTLR_C_BIT (1 << 2)
145#define SCTLR_SA_BIT (1 << 3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100146#define SCTLR_I_BIT (1 << 12)
147#define SCTLR_WXN_BIT (1 << 19)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100148#define SCTLR_EE_BIT (1 << 25)
149
Achin Gupta4f6ad662013-10-25 09:08:21 +0100150/* CPACR_El1 definitions */
151#define CPACR_EL1_FPEN(x) (x << 20)
152#define CPACR_EL1_FP_TRAP_EL0 0x1
153#define CPACR_EL1_FP_TRAP_ALL 0x2
154#define CPACR_EL1_FP_TRAP_NONE 0x3
155
156/* SCR definitions */
157#define SCR_RES1_BITS ((1 << 4) | (1 << 5))
158#define SCR_TWE_BIT (1 << 13)
159#define SCR_TWI_BIT (1 << 12)
160#define SCR_ST_BIT (1 << 11)
161#define SCR_RW_BIT (1 << 10)
162#define SCR_SIF_BIT (1 << 9)
163#define SCR_HCE_BIT (1 << 8)
164#define SCR_SMD_BIT (1 << 7)
165#define SCR_EA_BIT (1 << 3)
166#define SCR_FIQ_BIT (1 << 2)
167#define SCR_IRQ_BIT (1 << 1)
168#define SCR_NS_BIT (1 << 0)
Achin Gupta27b895e2014-05-04 18:38:28 +0100169#define SCR_VALID_BIT_MASK 0x2f8f
Achin Gupta4f6ad662013-10-25 09:08:21 +0100170
171/* HCR definitions */
172#define HCR_RW_BIT (1ull << 31)
173#define HCR_AMO_BIT (1 << 5)
174#define HCR_IMO_BIT (1 << 4)
175#define HCR_FMO_BIT (1 << 3)
176
177/* CNTHCTL_EL2 definitions */
Andrew Thoelke4e126072014-06-04 21:10:52 +0100178#define EVNTEN_BIT (1 << 2)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100179#define EL1PCEN_BIT (1 << 1)
180#define EL1PCTEN_BIT (1 << 0)
181
182/* CNTKCTL_EL1 definitions */
183#define EL0PTEN_BIT (1 << 9)
184#define EL0VTEN_BIT (1 << 8)
185#define EL0PCTEN_BIT (1 << 0)
186#define EL0VCTEN_BIT (1 << 1)
Sandrine Bailleux798140d2014-07-17 16:06:39 +0100187#define EVNTEN_BIT (1 << 2)
188#define EVNTDIR_BIT (1 << 3)
189#define EVNTI_SHIFT 4
190#define EVNTI_MASK 0xf
Achin Gupta4f6ad662013-10-25 09:08:21 +0100191
192/* CPTR_EL3 definitions */
Harry Liebel4f603682014-01-14 18:11:48 +0000193#define TCPAC_BIT (1 << 31)
194#define TTA_BIT (1 << 20)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100195#define TFP_BIT (1 << 10)
196
197/* CPSR/SPSR definitions */
198#define DAIF_FIQ_BIT (1 << 0)
199#define DAIF_IRQ_BIT (1 << 1)
200#define DAIF_ABT_BIT (1 << 2)
201#define DAIF_DBG_BIT (1 << 3)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100202#define SPSR_DAIF_SHIFT 6
203#define SPSR_DAIF_MASK 0xf
204
205#define SPSR_AIF_SHIFT 6
206#define SPSR_AIF_MASK 0x7
207
208#define SPSR_E_SHIFT 9
209#define SPSR_E_MASK 0x1
210#define SPSR_E_LITTLE 0x0
211#define SPSR_E_BIG 0x1
212
213#define SPSR_T_SHIFT 5
214#define SPSR_T_MASK 0x1
215#define SPSR_T_ARM 0x0
216#define SPSR_T_THUMB 0x1
217
218#define DISABLE_ALL_EXCEPTIONS \
219 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT)
220
Achin Gupta4f6ad662013-10-25 09:08:21 +0100221
222/*
223 * TCR defintions
224 */
225#define TCR_EL3_RES1 ((1UL << 31) | (1UL << 23))
Lin Ma741a3822014-06-27 16:56:30 -0700226#define TCR_EL1_IPS_SHIFT 32
227#define TCR_EL3_PS_SHIFT 16
228
229/* (internal) physical address size bits in EL3/EL1 */
230#define TCR_PS_BITS_4GB (0x0)
231#define TCR_PS_BITS_64GB (0x1)
232#define TCR_PS_BITS_1TB (0x2)
233#define TCR_PS_BITS_4TB (0x3)
234#define TCR_PS_BITS_16TB (0x4)
235#define TCR_PS_BITS_256TB (0x5)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100236
Lin Ma741a3822014-06-27 16:56:30 -0700237#define ADDR_MASK_48_TO_63 0xFFFF000000000000UL
238#define ADDR_MASK_44_TO_47 0x0000F00000000000UL
239#define ADDR_MASK_42_TO_43 0x00000C0000000000UL
240#define ADDR_MASK_40_TO_41 0x0000030000000000UL
241#define ADDR_MASK_36_TO_39 0x000000F000000000UL
242#define ADDR_MASK_32_TO_35 0x0000000F00000000UL
Achin Gupta4f6ad662013-10-25 09:08:21 +0100243
244#define TCR_RGN_INNER_NC (0x0 << 8)
245#define TCR_RGN_INNER_WBA (0x1 << 8)
246#define TCR_RGN_INNER_WT (0x2 << 8)
247#define TCR_RGN_INNER_WBNA (0x3 << 8)
248
249#define TCR_RGN_OUTER_NC (0x0 << 10)
250#define TCR_RGN_OUTER_WBA (0x1 << 10)
251#define TCR_RGN_OUTER_WT (0x2 << 10)
252#define TCR_RGN_OUTER_WBNA (0x3 << 10)
253
254#define TCR_SH_NON_SHAREABLE (0x0 << 12)
255#define TCR_SH_OUTER_SHAREABLE (0x2 << 12)
256#define TCR_SH_INNER_SHAREABLE (0x3 << 12)
257
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100258#define MODE_SP_SHIFT 0x0
259#define MODE_SP_MASK 0x1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100260#define MODE_SP_EL0 0x0
261#define MODE_SP_ELX 0x1
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100262
263#define MODE_RW_SHIFT 0x4
264#define MODE_RW_MASK 0x1
265#define MODE_RW_64 0x0
266#define MODE_RW_32 0x1
267
268#define MODE_EL_SHIFT 0x2
269#define MODE_EL_MASK 0x3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100270#define MODE_EL3 0x3
271#define MODE_EL2 0x2
272#define MODE_EL1 0x1
273#define MODE_EL0 0x0
274
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100275#define MODE32_SHIFT 0
276#define MODE32_MASK 0xf
277#define MODE32_usr 0x0
278#define MODE32_fiq 0x1
279#define MODE32_irq 0x2
280#define MODE32_svc 0x3
281#define MODE32_mon 0x6
282#define MODE32_abt 0x7
283#define MODE32_hyp 0xa
284#define MODE32_und 0xb
285#define MODE32_sys 0xf
Achin Gupta4f6ad662013-10-25 09:08:21 +0100286
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100287#define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK)
288#define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK)
289#define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK)
290#define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100291
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100292#define SPSR_64(el, sp, daif) \
293 (MODE_RW_64 << MODE_RW_SHIFT | \
294 ((el) & MODE_EL_MASK) << MODE_EL_SHIFT | \
295 ((sp) & MODE_SP_MASK) << MODE_SP_SHIFT | \
296 ((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)
297
298#define SPSR_MODE32(mode, isa, endian, aif) \
299 (MODE_RW_32 << MODE_RW_SHIFT | \
300 ((mode) & MODE32_MASK) << MODE32_SHIFT | \
301 ((isa) & SPSR_T_MASK) << SPSR_T_SHIFT | \
302 ((endian) & SPSR_E_MASK) << SPSR_E_SHIFT | \
303 ((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100304
Achin Gupta4f6ad662013-10-25 09:08:21 +0100305
Achin Gupta405406d2014-05-09 12:00:17 +0100306/* Physical timer control register bit fields shifts and masks */
307#define CNTP_CTL_ENABLE_SHIFT 0
308#define CNTP_CTL_IMASK_SHIFT 1
309#define CNTP_CTL_ISTATUS_SHIFT 2
310
311#define CNTP_CTL_ENABLE_MASK 1
312#define CNTP_CTL_IMASK_MASK 1
313#define CNTP_CTL_ISTATUS_MASK 1
314
315#define get_cntp_ctl_enable(x) ((x >> CNTP_CTL_ENABLE_SHIFT) & \
316 CNTP_CTL_ENABLE_MASK)
317#define get_cntp_ctl_imask(x) ((x >> CNTP_CTL_IMASK_SHIFT) & \
318 CNTP_CTL_IMASK_MASK)
319#define get_cntp_ctl_istatus(x) ((x >> CNTP_CTL_ISTATUS_SHIFT) & \
320 CNTP_CTL_ISTATUS_MASK)
321
322#define set_cntp_ctl_enable(x) (x |= 1 << CNTP_CTL_ENABLE_SHIFT)
323#define set_cntp_ctl_imask(x) (x |= 1 << CNTP_CTL_IMASK_SHIFT)
324
325#define clr_cntp_ctl_enable(x) (x &= ~(1 << CNTP_CTL_ENABLE_SHIFT))
326#define clr_cntp_ctl_imask(x) (x &= ~(1 << CNTP_CTL_IMASK_SHIFT))
327
Achin Gupta4f6ad662013-10-25 09:08:21 +0100328/* Miscellaneous MMU related constants */
329#define NUM_2MB_IN_GB (1 << 9)
330#define NUM_4K_IN_2MB (1 << 9)
Achin Guptaa0cd9892014-02-09 13:30:38 +0000331#define NUM_GB_IN_4GB (1 << 2)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100332
333#define TWO_MB_SHIFT 21
334#define ONE_GB_SHIFT 30
335#define FOUR_KB_SHIFT 12
336
337#define ONE_GB_INDEX(x) ((x) >> ONE_GB_SHIFT)
338#define TWO_MB_INDEX(x) ((x) >> TWO_MB_SHIFT)
339#define FOUR_KB_INDEX(x) ((x) >> FOUR_KB_SHIFT)
340
341#define INVALID_DESC 0x0
342#define BLOCK_DESC 0x1
343#define TABLE_DESC 0x3
344
345#define FIRST_LEVEL_DESC_N ONE_GB_SHIFT
346#define SECOND_LEVEL_DESC_N TWO_MB_SHIFT
347#define THIRD_LEVEL_DESC_N FOUR_KB_SHIFT
348
349#define LEVEL1 1
350#define LEVEL2 2
351#define LEVEL3 3
352
353#define XN (1ull << 2)
354#define PXN (1ull << 1)
355#define CONT_HINT (1ull << 0)
356
357#define UPPER_ATTRS(x) (x & 0x7) << 52
358#define NON_GLOBAL (1 << 9)
359#define ACCESS_FLAG (1 << 8)
360#define NSH (0x0 << 6)
361#define OSH (0x2 << 6)
362#define ISH (0x3 << 6)
363
Jon Medhurstbb1fe202014-01-24 15:41:33 +0000364#define PAGE_SIZE_SHIFT FOUR_KB_SHIFT
365#define PAGE_SIZE (1 << PAGE_SIZE_SHIFT)
366#define PAGE_SIZE_MASK (PAGE_SIZE - 1)
367#define IS_PAGE_ALIGNED(addr) (((addr) & PAGE_SIZE_MASK) == 0)
368
369#define XLAT_ENTRY_SIZE_SHIFT 3 /* Each MMU table entry is 8 bytes (1 << 3) */
370#define XLAT_ENTRY_SIZE (1 << XLAT_ENTRY_SIZE_SHIFT)
371
372#define XLAT_TABLE_SIZE_SHIFT PAGE_SIZE_SHIFT
373#define XLAT_TABLE_SIZE (1 << XLAT_TABLE_SIZE_SHIFT)
374
375/* Values for number of entries in each MMU translation table */
376#define XLAT_TABLE_ENTRIES_SHIFT (XLAT_TABLE_SIZE_SHIFT - XLAT_ENTRY_SIZE_SHIFT)
377#define XLAT_TABLE_ENTRIES (1 << XLAT_TABLE_ENTRIES_SHIFT)
378#define XLAT_TABLE_ENTRIES_MASK (XLAT_TABLE_ENTRIES - 1)
379
380/* Values to convert a memory address to an index into a translation table */
381#define L3_XLAT_ADDRESS_SHIFT PAGE_SIZE_SHIFT
382#define L2_XLAT_ADDRESS_SHIFT (L3_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
383#define L1_XLAT_ADDRESS_SHIFT (L2_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000384
Achin Gupta4f6ad662013-10-25 09:08:21 +0100385/*
386 * AP[1] bit is ignored by hardware and is
387 * treated as if it is One in EL2/EL3
388 */
389#define AP_RO (0x1 << 5)
390#define AP_RW (0x0 << 5)
391
392#define NS (0x1 << 3)
393#define ATTR_SO_INDEX 0x2
394#define ATTR_DEVICE_INDEX 0x1
395#define ATTR_IWBWA_OWBWA_NTR_INDEX 0x0
396#define LOWER_ATTRS(x) (((x) & 0xfff) << 2)
397#define ATTR_SO (0x0)
398#define ATTR_DEVICE (0x4)
399#define ATTR_IWBWA_OWBWA_NTR (0xff)
400#define MAIR_ATTR_SET(attr, index) (attr << (index << 3))
401
402/* Exception Syndrome register bits and bobs */
403#define ESR_EC_SHIFT 26
404#define ESR_EC_MASK 0x3f
405#define ESR_EC_LENGTH 6
406#define EC_UNKNOWN 0x0
407#define EC_WFE_WFI 0x1
408#define EC_AARCH32_CP15_MRC_MCR 0x3
409#define EC_AARCH32_CP15_MRRC_MCRR 0x4
410#define EC_AARCH32_CP14_MRC_MCR 0x5
411#define EC_AARCH32_CP14_LDC_STC 0x6
412#define EC_FP_SIMD 0x7
413#define EC_AARCH32_CP10_MRC 0x8
414#define EC_AARCH32_CP14_MRRC_MCRR 0xc
415#define EC_ILLEGAL 0xe
416#define EC_AARCH32_SVC 0x11
417#define EC_AARCH32_HVC 0x12
418#define EC_AARCH32_SMC 0x13
419#define EC_AARCH64_SVC 0x15
420#define EC_AARCH64_HVC 0x16
421#define EC_AARCH64_SMC 0x17
422#define EC_AARCH64_SYS 0x18
423#define EC_IABORT_LOWER_EL 0x20
424#define EC_IABORT_CUR_EL 0x21
425#define EC_PC_ALIGN 0x22
426#define EC_DABORT_LOWER_EL 0x24
427#define EC_DABORT_CUR_EL 0x25
428#define EC_SP_ALIGN 0x26
429#define EC_AARCH32_FP 0x28
430#define EC_AARCH64_FP 0x2c
431#define EC_SERROR 0x2f
432
433#define EC_BITS(x) (x >> ESR_EC_SHIFT) & ESR_EC_MASK
434
Dan Handleyed6ff952014-05-14 17:44:19 +0100435/*******************************************************************************
436 * Definitions of register offsets and fields in the CNTCTLBase Frame of the
437 * system level implementation of the Generic Timer.
438 ******************************************************************************/
439#define CNTNSAR 0x4
440#define CNTNSAR_NS_SHIFT(x) x
441
442#define CNTACR_BASE(x) (0x40 + (x << 2))
443#define CNTACR_RPCT_SHIFT 0x0
444#define CNTACR_RVCT_SHIFT 0x1
445#define CNTACR_RFRQ_SHIFT 0x2
446#define CNTACR_RVOFF_SHIFT 0x3
447#define CNTACR_RWVT_SHIFT 0x4
448#define CNTACR_RWPT_SHIFT 0x5
449
Achin Gupta4f6ad662013-10-25 09:08:21 +0100450#endif /* __ARCH_H__ */