feat(cpufeat): enable FEAT_SME for FEAT_STATE_CHECKED
Add support for runtime detection (ENABLE_SME_FOR_NS=2), by splitting
feat_sme_supported() into an ID register reading function and a
second function to report the support status. That function considers
both build time settings and runtime information (if needed), and is
used before we do SME specific setup.
Change the FVP platform default to the now supported dynamic option
(=2),so the right decision can be made by the code at runtime.
Change-Id: Ida9ccf737db5be20865b84f42b1f9587be0626ab
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index 8663ab8..2ce1be8 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -393,8 +393,10 @@
#define ID_AA64PFR1_MPAM_FRAC_SHIFT ULL(16)
#define ID_AA64PFR1_MPAM_FRAC_MASK ULL(0xf)
-#define ID_AA64PFR1_EL1_SME_SHIFT U(24)
-#define ID_AA64PFR1_EL1_SME_MASK ULL(0xf)
+#define ID_AA64PFR1_EL1_SME_SHIFT U(24)
+#define ID_AA64PFR1_EL1_SME_MASK ULL(0xf)
+#define ID_AA64PFR1_EL1_SME_NOT_SUPPORTED ULL(0x0)
+#define ID_AA64PFR1_EL1_SME_SUPPORTED ULL(0x1)
/* ID_PFR1_EL1 definitions */
#define ID_PFR1_VIRTEXT_SHIFT U(12)
@@ -1004,7 +1006,9 @@
#define SMCR_EL3 S3_6_C1_C2_6
/* ID_AA64SMFR0_EL1 definitions */
-#define ID_AA64SMFR0_EL1_FA64_BIT (UL(1) << 63)
+#define ID_AA64SMFR0_EL1_SME_FA64_SHIFT U(63)
+#define ID_AA64SMFR0_EL1_SME_FA64_MASK U(0x1)
+#define ID_AA64SMFR0_EL1_SME_FA64_SUPPORTED U(0x1)
/* SMCR_ELx definitions */
#define SMCR_ELX_LEN_SHIFT U(0)