| commit | 307f34bee848835dc6346e09822bace711028cf9 | [log] [tgz] |
|---|---|---|
| author | Alexei Fedorov <Alexei.Fedorov@arm.com> | Fri May 14 11:21:56 2021 +0100 |
| committer | Alexei Fedorov <Alexei.Fedorov@arm.com> | Fri May 14 12:19:54 2021 +0100 |
| tree | 6fb7f4b1cee78b86e25592419cd7d5979a5a12f6 | |
| parent | fdef0b8d753e161eb07a0b78a223b3fe262d3402 [diff] |
fix(security): Set MDCR_EL3.MCCD bit This patch adds setting MDCR_EL3.MCCD in 'el3_arch_init_common' macro to disable cycle counting by PMCCNTR_EL0 in EL3 when FEAT_PMUv3p7 is implemented. This fixes failing test 'Leak PMU CYCLE counter values from EL3 on PSCI suspend SMC' on FVP models with 'has_v8_7_pmu_extension' parameter set to 1 or 2. Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com> Change-Id: I2ad3ef501b31ee11306f76cb5a61032ecfd0fbda