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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
johpow01fa59c6f2020-10-02 13:41:11 -05002 * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
Varun Wadekar787a1292018-06-18 16:15:51 -07003 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01004 *
dp-armfa3cf0b2017-05-03 09:38:09 +01005 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01006 */
7
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +01008#ifndef ARCH_H
9#define ARCH_H
Achin Gupta4f6ad662013-10-25 09:08:21 +010010
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <lib/utils_def.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010012
13/*******************************************************************************
14 * MIDR bit definitions
15 ******************************************************************************/
Varun Wadekarc6a11f62017-05-25 18:04:48 -070016#define MIDR_IMPL_MASK U(0xff)
17#define MIDR_IMPL_SHIFT U(0x18)
18#define MIDR_VAR_SHIFT U(20)
19#define MIDR_VAR_BITS U(4)
20#define MIDR_VAR_MASK U(0xf)
21#define MIDR_REV_SHIFT U(0)
22#define MIDR_REV_BITS U(4)
23#define MIDR_REV_MASK U(0xf)
24#define MIDR_PN_MASK U(0xfff)
25#define MIDR_PN_SHIFT U(0x4)
Achin Gupta4f6ad662013-10-25 09:08:21 +010026
27/*******************************************************************************
28 * MPIDR macros
29 ******************************************************************************/
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010030#define MPIDR_MT_MASK (ULL(1) << 24)
Achin Gupta4f6ad662013-10-25 09:08:21 +010031#define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK
Varun Wadekarc6a11f62017-05-25 18:04:48 -070032#define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS)
33#define MPIDR_AFFINITY_BITS U(8)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010034#define MPIDR_AFFLVL_MASK ULL(0xff)
Varun Wadekarc6a11f62017-05-25 18:04:48 -070035#define MPIDR_AFF0_SHIFT U(0)
36#define MPIDR_AFF1_SHIFT U(8)
37#define MPIDR_AFF2_SHIFT U(16)
38#define MPIDR_AFF3_SHIFT U(32)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000039#define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010040#define MPIDR_AFFINITY_MASK ULL(0xff00ffffff)
Varun Wadekarc6a11f62017-05-25 18:04:48 -070041#define MPIDR_AFFLVL_SHIFT U(3)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000042#define MPIDR_AFFLVL0 ULL(0x0)
43#define MPIDR_AFFLVL1 ULL(0x1)
44#define MPIDR_AFFLVL2 ULL(0x2)
45#define MPIDR_AFFLVL3 ULL(0x3)
46#define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000047#define MPIDR_AFFLVL0_VAL(mpidr) \
Antonio Nino Diaz34235a32018-07-11 16:45:49 +010048 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK)
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000049#define MPIDR_AFFLVL1_VAL(mpidr) \
Antonio Nino Diaz34235a32018-07-11 16:45:49 +010050 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK)
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000051#define MPIDR_AFFLVL2_VAL(mpidr) \
Antonio Nino Diaz34235a32018-07-11 16:45:49 +010052 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK)
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000053#define MPIDR_AFFLVL3_VAL(mpidr) \
Antonio Nino Diaz34235a32018-07-11 16:45:49 +010054 (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK)
Soby Mathewe2b2d8f2014-12-04 14:14:12 +000055/*
56 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to
57 * add one while using this macro to define array sizes.
58 * TODO: Support only the first 3 affinity levels for now.
59 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070060#define MPIDR_MAX_AFFLVL U(2)
Achin Gupta4f6ad662013-10-25 09:08:21 +010061
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000062#define MPID_MASK (MPIDR_MT_MASK | \
63 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \
64 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \
65 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \
66 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT))
67
68#define MPIDR_AFF_ID(mpid, n) \
69 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK)
70
71/*
72 * An invalid MPID. This value can be used by functions that return an MPID to
73 * indicate an error.
74 */
75#define INVALID_MPID U(0xFFFFFFFF)
Achin Gupta4f6ad662013-10-25 09:08:21 +010076
77/*******************************************************************************
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010078 * Definitions for CPU system register interface to GICv3
79 ******************************************************************************/
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000080#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7
81#define ICC_SGI1R S3_0_C12_C11_5
82#define ICC_SRE_EL1 S3_0_C12_C12_5
83#define ICC_SRE_EL2 S3_4_C12_C9_5
84#define ICC_SRE_EL3 S3_6_C12_C12_5
85#define ICC_CTLR_EL1 S3_0_C12_C12_4
86#define ICC_CTLR_EL3 S3_6_C12_C12_4
87#define ICC_PMR_EL1 S3_0_C4_C6_0
88#define ICC_RPR_EL1 S3_0_C12_C11_3
89#define ICC_IGRPEN1_EL3 S3_6_c12_c12_7
90#define ICC_IGRPEN0_EL1 S3_0_c12_c12_6
91#define ICC_HPPIR0_EL1 S3_0_c12_c8_2
92#define ICC_HPPIR1_EL1 S3_0_c12_c12_2
93#define ICC_IAR0_EL1 S3_0_c12_c8_0
94#define ICC_IAR1_EL1 S3_0_c12_c12_0
95#define ICC_EOIR0_EL1 S3_0_c12_c8_1
96#define ICC_EOIR1_EL1 S3_0_c12_c12_1
97#define ICC_SGI0R_EL1 S3_0_c12_c11_7
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010098
99/*******************************************************************************
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000100 * Definitions for EL2 system registers for save/restore routine
101 ******************************************************************************/
102
103#define CNTPOFF_EL2 S3_4_C14_C0_6
104#define HAFGRTR_EL2 S3_4_C3_C1_6
105#define HDFGRTR_EL2 S3_4_C3_C1_4
106#define HDFGWTR_EL2 S3_4_C3_C1_5
107#define HFGITR_EL2 S3_4_C1_C1_6
108#define HFGRTR_EL2 S3_4_C1_C1_4
109#define HFGWTR_EL2 S3_4_C1_C1_5
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000110#define ICH_HCR_EL2 S3_4_C12_C11_0
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000111#define ICH_VMCR_EL2 S3_4_C12_C11_7
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000112#define MPAMVPM0_EL2 S3_4_C10_C5_0
113#define MPAMVPM1_EL2 S3_4_C10_C5_1
114#define MPAMVPM2_EL2 S3_4_C10_C5_2
115#define MPAMVPM3_EL2 S3_4_C10_C5_3
116#define MPAMVPM4_EL2 S3_4_C10_C5_4
117#define MPAMVPM5_EL2 S3_4_C10_C5_5
118#define MPAMVPM6_EL2 S3_4_C10_C5_6
119#define MPAMVPM7_EL2 S3_4_C10_C5_7
120#define MPAMVPMV_EL2 S3_4_C10_C4_1
Max Shvetsovc9e2c922020-02-17 16:15:47 +0000121#define TRFCR_EL2 S3_4_C1_C2_1
122#define PMSCR_EL2 S3_4_C9_C9_0
123#define TFSR_EL2 S3_4_C5_C6_0
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000124
125/*******************************************************************************
Achin Guptac2b43af2013-10-31 11:27:43 +0000126 * Generic timer memory mapped registers & offsets
127 ******************************************************************************/
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700128#define CNTCR_OFF U(0x000)
Yann Gautier007d7452019-04-17 13:47:07 +0200129#define CNTCV_OFF U(0x008)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700130#define CNTFID_OFF U(0x020)
Achin Guptac2b43af2013-10-31 11:27:43 +0000131
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700132#define CNTCR_EN (U(1) << 0)
133#define CNTCR_HDBG (U(1) << 1)
Sandrine Bailleux3fa98472014-03-31 11:25:18 +0100134#define CNTCR_FCREQ(x) ((x) << 8)
Achin Guptac2b43af2013-10-31 11:27:43 +0000135
136/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +0100137 * System register bit definitions
138 ******************************************************************************/
139/* CLIDR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700140#define LOUIS_SHIFT U(21)
141#define LOC_SHIFT U(24)
Alexei Fedorova95a5892019-07-29 17:22:53 +0100142#define CTYPE_SHIFT(n) U(3 * (n - 1))
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700143#define CLIDR_FIELD_WIDTH U(3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100144
145/* CSSELR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700146#define LEVEL_SHIFT U(1)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100147
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100148/* Data cache set/way op type defines */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700149#define DCISW U(0x0)
150#define DCCISW U(0x1)
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +0000151#if ERRATA_A53_827319
152#define DCCSW DCCISW
153#else
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700154#define DCCSW U(0x2)
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +0000155#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100156
157/* ID_AA64PFR0_EL1 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700158#define ID_AA64PFR0_EL0_SHIFT U(0)
159#define ID_AA64PFR0_EL1_SHIFT U(4)
160#define ID_AA64PFR0_EL2_SHIFT U(8)
161#define ID_AA64PFR0_EL3_SHIFT U(12)
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100162#define ID_AA64PFR0_AMU_SHIFT U(44)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100163#define ID_AA64PFR0_AMU_MASK ULL(0xf)
johpow01fa59c6f2020-10-02 13:41:11 -0500164#define ID_AA64PFR0_AMU_NOT_SUPPORTED U(0x0)
165#define ID_AA64PFR0_AMU_V1 U(0x1)
166#define ID_AA64PFR0_AMU_V1P1 U(0x2)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100167#define ID_AA64PFR0_ELX_MASK ULL(0xf)
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100168#define ID_AA64PFR0_GIC_SHIFT U(24)
169#define ID_AA64PFR0_GIC_WIDTH U(4)
170#define ID_AA64PFR0_GIC_MASK ULL(0xf)
David Cunadoce88eee2017-10-20 11:30:57 +0100171#define ID_AA64PFR0_SVE_SHIFT U(32)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100172#define ID_AA64PFR0_SVE_MASK ULL(0xf)
Max Shvetsovc4502772021-03-22 11:59:37 +0000173#define ID_AA64PFR0_SVE_LENGTH U(4)
Achin Gupta023c1552019-10-11 14:44:05 +0100174#define ID_AA64PFR0_SEL2_SHIFT U(36)
Artsem Artsemenkaa5334472019-11-26 16:40:31 +0000175#define ID_AA64PFR0_SEL2_MASK ULL(0xf)
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +0100176#define ID_AA64PFR0_MPAM_SHIFT U(40)
177#define ID_AA64PFR0_MPAM_MASK ULL(0xf)
Sathees Balya0911df12018-12-06 13:33:24 +0000178#define ID_AA64PFR0_DIT_SHIFT U(48)
179#define ID_AA64PFR0_DIT_MASK ULL(0xf)
180#define ID_AA64PFR0_DIT_LENGTH U(4)
181#define ID_AA64PFR0_DIT_SUPPORTED U(1)
Dimitris Papastamos43e05ec2018-01-02 15:53:01 +0000182#define ID_AA64PFR0_CSV2_SHIFT U(56)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100183#define ID_AA64PFR0_CSV2_MASK ULL(0xf)
Dimitris Papastamos43e05ec2018-01-02 15:53:01 +0000184#define ID_AA64PFR0_CSV2_LENGTH U(4)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100185
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100186/* Exception level handling */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100187#define EL_IMPL_NONE ULL(0)
188#define EL_IMPL_A64ONLY ULL(1)
189#define EL_IMPL_A64_A32 ULL(2)
Jeenu Viswambharan2a9b8822017-02-21 14:40:44 +0000190
Manish V Badarkhef7ee0642021-07-07 16:27:10 +0100191/* ID_AA64DFR0_EL1.TraceVer definitions */
192#define ID_AA64DFR0_TRACEVER_SHIFT U(4)
193#define ID_AA64DFR0_TRACEVER_MASK ULL(0xf)
194#define ID_AA64DFR0_TRACEVER_SUPPORTED ULL(1)
195#define ID_AA64DFR0_TRACEVER_LENGTH U(4)
Manish V Badarkhe8ce33942021-07-18 02:26:27 +0100196#define ID_AA64DFR0_TRACEFILT_SHIFT U(40)
197#define ID_AA64DFR0_TRACEFILT_MASK U(0xf)
198#define ID_AA64DFR0_TRACEFILT_SUPPORTED U(1)
199#define ID_AA64DFR0_TRACEFILT_LENGTH U(4)
Manish V Badarkhef7ee0642021-07-07 16:27:10 +0100200
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100201/* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */
202#define ID_AA64DFR0_PMS_SHIFT U(32)
203#define ID_AA64DFR0_PMS_MASK ULL(0xf)
Achin Gupta92712a52015-09-03 14:18:02 +0100204
Manish V Badarkhe20df29c2021-07-02 09:10:56 +0100205/* ID_AA64DFR0_EL1.TraceBuffer definitions */
206#define ID_AA64DFR0_TRACEBUFFER_SHIFT U(44)
207#define ID_AA64DFR0_TRACEBUFFER_MASK ULL(0xf)
208#define ID_AA64DFR0_TRACEBUFFER_SUPPORTED ULL(1)
209
Javier Almansa Sobrinof3a4c542020-11-23 18:38:15 +0000210/* ID_AA64DFR0_EL1.MTPMU definitions (for ARMv8.6+) */
211#define ID_AA64DFR0_MTPMU_SHIFT U(48)
212#define ID_AA64DFR0_MTPMU_MASK ULL(0xf)
213#define ID_AA64DFR0_MTPMU_SUPPORTED ULL(1)
214
Tomas Pilar6fd816e2020-10-28 15:34:12 +0000215/* ID_AA64ISAR0_EL1 definitions */
216#define ID_AA64ISAR0_RNDR_SHIFT U(60)
217#define ID_AA64ISAR0_RNDR_MASK ULL(0xf)
218
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000219/* ID_AA64ISAR1_EL1 definitions */
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000220#define ID_AA64ISAR1_EL1 S3_0_C0_C6_1
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000221#define ID_AA64ISAR1_GPI_SHIFT U(28)
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000222#define ID_AA64ISAR1_GPI_MASK ULL(0xf)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000223#define ID_AA64ISAR1_GPA_SHIFT U(24)
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000224#define ID_AA64ISAR1_GPA_MASK ULL(0xf)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000225#define ID_AA64ISAR1_API_SHIFT U(8)
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000226#define ID_AA64ISAR1_API_MASK ULL(0xf)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000227#define ID_AA64ISAR1_APA_SHIFT U(4)
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000228#define ID_AA64ISAR1_APA_MASK ULL(0xf)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000229
Antonio Nino Diazc326c342019-01-11 11:20:10 +0000230/* ID_AA64MMFR0_EL1 definitions */
231#define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0)
232#define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf)
233
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700234#define PARANGE_0000 U(32)
235#define PARANGE_0001 U(36)
236#define PARANGE_0010 U(40)
237#define PARANGE_0011 U(42)
238#define PARANGE_0100 U(44)
239#define PARANGE_0101 U(48)
Antonio Nino Diazb9ef6642017-11-17 09:52:53 +0000240#define PARANGE_0110 U(52)
Antonio Nino Diazd1beee22016-12-13 15:28:54 +0000241
Jimmy Brisson83573892020-04-16 10:48:02 -0500242#define ID_AA64MMFR0_EL1_ECV_SHIFT U(60)
243#define ID_AA64MMFR0_EL1_ECV_MASK ULL(0xf)
244#define ID_AA64MMFR0_EL1_ECV_NOT_SUPPORTED ULL(0x0)
245#define ID_AA64MMFR0_EL1_ECV_SUPPORTED ULL(0x1)
246#define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2)
247
Jimmy Brissonecc3c672020-04-16 10:47:56 -0500248#define ID_AA64MMFR0_EL1_FGT_SHIFT U(56)
249#define ID_AA64MMFR0_EL1_FGT_MASK ULL(0xf)
250#define ID_AA64MMFR0_EL1_FGT_SUPPORTED ULL(0x1)
251#define ID_AA64MMFR0_EL1_FGT_NOT_SUPPORTED ULL(0x0)
252
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100253#define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100254#define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf)
255#define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0)
256#define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100257
258#define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100259#define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf)
260#define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED ULL(0x0)
261#define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED ULL(0xf)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100262
263#define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100264#define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf)
265#define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1)
266#define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100267
johpow013e24c162020-04-22 14:05:13 -0500268/* ID_AA64MMFR1_EL1 definitions */
269#define ID_AA64MMFR1_EL1_TWED_SHIFT U(32)
270#define ID_AA64MMFR1_EL1_TWED_MASK ULL(0xf)
271#define ID_AA64MMFR1_EL1_TWED_SUPPORTED ULL(0x1)
272#define ID_AA64MMFR1_EL1_TWED_NOT_SUPPORTED ULL(0x0)
273
Alexei Fedorovc082f032020-11-25 14:07:05 +0000274#define ID_AA64MMFR1_EL1_PAN_SHIFT U(20)
275#define ID_AA64MMFR1_EL1_PAN_MASK ULL(0xf)
276#define ID_AA64MMFR1_EL1_PAN_NOT_SUPPORTED ULL(0x0)
277#define ID_AA64MMFR1_EL1_PAN_SUPPORTED ULL(0x1)
278#define ID_AA64MMFR1_EL1_PAN2_SUPPORTED ULL(0x2)
279#define ID_AA64MMFR1_EL1_PAN3_SUPPORTED ULL(0x3)
280
Daniel Boulby44b43332020-11-25 16:36:46 +0000281#define ID_AA64MMFR1_EL1_VHE_SHIFT U(8)
282#define ID_AA64MMFR1_EL1_VHE_MASK ULL(0xf)
283
johpow01f91e59f2021-08-04 19:38:18 -0500284#define ID_AA64MMFR1_EL1_HCX_SHIFT U(40)
285#define ID_AA64MMFR1_EL1_HCX_MASK ULL(0xf)
286#define ID_AA64MMFR1_EL1_HCX_SUPPORTED ULL(0x1)
287#define ID_AA64MMFR1_EL1_HCX_NOT_SUPPORTED ULL(0x0)
288
Antonio Nino Diazc326c342019-01-11 11:20:10 +0000289/* ID_AA64MMFR2_EL1 definitions */
290#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2
Sathees Balya74155972019-01-25 11:36:01 +0000291
292#define ID_AA64MMFR2_EL1_ST_SHIFT U(28)
293#define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf)
294
Antonio Nino Diazc326c342019-01-11 11:20:10 +0000295#define ID_AA64MMFR2_EL1_CNP_SHIFT U(0)
296#define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf)
297
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000298/* ID_AA64PFR1_EL1 definitions */
299#define ID_AA64PFR1_EL1_SSBS_SHIFT U(4)
300#define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf)
301
302#define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */
303
Alexei Fedorov90f2e882019-05-24 12:17:09 +0100304#define ID_AA64PFR1_EL1_BT_SHIFT U(0)
305#define ID_AA64PFR1_EL1_BT_MASK ULL(0xf)
306
307#define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */
308
Soby Mathew830f0ad2019-07-12 09:23:38 +0100309#define ID_AA64PFR1_EL1_MTE_SHIFT U(8)
310#define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf)
311
Alexei Fedorovaf54f6e2020-12-01 13:22:25 +0000312/* Memory Tagging Extension is not implemented */
313#define MTE_UNIMPLEMENTED U(0)
314/* FEAT_MTE: MTE instructions accessible at EL0 are implemented */
315#define MTE_IMPLEMENTED_EL0 U(1)
316/* FEAT_MTE2: Full MTE is implemented */
317#define MTE_IMPLEMENTED_ELX U(2)
318/*
319 * FEAT_MTE3: MTE is implemented with support for
320 * asymmetric Tag Check Fault handling
321 */
322#define MTE_IMPLEMENTED_ASY U(3)
Soby Mathew830f0ad2019-07-12 09:23:38 +0100323
Alexei Fedorov19933552020-05-26 13:16:41 +0100324#define ID_AA64PFR1_MPAM_FRAC_SHIFT ULL(16)
325#define ID_AA64PFR1_MPAM_FRAC_MASK ULL(0xf)
326
Achin Gupta4f6ad662013-10-25 09:08:21 +0100327/* ID_PFR1_EL1 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700328#define ID_PFR1_VIRTEXT_SHIFT U(12)
329#define ID_PFR1_VIRTEXT_MASK U(0xf)
Antonio Nino Diaz34235a32018-07-11 16:45:49 +0100330#define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \
Achin Gupta4f6ad662013-10-25 09:08:21 +0100331 & ID_PFR1_VIRTEXT_MASK)
332
333/* SCTLR definitions */
David Cunadofee86532017-04-13 22:38:29 +0100334#define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700335 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
336 (U(1) << 11) | (U(1) << 5) | (U(1) << 4))
Achin Gupta4f6ad662013-10-25 09:08:21 +0100337
John Powella5c66362020-03-20 14:21:05 -0500338#define SCTLR_EL1_RES1 ((UL(1) << 29) | (UL(1) << 28) | (UL(1) << 23) | \
339 (UL(1) << 22) | (UL(1) << 20) | (UL(1) << 11))
Alexei Fedorovc082f032020-11-25 14:07:05 +0000340
Jens Wiklanderc93c9df2014-09-04 10:23:27 +0200341#define SCTLR_AARCH32_EL1_RES1 \
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700342 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \
343 (U(1) << 4) | (U(1) << 3))
Jens Wiklanderc93c9df2014-09-04 10:23:27 +0200344
David Cunadofee86532017-04-13 22:38:29 +0100345#define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
346 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
347 (U(1) << 11) | (U(1) << 5) | (U(1) << 4))
348
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000349#define SCTLR_M_BIT (ULL(1) << 0)
350#define SCTLR_A_BIT (ULL(1) << 1)
351#define SCTLR_C_BIT (ULL(1) << 2)
352#define SCTLR_SA_BIT (ULL(1) << 3)
353#define SCTLR_SA0_BIT (ULL(1) << 4)
354#define SCTLR_CP15BEN_BIT (ULL(1) << 5)
Alexei Fedorovc082f032020-11-25 14:07:05 +0000355#define SCTLR_nAA_BIT (ULL(1) << 6)
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000356#define SCTLR_ITD_BIT (ULL(1) << 7)
357#define SCTLR_SED_BIT (ULL(1) << 8)
358#define SCTLR_UMA_BIT (ULL(1) << 9)
Alexei Fedorovc082f032020-11-25 14:07:05 +0000359#define SCTLR_EnRCTX_BIT (ULL(1) << 10)
360#define SCTLR_EOS_BIT (ULL(1) << 11)
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000361#define SCTLR_I_BIT (ULL(1) << 12)
Alexei Fedorovc31ab382019-07-10 10:49:12 +0100362#define SCTLR_EnDB_BIT (ULL(1) << 13)
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000363#define SCTLR_DZE_BIT (ULL(1) << 14)
364#define SCTLR_UCT_BIT (ULL(1) << 15)
365#define SCTLR_NTWI_BIT (ULL(1) << 16)
366#define SCTLR_NTWE_BIT (ULL(1) << 18)
367#define SCTLR_WXN_BIT (ULL(1) << 19)
Alexei Fedorovc082f032020-11-25 14:07:05 +0000368#define SCTLR_TSCXT_BIT (ULL(1) << 20)
Louis Mayencourt78a0aed2019-02-20 12:11:41 +0000369#define SCTLR_IESB_BIT (ULL(1) << 21)
Alexei Fedorovc082f032020-11-25 14:07:05 +0000370#define SCTLR_EIS_BIT (ULL(1) << 22)
371#define SCTLR_SPAN_BIT (ULL(1) << 23)
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000372#define SCTLR_E0E_BIT (ULL(1) << 24)
373#define SCTLR_EE_BIT (ULL(1) << 25)
374#define SCTLR_UCI_BIT (ULL(1) << 26)
Alexei Fedorovc31ab382019-07-10 10:49:12 +0100375#define SCTLR_EnDA_BIT (ULL(1) << 27)
Alexei Fedorovc082f032020-11-25 14:07:05 +0000376#define SCTLR_nTLSMD_BIT (ULL(1) << 28)
377#define SCTLR_LSMAOE_BIT (ULL(1) << 29)
Alexei Fedorovc31ab382019-07-10 10:49:12 +0100378#define SCTLR_EnIB_BIT (ULL(1) << 30)
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000379#define SCTLR_EnIA_BIT (ULL(1) << 31)
Alexei Fedorov90f2e882019-05-24 12:17:09 +0100380#define SCTLR_BT0_BIT (ULL(1) << 35)
381#define SCTLR_BT1_BIT (ULL(1) << 36)
382#define SCTLR_BT_BIT (ULL(1) << 36)
Alexei Fedorovc082f032020-11-25 14:07:05 +0000383#define SCTLR_ITFSB_BIT (ULL(1) << 37)
384#define SCTLR_TCF0_SHIFT U(38)
385#define SCTLR_TCF0_MASK ULL(3)
386
387/* Tag Check Faults in EL0 have no effect on the PE */
388#define SCTLR_TCF0_NO_EFFECT U(0)
389/* Tag Check Faults in EL0 cause a synchronous exception */
390#define SCTLR_TCF0_SYNC U(1)
391/* Tag Check Faults in EL0 are asynchronously accumulated */
392#define SCTLR_TCF0_ASYNC U(2)
393/*
394 * Tag Check Faults in EL0 cause a synchronous exception on reads,
395 * and are asynchronously accumulated on writes
396 */
397#define SCTLR_TCF0_SYNCR_ASYNCW U(3)
398
399#define SCTLR_TCF_SHIFT U(40)
400#define SCTLR_TCF_MASK ULL(3)
401
402/* Tag Check Faults in EL1 have no effect on the PE */
403#define SCTLR_TCF_NO_EFFECT U(0)
404/* Tag Check Faults in EL1 cause a synchronous exception */
405#define SCTLR_TCF_SYNC U(1)
406/* Tag Check Faults in EL1 are asynchronously accumulated */
407#define SCTLR_TCF_ASYNC U(2)
408/*
409 * Tag Check Faults in EL1 cause a synchronous exception on reads,
410 * and are asynchronously accumulated on writes
411 */
412#define SCTLR_TCF_SYNCR_ASYNCW U(3)
413
414#define SCTLR_ATA0_BIT (ULL(1) << 42)
415#define SCTLR_ATA_BIT (ULL(1) << 43)
Daniel Boulby44b43332020-11-25 16:36:46 +0000416#define SCTLR_DSSBS_SHIFT U(44)
417#define SCTLR_DSSBS_BIT (ULL(1) << SCTLR_DSSBS_SHIFT)
Alexei Fedorovc082f032020-11-25 14:07:05 +0000418#define SCTLR_TWEDEn_BIT (ULL(1) << 45)
419#define SCTLR_TWEDEL_SHIFT U(46)
420#define SCTLR_TWEDEL_MASK ULL(0xf)
421#define SCTLR_EnASR_BIT (ULL(1) << 54)
422#define SCTLR_EnAS0_BIT (ULL(1) << 55)
423#define SCTLR_EnALS_BIT (ULL(1) << 56)
424#define SCTLR_EPAN_BIT (ULL(1) << 57)
David Cunadofee86532017-04-13 22:38:29 +0100425#define SCTLR_RESET_VAL SCTLR_EL3_RES1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100426
Alexei Fedorovc082f032020-11-25 14:07:05 +0000427/* CPACR_EL1 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700428#define CPACR_EL1_FPEN(x) ((x) << 20)
Jimmy Brissoned202072020-08-04 16:18:52 -0500429#define CPACR_EL1_FP_TRAP_EL0 UL(0x1)
430#define CPACR_EL1_FP_TRAP_ALL UL(0x2)
431#define CPACR_EL1_FP_TRAP_NONE UL(0x3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100432
433/* SCR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700434#define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5))
johpow013e24c162020-04-22 14:05:13 -0500435#define SCR_TWEDEL_SHIFT U(30)
436#define SCR_TWEDEL_MASK ULL(0xf)
johpow01f91e59f2021-08-04 19:38:18 -0500437#define SCR_HXEn_BIT (UL(1) << 38)
johpow01fa59c6f2020-10-02 13:41:11 -0500438#define SCR_AMVOFFEN_BIT (UL(1) << 35)
johpow013e24c162020-04-22 14:05:13 -0500439#define SCR_TWEDEn_BIT (UL(1) << 29)
johpow01fa59c6f2020-10-02 13:41:11 -0500440#define SCR_ECVEN_BIT (UL(1) << 28)
441#define SCR_FGTEN_BIT (UL(1) << 27)
Jimmy Brissoned202072020-08-04 16:18:52 -0500442#define SCR_ATA_BIT (UL(1) << 26)
443#define SCR_FIEN_BIT (UL(1) << 21)
444#define SCR_EEL2_BIT (UL(1) << 18)
445#define SCR_API_BIT (UL(1) << 17)
446#define SCR_APK_BIT (UL(1) << 16)
447#define SCR_TERR_BIT (UL(1) << 15)
448#define SCR_TWE_BIT (UL(1) << 13)
449#define SCR_TWI_BIT (UL(1) << 12)
450#define SCR_ST_BIT (UL(1) << 11)
451#define SCR_RW_BIT (UL(1) << 10)
452#define SCR_SIF_BIT (UL(1) << 9)
453#define SCR_HCE_BIT (UL(1) << 8)
454#define SCR_SMD_BIT (UL(1) << 7)
455#define SCR_EA_BIT (UL(1) << 3)
456#define SCR_FIQ_BIT (UL(1) << 2)
457#define SCR_IRQ_BIT (UL(1) << 1)
458#define SCR_NS_BIT (UL(1) << 0)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700459#define SCR_VALID_BIT_MASK U(0x2f8f)
David Cunadofee86532017-04-13 22:38:29 +0100460#define SCR_RESET_VAL SCR_RES1_BITS
Achin Gupta4f6ad662013-10-25 09:08:21 +0100461
David Cunadofee86532017-04-13 22:38:29 +0100462/* MDCR_EL3 definitions */
Alexei Fedorov307f34b2021-05-14 11:21:56 +0100463#define MDCR_EnPMSN_BIT (ULL(1) << 36)
464#define MDCR_MPMX_BIT (ULL(1) << 35)
465#define MDCR_MCCD_BIT (ULL(1) << 34)
Manish V Badarkhee1cccb42021-06-23 20:02:39 +0100466#define MDCR_NSTB(x) ((x) << 24)
467#define MDCR_NSTB_EL1 ULL(0x3)
468#define MDCR_NSTBE (ULL(1) << 26)
Javier Almansa Sobrinof3a4c542020-11-23 18:38:15 +0000469#define MDCR_MTPME_BIT (ULL(1) << 28)
Alexei Fedorov307f34b2021-05-14 11:21:56 +0100470#define MDCR_TDCC_BIT (ULL(1) << 27)
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100471#define MDCR_SCCD_BIT (ULL(1) << 23)
Alexei Fedorov307f34b2021-05-14 11:21:56 +0100472#define MDCR_EPMAD_BIT (ULL(1) << 21)
473#define MDCR_EDAD_BIT (ULL(1) << 20)
474#define MDCR_TTRF_BIT (ULL(1) << 19)
475#define MDCR_STE_BIT (ULL(1) << 18)
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100476#define MDCR_SPME_BIT (ULL(1) << 17)
477#define MDCR_SDD_BIT (ULL(1) << 16)
dp-arm595d0d52017-02-08 11:51:50 +0000478#define MDCR_SPD32(x) ((x) << 14)
Antonio Nino Diaz3fbd3f52019-02-18 16:55:43 +0000479#define MDCR_SPD32_LEGACY ULL(0x0)
480#define MDCR_SPD32_DISABLE ULL(0x2)
481#define MDCR_SPD32_ENABLE ULL(0x3)
dp-armee3457b2017-05-23 09:32:49 +0100482#define MDCR_NSPB(x) ((x) << 12)
Antonio Nino Diaz3fbd3f52019-02-18 16:55:43 +0000483#define MDCR_NSPB_EL1 ULL(0x3)
484#define MDCR_TDOSA_BIT (ULL(1) << 10)
485#define MDCR_TDA_BIT (ULL(1) << 9)
486#define MDCR_TPM_BIT (ULL(1) << 6)
Antonio Nino Diaz3fbd3f52019-02-18 16:55:43 +0000487#define MDCR_EL3_RESET_VAL ULL(0x0)
dp-arm595d0d52017-02-08 11:51:50 +0000488
David Cunadofee86532017-04-13 22:38:29 +0100489/* MDCR_EL2 definitions */
Javier Almansa Sobrinof3a4c542020-11-23 18:38:15 +0000490#define MDCR_EL2_MTPME (U(1) << 28)
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100491#define MDCR_EL2_HLP (U(1) << 26)
Manish V Badarkhee1cccb42021-06-23 20:02:39 +0100492#define MDCR_EL2_E2TB(x) ((x) << 24)
493#define MDCR_EL2_E2TB_EL1 U(0x3)
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100494#define MDCR_EL2_HCCD (U(1) << 23)
495#define MDCR_EL2_TTRF (U(1) << 19)
496#define MDCR_EL2_HPMD (U(1) << 17)
dp-armee3457b2017-05-23 09:32:49 +0100497#define MDCR_EL2_TPMS (U(1) << 14)
498#define MDCR_EL2_E2PB(x) ((x) << 12)
499#define MDCR_EL2_E2PB_EL1 U(0x3)
David Cunadofee86532017-04-13 22:38:29 +0100500#define MDCR_EL2_TDRA_BIT (U(1) << 11)
501#define MDCR_EL2_TDOSA_BIT (U(1) << 10)
502#define MDCR_EL2_TDA_BIT (U(1) << 9)
503#define MDCR_EL2_TDE_BIT (U(1) << 8)
504#define MDCR_EL2_HPME_BIT (U(1) << 7)
505#define MDCR_EL2_TPM_BIT (U(1) << 6)
506#define MDCR_EL2_TPMCR_BIT (U(1) << 5)
507#define MDCR_EL2_RESET_VAL U(0x0)
508
509/* HSTR_EL2 definitions */
510#define HSTR_EL2_RESET_VAL U(0x0)
511#define HSTR_EL2_T_MASK U(0xff)
512
513/* CNTHP_CTL_EL2 definitions */
514#define CNTHP_CTL_ENABLE_BIT (U(1) << 0)
515#define CNTHP_CTL_RESET_VAL U(0x0)
516
517/* VTTBR_EL2 definitions */
518#define VTTBR_RESET_VAL ULL(0x0)
519#define VTTBR_VMID_MASK ULL(0xff)
520#define VTTBR_VMID_SHIFT U(48)
521#define VTTBR_BADDR_MASK ULL(0xffffffffffff)
522#define VTTBR_BADDR_SHIFT U(0)
dp-arm595d0d52017-02-08 11:51:50 +0000523
Achin Gupta4f6ad662013-10-25 09:08:21 +0100524/* HCR definitions */
Gary Morrison3d7f6542021-01-27 13:08:47 -0600525#define HCR_RESET_VAL ULL(0x0)
johpow01fa59c6f2020-10-02 13:41:11 -0500526#define HCR_AMVOFFEN_BIT (ULL(1) << 51)
Gary Morrison3d7f6542021-01-27 13:08:47 -0600527#define HCR_TEA_BIT (ULL(1) << 47)
Jeenu Viswambharancbad6612018-08-15 14:29:29 +0100528#define HCR_API_BIT (ULL(1) << 41)
529#define HCR_APK_BIT (ULL(1) << 40)
Manish V Badarkhe2801ed42020-04-28 04:53:32 +0100530#define HCR_E2H_BIT (ULL(1) << 34)
Gary Morrison3d7f6542021-01-27 13:08:47 -0600531#define HCR_HCD_BIT (ULL(1) << 29)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000532#define HCR_TGE_BIT (ULL(1) << 27)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700533#define HCR_RW_SHIFT U(31)
534#define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT)
Gary Morrison3d7f6542021-01-27 13:08:47 -0600535#define HCR_TWE_BIT (ULL(1) << 14)
536#define HCR_TWI_BIT (ULL(1) << 13)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100537#define HCR_AMO_BIT (ULL(1) << 5)
538#define HCR_IMO_BIT (ULL(1) << 4)
539#define HCR_FMO_BIT (ULL(1) << 3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100540
Gerald Lejeune851dc7e2016-03-22 11:11:46 +0100541/* ISR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700542#define ISR_A_SHIFT U(8)
543#define ISR_I_SHIFT U(7)
544#define ISR_F_SHIFT U(6)
Gerald Lejeune851dc7e2016-03-22 11:11:46 +0100545
Achin Gupta4f6ad662013-10-25 09:08:21 +0100546/* CNTHCTL_EL2 definitions */
David Cunadofee86532017-04-13 22:38:29 +0100547#define CNTHCTL_RESET_VAL U(0x0)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700548#define EVNTEN_BIT (U(1) << 2)
549#define EL1PCEN_BIT (U(1) << 1)
550#define EL1PCTEN_BIT (U(1) << 0)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100551
552/* CNTKCTL_EL1 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700553#define EL0PTEN_BIT (U(1) << 9)
554#define EL0VTEN_BIT (U(1) << 8)
555#define EL0PCTEN_BIT (U(1) << 0)
556#define EL0VCTEN_BIT (U(1) << 1)
557#define EVNTEN_BIT (U(1) << 2)
558#define EVNTDIR_BIT (U(1) << 3)
559#define EVNTI_SHIFT U(4)
560#define EVNTI_MASK U(0xf)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100561
562/* CPTR_EL3 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700563#define TCPAC_BIT (U(1) << 31)
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100564#define TAM_BIT (U(1) << 30)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700565#define TTA_BIT (U(1) << 20)
566#define TFP_BIT (U(1) << 10)
David Cunadoce88eee2017-10-20 11:30:57 +0100567#define CPTR_EZ_BIT (U(1) << 8)
Max Shvetsovc4502772021-03-22 11:59:37 +0000568#define CPTR_EL3_RESET_VAL (TCPAC_BIT | TAM_BIT | TTA_BIT | TFP_BIT & ~(CPTR_EZ_BIT))
David Cunadofee86532017-04-13 22:38:29 +0100569
570/* CPTR_EL2 definitions */
571#define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff)))
572#define CPTR_EL2_TCPAC_BIT (U(1) << 31)
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100573#define CPTR_EL2_TAM_BIT (U(1) << 30)
David Cunadofee86532017-04-13 22:38:29 +0100574#define CPTR_EL2_TTA_BIT (U(1) << 20)
575#define CPTR_EL2_TFP_BIT (U(1) << 10)
David Cunadoce88eee2017-10-20 11:30:57 +0100576#define CPTR_EL2_TZ_BIT (U(1) << 8)
David Cunadofee86532017-04-13 22:38:29 +0100577#define CPTR_EL2_RESET_VAL CPTR_EL2_RES1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100578
579/* CPSR/SPSR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700580#define DAIF_FIQ_BIT (U(1) << 0)
581#define DAIF_IRQ_BIT (U(1) << 1)
582#define DAIF_ABT_BIT (U(1) << 2)
583#define DAIF_DBG_BIT (U(1) << 3)
584#define SPSR_DAIF_SHIFT U(6)
585#define SPSR_DAIF_MASK U(0xf)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100586
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700587#define SPSR_AIF_SHIFT U(6)
588#define SPSR_AIF_MASK U(0x7)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100589
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700590#define SPSR_E_SHIFT U(9)
591#define SPSR_E_MASK U(0x1)
592#define SPSR_E_LITTLE U(0x0)
593#define SPSR_E_BIG U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100594
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700595#define SPSR_T_SHIFT U(5)
596#define SPSR_T_MASK U(0x1)
597#define SPSR_T_ARM U(0x0)
598#define SPSR_T_THUMB U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100599
Dimitris Papastamosc52ebdc2017-12-18 13:46:21 +0000600#define SPSR_M_SHIFT U(4)
601#define SPSR_M_MASK U(0x1)
602#define SPSR_M_AARCH64 U(0x0)
603#define SPSR_M_AARCH32 U(0x1)
604
Alexei Fedorov813c9f92020-03-03 13:31:58 +0000605#define SPSR_EL_SHIFT U(2)
606#define SPSR_EL_WIDTH U(2)
607
Daniel Boulby44b43332020-11-25 16:36:46 +0000608#define SPSR_SSBS_SHIFT_AARCH64 U(12)
609#define SPSR_SSBS_BIT_AARCH64 (ULL(1) << SPSR_SSBS_SHIFT_AARCH64)
610#define SPSR_SSBS_SHIFT_AARCH32 U(23)
611#define SPSR_SSBS_BIT_AARCH32 (ULL(1) << SPSR_SSBS_SHIFT_AARCH32)
612
613#define SPSR_PAN_BIT BIT_64(22)
614
615#define SPSR_DIT_BIT BIT(24)
616
617#define SPSR_TCO_BIT_AARCH64 BIT_64(25)
John Tsichritzis55534172019-07-23 11:12:41 +0100618
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100619#define DISABLE_ALL_EXCEPTIONS \
620 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT)
621
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000622#define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT)
623
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000624/*
625 * RMR_EL3 definitions
626 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700627#define RMR_EL3_RR_BIT (U(1) << 1)
628#define RMR_EL3_AA64_BIT (U(1) << 0)
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000629
630/*
631 * HI-VECTOR address for AArch32 state
632 */
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000633#define HI_VECTOR_BASE U(0xFFFF0000)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100634
635/*
636 * TCR defintions
637 */
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000638#define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23))
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100639#define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23))
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700640#define TCR_EL1_IPS_SHIFT U(32)
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100641#define TCR_EL2_PS_SHIFT U(16)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700642#define TCR_EL3_PS_SHIFT U(16)
Lin Ma741a3822014-06-27 16:56:30 -0700643
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100644#define TCR_TxSZ_MIN ULL(16)
645#define TCR_TxSZ_MAX ULL(39)
Sathees Balya74155972019-01-25 11:36:01 +0000646#define TCR_TxSZ_MAX_TTST ULL(48)
Antonio Nino Diazd48ae612016-08-02 09:21:41 +0100647
Antonio Nino Diaz37f97a52019-03-27 11:10:31 +0000648#define TCR_T0SZ_SHIFT U(0)
649#define TCR_T1SZ_SHIFT U(16)
650
Lin Ma741a3822014-06-27 16:56:30 -0700651/* (internal) physical address size bits in EL3/EL1 */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100652#define TCR_PS_BITS_4GB ULL(0x0)
653#define TCR_PS_BITS_64GB ULL(0x1)
654#define TCR_PS_BITS_1TB ULL(0x2)
655#define TCR_PS_BITS_4TB ULL(0x3)
656#define TCR_PS_BITS_16TB ULL(0x4)
657#define TCR_PS_BITS_256TB ULL(0x5)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100658
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700659#define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000)
660#define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000)
661#define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000)
662#define ADDR_MASK_40_TO_41 ULL(0x0000030000000000)
663#define ADDR_MASK_36_TO_39 ULL(0x000000F000000000)
664#define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100665
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100666#define TCR_RGN_INNER_NC (ULL(0x0) << 8)
667#define TCR_RGN_INNER_WBA (ULL(0x1) << 8)
668#define TCR_RGN_INNER_WT (ULL(0x2) << 8)
669#define TCR_RGN_INNER_WBNA (ULL(0x3) << 8)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100670
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100671#define TCR_RGN_OUTER_NC (ULL(0x0) << 10)
672#define TCR_RGN_OUTER_WBA (ULL(0x1) << 10)
673#define TCR_RGN_OUTER_WT (ULL(0x2) << 10)
674#define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100675
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100676#define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12)
677#define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12)
678#define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100679
Antonio Nino Diaz37f97a52019-03-27 11:10:31 +0000680#define TCR_RGN1_INNER_NC (ULL(0x0) << 24)
681#define TCR_RGN1_INNER_WBA (ULL(0x1) << 24)
682#define TCR_RGN1_INNER_WT (ULL(0x2) << 24)
683#define TCR_RGN1_INNER_WBNA (ULL(0x3) << 24)
684
685#define TCR_RGN1_OUTER_NC (ULL(0x0) << 26)
686#define TCR_RGN1_OUTER_WBA (ULL(0x1) << 26)
687#define TCR_RGN1_OUTER_WT (ULL(0x2) << 26)
688#define TCR_RGN1_OUTER_WBNA (ULL(0x3) << 26)
689
690#define TCR_SH1_NON_SHAREABLE (ULL(0x0) << 28)
691#define TCR_SH1_OUTER_SHAREABLE (ULL(0x2) << 28)
692#define TCR_SH1_INNER_SHAREABLE (ULL(0x3) << 28)
693
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100694#define TCR_TG0_SHIFT U(14)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100695#define TCR_TG0_MASK ULL(3)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100696#define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT)
697#define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT)
698#define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT)
699
Antonio Nino Diaz37f97a52019-03-27 11:10:31 +0000700#define TCR_TG1_SHIFT U(30)
701#define TCR_TG1_MASK ULL(3)
702#define TCR_TG1_16K (ULL(1) << TCR_TG1_SHIFT)
703#define TCR_TG1_4K (ULL(2) << TCR_TG1_SHIFT)
704#define TCR_TG1_64K (ULL(3) << TCR_TG1_SHIFT)
705
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100706#define TCR_EPD0_BIT (ULL(1) << 7)
707#define TCR_EPD1_BIT (ULL(1) << 23)
Antonio Nino Diazc8274a82017-09-15 10:30:34 +0100708
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700709#define MODE_SP_SHIFT U(0x0)
710#define MODE_SP_MASK U(0x1)
711#define MODE_SP_EL0 U(0x0)
712#define MODE_SP_ELX U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100713
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700714#define MODE_RW_SHIFT U(0x4)
715#define MODE_RW_MASK U(0x1)
716#define MODE_RW_64 U(0x0)
717#define MODE_RW_32 U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100718
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700719#define MODE_EL_SHIFT U(0x2)
720#define MODE_EL_MASK U(0x3)
Alexei Fedorov813c9f92020-03-03 13:31:58 +0000721#define MODE_EL_WIDTH U(0x2)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700722#define MODE_EL3 U(0x3)
723#define MODE_EL2 U(0x2)
724#define MODE_EL1 U(0x1)
725#define MODE_EL0 U(0x0)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100726
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700727#define MODE32_SHIFT U(0)
728#define MODE32_MASK U(0xf)
729#define MODE32_usr U(0x0)
730#define MODE32_fiq U(0x1)
731#define MODE32_irq U(0x2)
732#define MODE32_svc U(0x3)
733#define MODE32_mon U(0x6)
734#define MODE32_abt U(0x7)
735#define MODE32_hyp U(0xa)
736#define MODE32_und U(0xb)
737#define MODE32_sys U(0xf)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100738
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100739#define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK)
740#define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK)
741#define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK)
742#define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100743
John Tsichritzis55534172019-07-23 11:12:41 +0100744#define SPSR_64(el, sp, daif) \
745 (((MODE_RW_64 << MODE_RW_SHIFT) | \
746 (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \
747 (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \
748 (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) & \
749 (~(SPSR_SSBS_BIT_AARCH64)))
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100750
751#define SPSR_MODE32(mode, isa, endian, aif) \
John Tsichritzis55534172019-07-23 11:12:41 +0100752 (((MODE_RW_32 << MODE_RW_SHIFT) | \
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700753 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \
754 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \
755 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \
John Tsichritzis55534172019-07-23 11:12:41 +0100756 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) & \
757 (~(SPSR_SSBS_BIT_AARCH32)))
Achin Gupta4f6ad662013-10-25 09:08:21 +0100758
Dan Handley0cdebbd2015-03-30 17:15:16 +0100759/*
Isla Mitchellc4a1a072017-08-07 11:20:13 +0100760 * TTBR Definitions
761 */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100762#define TTBR_CNP_BIT ULL(0x1)
Isla Mitchellc4a1a072017-08-07 11:20:13 +0100763
764/*
Dan Handley0cdebbd2015-03-30 17:15:16 +0100765 * CTR_EL0 definitions
766 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700767#define CTR_CWG_SHIFT U(24)
768#define CTR_CWG_MASK U(0xf)
769#define CTR_ERG_SHIFT U(20)
770#define CTR_ERG_MASK U(0xf)
771#define CTR_DMINLINE_SHIFT U(16)
772#define CTR_DMINLINE_MASK U(0xf)
773#define CTR_L1IP_SHIFT U(14)
774#define CTR_L1IP_MASK U(0x3)
775#define CTR_IMINLINE_SHIFT U(0)
776#define CTR_IMINLINE_MASK U(0xf)
Dan Handley0cdebbd2015-03-30 17:15:16 +0100777
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700778#define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100779
Achin Gupta405406d2014-05-09 12:00:17 +0100780/* Physical timer control register bit fields shifts and masks */
johpow01fa59c6f2020-10-02 13:41:11 -0500781#define CNTP_CTL_ENABLE_SHIFT U(0)
782#define CNTP_CTL_IMASK_SHIFT U(1)
783#define CNTP_CTL_ISTATUS_SHIFT U(2)
Achin Gupta405406d2014-05-09 12:00:17 +0100784
johpow01fa59c6f2020-10-02 13:41:11 -0500785#define CNTP_CTL_ENABLE_MASK U(1)
786#define CNTP_CTL_IMASK_MASK U(1)
787#define CNTP_CTL_ISTATUS_MASK U(1)
Achin Gupta405406d2014-05-09 12:00:17 +0100788
Varun Wadekar787a1292018-06-18 16:15:51 -0700789/* Physical timer control macros */
790#define CNTP_CTL_ENABLE_BIT (U(1) << CNTP_CTL_ENABLE_SHIFT)
791#define CNTP_CTL_IMASK_BIT (U(1) << CNTP_CTL_IMASK_SHIFT)
792
Achin Gupta4f6ad662013-10-25 09:08:21 +0100793/* Exception Syndrome register bits and bobs */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700794#define ESR_EC_SHIFT U(26)
795#define ESR_EC_MASK U(0x3f)
796#define ESR_EC_LENGTH U(6)
Justin Chadwell83e04882019-08-20 11:01:52 +0100797#define ESR_ISS_SHIFT U(0)
798#define ESR_ISS_LENGTH U(25)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700799#define EC_UNKNOWN U(0x0)
800#define EC_WFE_WFI U(0x1)
801#define EC_AARCH32_CP15_MRC_MCR U(0x3)
802#define EC_AARCH32_CP15_MRRC_MCRR U(0x4)
803#define EC_AARCH32_CP14_MRC_MCR U(0x5)
804#define EC_AARCH32_CP14_LDC_STC U(0x6)
805#define EC_FP_SIMD U(0x7)
806#define EC_AARCH32_CP10_MRC U(0x8)
807#define EC_AARCH32_CP14_MRRC_MCRR U(0xc)
808#define EC_ILLEGAL U(0xe)
809#define EC_AARCH32_SVC U(0x11)
810#define EC_AARCH32_HVC U(0x12)
811#define EC_AARCH32_SMC U(0x13)
812#define EC_AARCH64_SVC U(0x15)
813#define EC_AARCH64_HVC U(0x16)
814#define EC_AARCH64_SMC U(0x17)
815#define EC_AARCH64_SYS U(0x18)
816#define EC_IABORT_LOWER_EL U(0x20)
817#define EC_IABORT_CUR_EL U(0x21)
818#define EC_PC_ALIGN U(0x22)
819#define EC_DABORT_LOWER_EL U(0x24)
820#define EC_DABORT_CUR_EL U(0x25)
821#define EC_SP_ALIGN U(0x26)
822#define EC_AARCH32_FP U(0x28)
823#define EC_AARCH64_FP U(0x2c)
824#define EC_SERROR U(0x2f)
Justin Chadwell83e04882019-08-20 11:01:52 +0100825#define EC_BRK U(0x3c)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100826
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +0000827/*
828 * External Abort bit in Instruction and Data Aborts synchronous exception
829 * syndromes.
830 */
831#define ESR_ISS_EABORT_EA_BIT U(9)
832
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700833#define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100834
Vignesh Radhakrishnanb4a72942017-03-03 10:58:05 -0800835/* Reset bit inside the Reset management register for EL3 (RMR_EL3) */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700836#define RMR_RESET_REQUEST_SHIFT U(0x1)
837#define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT)
Vignesh Radhakrishnanb4a72942017-03-03 10:58:05 -0800838
Dan Handleyed6ff952014-05-14 17:44:19 +0100839/*******************************************************************************
Antonio Nino Diazac998032017-02-27 17:23:54 +0000840 * Definitions of register offsets, fields and macros for CPU system
841 * instructions.
842 ******************************************************************************/
843
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700844#define TLBI_ADDR_SHIFT U(12)
Antonio Nino Diazac998032017-02-27 17:23:54 +0000845#define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF)
846#define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK)
847
848/*******************************************************************************
Dan Handleyed6ff952014-05-14 17:44:19 +0100849 * Definitions of register offsets and fields in the CNTCTLBase Frame of the
850 * system level implementation of the Generic Timer.
851 ******************************************************************************/
Soby Mathew2d9f7952018-06-11 16:21:30 +0100852#define CNTCTLBASE_CNTFRQ U(0x0)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700853#define CNTNSAR U(0x4)
854#define CNTNSAR_NS_SHIFT(x) (x)
Dan Handleyed6ff952014-05-14 17:44:19 +0100855
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700856#define CNTACR_BASE(x) (U(0x40) + ((x) << 2))
857#define CNTACR_RPCT_SHIFT U(0x0)
858#define CNTACR_RVCT_SHIFT U(0x1)
859#define CNTACR_RFRQ_SHIFT U(0x2)
860#define CNTACR_RVOFF_SHIFT U(0x3)
861#define CNTACR_RWVT_SHIFT U(0x4)
862#define CNTACR_RWPT_SHIFT U(0x5)
Dan Handleyed6ff952014-05-14 17:44:19 +0100863
Soby Mathew2d9f7952018-06-11 16:21:30 +0100864/*******************************************************************************
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000865 * Definitions of register offsets and fields in the CNTBaseN Frame of the
Soby Mathew2d9f7952018-06-11 16:21:30 +0100866 * system level implementation of the Generic Timer.
867 ******************************************************************************/
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000868/* Physical Count register. */
869#define CNTPCT_LO U(0x0)
870/* Counter Frequency register. */
871#define CNTBASEN_CNTFRQ U(0x10)
872/* Physical Timer CompareValue register. */
873#define CNTP_CVAL_LO U(0x20)
874/* Physical Timer Control register. */
875#define CNTP_CTL U(0x2c)
Soby Mathew2d9f7952018-06-11 16:21:30 +0100876
David Cunado5f55e282016-10-31 17:37:34 +0000877/* PMCR_EL0 definitions */
David Cunado4168f2f2017-10-02 17:41:39 +0100878#define PMCR_EL0_RESET_VAL U(0x0)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700879#define PMCR_EL0_N_SHIFT U(11)
880#define PMCR_EL0_N_MASK U(0x1f)
David Cunado5f55e282016-10-31 17:37:34 +0000881#define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT)
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100882#define PMCR_EL0_LP_BIT (U(1) << 7)
David Cunado4168f2f2017-10-02 17:41:39 +0100883#define PMCR_EL0_LC_BIT (U(1) << 6)
884#define PMCR_EL0_DP_BIT (U(1) << 5)
885#define PMCR_EL0_X_BIT (U(1) << 4)
886#define PMCR_EL0_D_BIT (U(1) << 3)
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100887#define PMCR_EL0_C_BIT (U(1) << 2)
888#define PMCR_EL0_P_BIT (U(1) << 1)
889#define PMCR_EL0_E_BIT (U(1) << 0)
David Cunado5f55e282016-10-31 17:37:34 +0000890
Isla Mitchell02c63072017-07-21 14:44:36 +0100891/*******************************************************************************
David Cunadoce88eee2017-10-20 11:30:57 +0100892 * Definitions for system register interface to SVE
893 ******************************************************************************/
894#define ZCR_EL3 S3_6_C1_C2_0
895#define ZCR_EL2 S3_4_C1_C2_0
896
897/* ZCR_EL3 definitions */
898#define ZCR_EL3_LEN_MASK U(0xf)
899
900/* ZCR_EL2 definitions */
901#define ZCR_EL2_LEN_MASK U(0xf)
902
903/*******************************************************************************
Isla Mitchell02c63072017-07-21 14:44:36 +0100904 * Definitions of MAIR encodings for device and normal memory
905 ******************************************************************************/
906/*
907 * MAIR encodings for device memory attributes.
908 */
909#define MAIR_DEV_nGnRnE ULL(0x0)
910#define MAIR_DEV_nGnRE ULL(0x4)
911#define MAIR_DEV_nGRE ULL(0x8)
912#define MAIR_DEV_GRE ULL(0xc)
913
914/*
915 * MAIR encodings for normal memory attributes.
916 *
917 * Cache Policy
918 * WT: Write Through
919 * WB: Write Back
920 * NC: Non-Cacheable
921 *
922 * Transient Hint
923 * NTR: Non-Transient
924 * TR: Transient
925 *
926 * Allocation Policy
927 * RA: Read Allocate
928 * WA: Write Allocate
929 * RWA: Read and Write Allocate
930 * NA: No Allocation
931 */
932#define MAIR_NORM_WT_TR_WA ULL(0x1)
933#define MAIR_NORM_WT_TR_RA ULL(0x2)
934#define MAIR_NORM_WT_TR_RWA ULL(0x3)
935#define MAIR_NORM_NC ULL(0x4)
936#define MAIR_NORM_WB_TR_WA ULL(0x5)
937#define MAIR_NORM_WB_TR_RA ULL(0x6)
938#define MAIR_NORM_WB_TR_RWA ULL(0x7)
939#define MAIR_NORM_WT_NTR_NA ULL(0x8)
940#define MAIR_NORM_WT_NTR_WA ULL(0x9)
941#define MAIR_NORM_WT_NTR_RA ULL(0xa)
942#define MAIR_NORM_WT_NTR_RWA ULL(0xb)
943#define MAIR_NORM_WB_NTR_NA ULL(0xc)
944#define MAIR_NORM_WB_NTR_WA ULL(0xd)
945#define MAIR_NORM_WB_NTR_RA ULL(0xe)
946#define MAIR_NORM_WB_NTR_RWA ULL(0xf)
947
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100948#define MAIR_NORM_OUTER_SHIFT U(4)
Isla Mitchell02c63072017-07-21 14:44:36 +0100949
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100950#define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \
951 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT))
Isla Mitchell02c63072017-07-21 14:44:36 +0100952
Jeenu Viswambharan1dc771b2017-10-19 09:15:15 +0100953/* PAR_EL1 fields */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100954#define PAR_F_SHIFT U(0)
955#define PAR_F_MASK ULL(0x1)
956#define PAR_ADDR_SHIFT U(12)
957#define PAR_ADDR_MASK (BIT(40) - ULL(1)) /* 40-bits-wide page address */
Jeenu Viswambharan1dc771b2017-10-19 09:15:15 +0100958
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +0100959/*******************************************************************************
960 * Definitions for system register interface to SPE
961 ******************************************************************************/
962#define PMBLIMITR_EL1 S3_0_C9_C10_0
963
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100964/*******************************************************************************
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +0100965 * Definitions for system register interface to MPAM
966 ******************************************************************************/
967#define MPAMIDR_EL1 S3_0_C10_C4_4
968#define MPAM2_EL2 S3_4_C10_C5_0
969#define MPAMHCR_EL2 S3_4_C10_C4_0
970#define MPAM3_EL3 S3_6_C10_C5_0
971
972/*******************************************************************************
johpow01fa59c6f2020-10-02 13:41:11 -0500973 * Definitions for system register interface to AMU for FEAT_AMUv1
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100974 ******************************************************************************/
975#define AMCR_EL0 S3_3_C13_C2_0
976#define AMCFGR_EL0 S3_3_C13_C2_1
977#define AMCGCR_EL0 S3_3_C13_C2_2
978#define AMUSERENR_EL0 S3_3_C13_C2_3
979#define AMCNTENCLR0_EL0 S3_3_C13_C2_4
980#define AMCNTENSET0_EL0 S3_3_C13_C2_5
981#define AMCNTENCLR1_EL0 S3_3_C13_C3_0
982#define AMCNTENSET1_EL0 S3_3_C13_C3_1
983
984/* Activity Monitor Group 0 Event Counter Registers */
985#define AMEVCNTR00_EL0 S3_3_C13_C4_0
986#define AMEVCNTR01_EL0 S3_3_C13_C4_1
987#define AMEVCNTR02_EL0 S3_3_C13_C4_2
988#define AMEVCNTR03_EL0 S3_3_C13_C4_3
989
990/* Activity Monitor Group 0 Event Type Registers */
991#define AMEVTYPER00_EL0 S3_3_C13_C6_0
992#define AMEVTYPER01_EL0 S3_3_C13_C6_1
993#define AMEVTYPER02_EL0 S3_3_C13_C6_2
994#define AMEVTYPER03_EL0 S3_3_C13_C6_3
995
Dimitris Papastamos525c37a2017-11-13 09:49:45 +0000996/* Activity Monitor Group 1 Event Counter Registers */
997#define AMEVCNTR10_EL0 S3_3_C13_C12_0
998#define AMEVCNTR11_EL0 S3_3_C13_C12_1
999#define AMEVCNTR12_EL0 S3_3_C13_C12_2
1000#define AMEVCNTR13_EL0 S3_3_C13_C12_3
1001#define AMEVCNTR14_EL0 S3_3_C13_C12_4
1002#define AMEVCNTR15_EL0 S3_3_C13_C12_5
1003#define AMEVCNTR16_EL0 S3_3_C13_C12_6
1004#define AMEVCNTR17_EL0 S3_3_C13_C12_7
1005#define AMEVCNTR18_EL0 S3_3_C13_C13_0
1006#define AMEVCNTR19_EL0 S3_3_C13_C13_1
1007#define AMEVCNTR1A_EL0 S3_3_C13_C13_2
1008#define AMEVCNTR1B_EL0 S3_3_C13_C13_3
1009#define AMEVCNTR1C_EL0 S3_3_C13_C13_4
1010#define AMEVCNTR1D_EL0 S3_3_C13_C13_5
1011#define AMEVCNTR1E_EL0 S3_3_C13_C13_6
1012#define AMEVCNTR1F_EL0 S3_3_C13_C13_7
1013
1014/* Activity Monitor Group 1 Event Type Registers */
1015#define AMEVTYPER10_EL0 S3_3_C13_C14_0
1016#define AMEVTYPER11_EL0 S3_3_C13_C14_1
1017#define AMEVTYPER12_EL0 S3_3_C13_C14_2
1018#define AMEVTYPER13_EL0 S3_3_C13_C14_3
1019#define AMEVTYPER14_EL0 S3_3_C13_C14_4
1020#define AMEVTYPER15_EL0 S3_3_C13_C14_5
1021#define AMEVTYPER16_EL0 S3_3_C13_C14_6
1022#define AMEVTYPER17_EL0 S3_3_C13_C14_7
1023#define AMEVTYPER18_EL0 S3_3_C13_C15_0
1024#define AMEVTYPER19_EL0 S3_3_C13_C15_1
1025#define AMEVTYPER1A_EL0 S3_3_C13_C15_2
1026#define AMEVTYPER1B_EL0 S3_3_C13_C15_3
1027#define AMEVTYPER1C_EL0 S3_3_C13_C15_4
1028#define AMEVTYPER1D_EL0 S3_3_C13_C15_5
1029#define AMEVTYPER1E_EL0 S3_3_C13_C15_6
1030#define AMEVTYPER1F_EL0 S3_3_C13_C15_7
1031
Alexei Fedorov7e6306b2020-07-14 08:17:56 +01001032/* AMCFGR_EL0 definitions */
1033#define AMCFGR_EL0_NCG_SHIFT U(28)
1034#define AMCFGR_EL0_NCG_MASK U(0xf)
1035#define AMCFGR_EL0_N_SHIFT U(0)
1036#define AMCFGR_EL0_N_MASK U(0xff)
1037
Dimitris Papastamos525c37a2017-11-13 09:49:45 +00001038/* AMCGCR_EL0 definitions */
1039#define AMCGCR_EL0_CG1NC_SHIFT U(8)
Dimitris Papastamos525c37a2017-11-13 09:49:45 +00001040#define AMCGCR_EL0_CG1NC_MASK U(0xff)
1041
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +01001042/* MPAM register definitions */
1043#define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63)
Louis Mayencourtbdfa1032019-02-11 11:25:50 +00001044#define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31)
1045
1046#define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49)
1047#define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48)
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +01001048
1049#define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17)
1050
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +01001051/*******************************************************************************
johpow01fa59c6f2020-10-02 13:41:11 -05001052 * Definitions for system register interface to AMU for FEAT_AMUv1p1
1053 ******************************************************************************/
1054
1055/* Definition for register defining which virtual offsets are implemented. */
1056#define AMCG1IDR_EL0 S3_3_C13_C2_6
1057#define AMCG1IDR_CTR_MASK ULL(0xffff)
1058#define AMCG1IDR_CTR_SHIFT U(0)
1059#define AMCG1IDR_VOFF_MASK ULL(0xffff)
1060#define AMCG1IDR_VOFF_SHIFT U(16)
1061
1062/* New bit added to AMCR_EL0 */
1063#define AMCR_CG1RZ_BIT (ULL(0x1) << 17)
1064
1065/*
1066 * Definitions for virtual offset registers for architected activity monitor
1067 * event counters.
1068 * AMEVCNTVOFF01_EL2 intentionally left undefined, as it does not exist.
1069 */
1070#define AMEVCNTVOFF00_EL2 S3_4_C13_C8_0
1071#define AMEVCNTVOFF02_EL2 S3_4_C13_C8_2
1072#define AMEVCNTVOFF03_EL2 S3_4_C13_C8_3
1073
1074/*
1075 * Definitions for virtual offset registers for auxiliary activity monitor event
1076 * counters.
1077 */
1078#define AMEVCNTVOFF10_EL2 S3_4_C13_C10_0
1079#define AMEVCNTVOFF11_EL2 S3_4_C13_C10_1
1080#define AMEVCNTVOFF12_EL2 S3_4_C13_C10_2
1081#define AMEVCNTVOFF13_EL2 S3_4_C13_C10_3
1082#define AMEVCNTVOFF14_EL2 S3_4_C13_C10_4
1083#define AMEVCNTVOFF15_EL2 S3_4_C13_C10_5
1084#define AMEVCNTVOFF16_EL2 S3_4_C13_C10_6
1085#define AMEVCNTVOFF17_EL2 S3_4_C13_C10_7
1086#define AMEVCNTVOFF18_EL2 S3_4_C13_C11_0
1087#define AMEVCNTVOFF19_EL2 S3_4_C13_C11_1
1088#define AMEVCNTVOFF1A_EL2 S3_4_C13_C11_2
1089#define AMEVCNTVOFF1B_EL2 S3_4_C13_C11_3
1090#define AMEVCNTVOFF1C_EL2 S3_4_C13_C11_4
1091#define AMEVCNTVOFF1D_EL2 S3_4_C13_C11_5
1092#define AMEVCNTVOFF1E_EL2 S3_4_C13_C11_6
1093#define AMEVCNTVOFF1F_EL2 S3_4_C13_C11_7
1094
1095/*******************************************************************************
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +01001096 * RAS system registers
Sathees Balya0911df12018-12-06 13:33:24 +00001097 ******************************************************************************/
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +01001098#define DISR_EL1 S3_0_C12_C1_1
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +01001099#define DISR_A_BIT U(31)
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +01001100
Jeenu Viswambharan19f6cf22017-12-07 08:43:05 +00001101#define ERRIDR_EL1 S3_0_C5_C3_0
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +01001102#define ERRIDR_MASK U(0xffff)
Jeenu Viswambharan19f6cf22017-12-07 08:43:05 +00001103
1104#define ERRSELR_EL1 S3_0_C5_C3_1
1105
1106/* System register access to Standard Error Record registers */
1107#define ERXFR_EL1 S3_0_C5_C4_0
1108#define ERXCTLR_EL1 S3_0_C5_C4_1
1109#define ERXSTATUS_EL1 S3_0_C5_C4_2
1110#define ERXADDR_EL1 S3_0_C5_C4_3
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +00001111#define ERXPFGF_EL1 S3_0_C5_C4_4
1112#define ERXPFGCTL_EL1 S3_0_C5_C4_5
1113#define ERXPFGCDN_EL1 S3_0_C5_C4_6
Jan Dabros82ef8bf2018-08-30 13:52:23 +02001114#define ERXMISC0_EL1 S3_0_C5_C5_0
1115#define ERXMISC1_EL1 S3_0_C5_C5_1
Jeenu Viswambharan19f6cf22017-12-07 08:43:05 +00001116
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +00001117#define ERXCTLR_ED_BIT (U(1) << 0)
1118#define ERXCTLR_UE_BIT (U(1) << 4)
1119
1120#define ERXPFGCTL_UC_BIT (U(1) << 1)
1121#define ERXPFGCTL_UEU_BIT (U(1) << 2)
1122#define ERXPFGCTL_CDEN_BIT (U(1) << 31)
1123
1124/*******************************************************************************
1125 * Armv8.3 Pointer Authentication Registers
Sathees Balya0911df12018-12-06 13:33:24 +00001126 ******************************************************************************/
Antonio Nino Diaz594811b2019-01-31 11:58:00 +00001127#define APIAKeyLo_EL1 S3_0_C2_C1_0
1128#define APIAKeyHi_EL1 S3_0_C2_C1_1
1129#define APIBKeyLo_EL1 S3_0_C2_C1_2
1130#define APIBKeyHi_EL1 S3_0_C2_C1_3
1131#define APDAKeyLo_EL1 S3_0_C2_C2_0
1132#define APDAKeyHi_EL1 S3_0_C2_C2_1
1133#define APDBKeyLo_EL1 S3_0_C2_C2_2
1134#define APDBKeyHi_EL1 S3_0_C2_C2_3
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +00001135#define APGAKeyLo_EL1 S3_0_C2_C3_0
Antonio Nino Diaz594811b2019-01-31 11:58:00 +00001136#define APGAKeyHi_EL1 S3_0_C2_C3_1
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +00001137
Sathees Balya0911df12018-12-06 13:33:24 +00001138/*******************************************************************************
1139 * Armv8.4 Data Independent Timing Registers
1140 ******************************************************************************/
1141#define DIT S3_3_C4_C2_5
1142#define DIT_BIT BIT(24)
1143
John Tsichritzis1f9ff492019-03-04 16:41:26 +00001144/*******************************************************************************
1145 * Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field
1146 ******************************************************************************/
1147#define SSBS S3_3_C4_C2_6
1148
Justin Chadwell1c7c13a2019-07-18 14:25:33 +01001149/*******************************************************************************
1150 * Armv8.5 - Memory Tagging Extension Registers
1151 ******************************************************************************/
1152#define TFSRE0_EL1 S3_0_C5_C6_1
1153#define TFSR_EL1 S3_0_C5_C6_0
1154#define RGSR_EL1 S3_0_C1_C0_5
1155#define GCR_EL1 S3_0_C1_C0_6
1156
Madhukar Pappireddy90d65322019-10-30 14:24:39 -05001157/*******************************************************************************
johpow01f91e59f2021-08-04 19:38:18 -05001158 * FEAT_HCX - Extended Hypervisor Configuration Register
1159 ******************************************************************************/
1160#define HCRX_EL2 S3_4_C1_C2_2
1161#define HCRX_EL2_FGTnXS_BIT (UL(1) << 4)
1162#define HCRX_EL2_FnXS_BIT (UL(1) << 3)
1163#define HCRX_EL2_EnASR_BIT (UL(1) << 2)
1164#define HCRX_EL2_EnALS_BIT (UL(1) << 1)
1165#define HCRX_EL2_EnAS0_BIT (UL(1) << 0)
1166
1167/*******************************************************************************
Madhukar Pappireddy90d65322019-10-30 14:24:39 -05001168 * Definitions for DynamicIQ Shared Unit registers
1169 ******************************************************************************/
1170#define CLUSTERPWRDN_EL1 S3_0_c15_c3_6
1171
1172/* CLUSTERPWRDN_EL1 register definitions */
1173#define DSU_CLUSTER_PWR_OFF 0
1174#define DSU_CLUSTER_PWR_ON 1
1175#define DSU_CLUSTER_PWR_MASK U(1)
1176
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +01001177#endif /* ARCH_H */