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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Antonio Nino Diazc326c342019-01-11 11:20:10 +00002 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +01007#ifndef ARCH_H
8#define ARCH_H
Achin Gupta4f6ad662013-10-25 09:08:21 +01009
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <lib/utils_def.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010011
12/*******************************************************************************
13 * MIDR bit definitions
14 ******************************************************************************/
Varun Wadekarc6a11f62017-05-25 18:04:48 -070015#define MIDR_IMPL_MASK U(0xff)
16#define MIDR_IMPL_SHIFT U(0x18)
17#define MIDR_VAR_SHIFT U(20)
18#define MIDR_VAR_BITS U(4)
19#define MIDR_VAR_MASK U(0xf)
20#define MIDR_REV_SHIFT U(0)
21#define MIDR_REV_BITS U(4)
22#define MIDR_REV_MASK U(0xf)
23#define MIDR_PN_MASK U(0xfff)
24#define MIDR_PN_SHIFT U(0x4)
Achin Gupta4f6ad662013-10-25 09:08:21 +010025
26/*******************************************************************************
27 * MPIDR macros
28 ******************************************************************************/
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010029#define MPIDR_MT_MASK (ULL(1) << 24)
Achin Gupta4f6ad662013-10-25 09:08:21 +010030#define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK
Varun Wadekarc6a11f62017-05-25 18:04:48 -070031#define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS)
32#define MPIDR_AFFINITY_BITS U(8)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010033#define MPIDR_AFFLVL_MASK ULL(0xff)
Varun Wadekarc6a11f62017-05-25 18:04:48 -070034#define MPIDR_AFF0_SHIFT U(0)
35#define MPIDR_AFF1_SHIFT U(8)
36#define MPIDR_AFF2_SHIFT U(16)
37#define MPIDR_AFF3_SHIFT U(32)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000038#define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010039#define MPIDR_AFFINITY_MASK ULL(0xff00ffffff)
Varun Wadekarc6a11f62017-05-25 18:04:48 -070040#define MPIDR_AFFLVL_SHIFT U(3)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000041#define MPIDR_AFFLVL0 ULL(0x0)
42#define MPIDR_AFFLVL1 ULL(0x1)
43#define MPIDR_AFFLVL2 ULL(0x2)
44#define MPIDR_AFFLVL3 ULL(0x3)
45#define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000046#define MPIDR_AFFLVL0_VAL(mpidr) \
Antonio Nino Diaz34235a32018-07-11 16:45:49 +010047 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK)
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000048#define MPIDR_AFFLVL1_VAL(mpidr) \
Antonio Nino Diaz34235a32018-07-11 16:45:49 +010049 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK)
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000050#define MPIDR_AFFLVL2_VAL(mpidr) \
Antonio Nino Diaz34235a32018-07-11 16:45:49 +010051 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK)
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000052#define MPIDR_AFFLVL3_VAL(mpidr) \
Antonio Nino Diaz34235a32018-07-11 16:45:49 +010053 (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK)
Soby Mathewe2b2d8f2014-12-04 14:14:12 +000054/*
55 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to
56 * add one while using this macro to define array sizes.
57 * TODO: Support only the first 3 affinity levels for now.
58 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070059#define MPIDR_MAX_AFFLVL U(2)
Achin Gupta4f6ad662013-10-25 09:08:21 +010060
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000061#define MPID_MASK (MPIDR_MT_MASK | \
62 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \
63 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \
64 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \
65 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT))
66
67#define MPIDR_AFF_ID(mpid, n) \
68 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK)
69
70/*
71 * An invalid MPID. This value can be used by functions that return an MPID to
72 * indicate an error.
73 */
74#define INVALID_MPID U(0xFFFFFFFF)
Achin Gupta4f6ad662013-10-25 09:08:21 +010075
76/*******************************************************************************
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010077 * Definitions for CPU system register interface to GICv3
78 ******************************************************************************/
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000079#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7
80#define ICC_SGI1R S3_0_C12_C11_5
81#define ICC_SRE_EL1 S3_0_C12_C12_5
82#define ICC_SRE_EL2 S3_4_C12_C9_5
83#define ICC_SRE_EL3 S3_6_C12_C12_5
84#define ICC_CTLR_EL1 S3_0_C12_C12_4
85#define ICC_CTLR_EL3 S3_6_C12_C12_4
86#define ICC_PMR_EL1 S3_0_C4_C6_0
87#define ICC_RPR_EL1 S3_0_C12_C11_3
88#define ICC_IGRPEN1_EL3 S3_6_c12_c12_7
89#define ICC_IGRPEN0_EL1 S3_0_c12_c12_6
90#define ICC_HPPIR0_EL1 S3_0_c12_c8_2
91#define ICC_HPPIR1_EL1 S3_0_c12_c12_2
92#define ICC_IAR0_EL1 S3_0_c12_c8_0
93#define ICC_IAR1_EL1 S3_0_c12_c12_0
94#define ICC_EOIR0_EL1 S3_0_c12_c8_1
95#define ICC_EOIR1_EL1 S3_0_c12_c12_1
96#define ICC_SGI0R_EL1 S3_0_c12_c11_7
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010097
98/*******************************************************************************
Achin Guptac2b43af2013-10-31 11:27:43 +000099 * Generic timer memory mapped registers & offsets
100 ******************************************************************************/
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700101#define CNTCR_OFF U(0x000)
Yann Gautier007d7452019-04-17 13:47:07 +0200102#define CNTCV_OFF U(0x008)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700103#define CNTFID_OFF U(0x020)
Achin Guptac2b43af2013-10-31 11:27:43 +0000104
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700105#define CNTCR_EN (U(1) << 0)
106#define CNTCR_HDBG (U(1) << 1)
Sandrine Bailleux3fa98472014-03-31 11:25:18 +0100107#define CNTCR_FCREQ(x) ((x) << 8)
Achin Guptac2b43af2013-10-31 11:27:43 +0000108
109/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +0100110 * System register bit definitions
111 ******************************************************************************/
112/* CLIDR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700113#define LOUIS_SHIFT U(21)
114#define LOC_SHIFT U(24)
Alexei Fedorova95a5892019-07-29 17:22:53 +0100115#define CTYPE_SHIFT(n) U(3 * (n - 1))
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700116#define CLIDR_FIELD_WIDTH U(3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100117
118/* CSSELR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700119#define LEVEL_SHIFT U(1)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100120
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100121/* Data cache set/way op type defines */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700122#define DCISW U(0x0)
123#define DCCISW U(0x1)
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +0000124#if ERRATA_A53_827319
125#define DCCSW DCCISW
126#else
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700127#define DCCSW U(0x2)
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +0000128#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100129
130/* ID_AA64PFR0_EL1 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700131#define ID_AA64PFR0_EL0_SHIFT U(0)
132#define ID_AA64PFR0_EL1_SHIFT U(4)
133#define ID_AA64PFR0_EL2_SHIFT U(8)
134#define ID_AA64PFR0_EL3_SHIFT U(12)
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100135#define ID_AA64PFR0_AMU_SHIFT U(44)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100136#define ID_AA64PFR0_AMU_MASK ULL(0xf)
137#define ID_AA64PFR0_ELX_MASK ULL(0xf)
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100138#define ID_AA64PFR0_GIC_SHIFT U(24)
139#define ID_AA64PFR0_GIC_WIDTH U(4)
140#define ID_AA64PFR0_GIC_MASK ULL(0xf)
David Cunadoce88eee2017-10-20 11:30:57 +0100141#define ID_AA64PFR0_SVE_SHIFT U(32)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100142#define ID_AA64PFR0_SVE_MASK ULL(0xf)
Achin Gupta023c1552019-10-11 14:44:05 +0100143#define ID_AA64PFR0_SEL2_SHIFT U(36)
Artsem Artsemenkaa5334472019-11-26 16:40:31 +0000144#define ID_AA64PFR0_SEL2_MASK ULL(0xf)
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +0100145#define ID_AA64PFR0_MPAM_SHIFT U(40)
146#define ID_AA64PFR0_MPAM_MASK ULL(0xf)
Sathees Balya0911df12018-12-06 13:33:24 +0000147#define ID_AA64PFR0_DIT_SHIFT U(48)
148#define ID_AA64PFR0_DIT_MASK ULL(0xf)
149#define ID_AA64PFR0_DIT_LENGTH U(4)
150#define ID_AA64PFR0_DIT_SUPPORTED U(1)
Dimitris Papastamos43e05ec2018-01-02 15:53:01 +0000151#define ID_AA64PFR0_CSV2_SHIFT U(56)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100152#define ID_AA64PFR0_CSV2_MASK ULL(0xf)
Dimitris Papastamos43e05ec2018-01-02 15:53:01 +0000153#define ID_AA64PFR0_CSV2_LENGTH U(4)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100154
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100155/* Exception level handling */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100156#define EL_IMPL_NONE ULL(0)
157#define EL_IMPL_A64ONLY ULL(1)
158#define EL_IMPL_A64_A32 ULL(2)
Jeenu Viswambharan2a9b8822017-02-21 14:40:44 +0000159
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100160/* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */
161#define ID_AA64DFR0_PMS_SHIFT U(32)
162#define ID_AA64DFR0_PMS_MASK ULL(0xf)
Achin Gupta92712a52015-09-03 14:18:02 +0100163
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000164/* ID_AA64ISAR1_EL1 definitions */
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000165#define ID_AA64ISAR1_EL1 S3_0_C0_C6_1
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000166#define ID_AA64ISAR1_GPI_SHIFT U(28)
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000167#define ID_AA64ISAR1_GPI_MASK ULL(0xf)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000168#define ID_AA64ISAR1_GPA_SHIFT U(24)
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000169#define ID_AA64ISAR1_GPA_MASK ULL(0xf)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000170#define ID_AA64ISAR1_API_SHIFT U(8)
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000171#define ID_AA64ISAR1_API_MASK ULL(0xf)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000172#define ID_AA64ISAR1_APA_SHIFT U(4)
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000173#define ID_AA64ISAR1_APA_MASK ULL(0xf)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000174
Antonio Nino Diazc326c342019-01-11 11:20:10 +0000175/* ID_AA64MMFR0_EL1 definitions */
176#define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0)
177#define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf)
178
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700179#define PARANGE_0000 U(32)
180#define PARANGE_0001 U(36)
181#define PARANGE_0010 U(40)
182#define PARANGE_0011 U(42)
183#define PARANGE_0100 U(44)
184#define PARANGE_0101 U(48)
Antonio Nino Diazb9ef6642017-11-17 09:52:53 +0000185#define PARANGE_0110 U(52)
Antonio Nino Diazd1beee22016-12-13 15:28:54 +0000186
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100187#define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100188#define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf)
189#define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0)
190#define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100191
192#define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100193#define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf)
194#define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED ULL(0x0)
195#define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED ULL(0xf)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100196
197#define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100198#define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf)
199#define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1)
200#define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100201
Antonio Nino Diazc326c342019-01-11 11:20:10 +0000202/* ID_AA64MMFR2_EL1 definitions */
203#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2
Sathees Balya74155972019-01-25 11:36:01 +0000204
205#define ID_AA64MMFR2_EL1_ST_SHIFT U(28)
206#define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf)
207
Antonio Nino Diazc326c342019-01-11 11:20:10 +0000208#define ID_AA64MMFR2_EL1_CNP_SHIFT U(0)
209#define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf)
210
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000211/* ID_AA64PFR1_EL1 definitions */
212#define ID_AA64PFR1_EL1_SSBS_SHIFT U(4)
213#define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf)
214
215#define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */
216
Alexei Fedorov90f2e882019-05-24 12:17:09 +0100217#define ID_AA64PFR1_EL1_BT_SHIFT U(0)
218#define ID_AA64PFR1_EL1_BT_MASK ULL(0xf)
219
220#define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */
221
Soby Mathew830f0ad2019-07-12 09:23:38 +0100222#define ID_AA64PFR1_EL1_MTE_SHIFT U(8)
223#define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf)
224
225#define MTE_UNIMPLEMENTED ULL(0)
226#define MTE_IMPLEMENTED_EL0 ULL(1) /* MTE is only implemented at EL0 */
227#define MTE_IMPLEMENTED_ELX ULL(2) /* MTE is implemented at all ELs */
228
Achin Gupta4f6ad662013-10-25 09:08:21 +0100229/* ID_PFR1_EL1 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700230#define ID_PFR1_VIRTEXT_SHIFT U(12)
231#define ID_PFR1_VIRTEXT_MASK U(0xf)
Antonio Nino Diaz34235a32018-07-11 16:45:49 +0100232#define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \
Achin Gupta4f6ad662013-10-25 09:08:21 +0100233 & ID_PFR1_VIRTEXT_MASK)
234
235/* SCTLR definitions */
David Cunadofee86532017-04-13 22:38:29 +0100236#define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700237 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
238 (U(1) << 11) | (U(1) << 5) | (U(1) << 4))
Achin Gupta4f6ad662013-10-25 09:08:21 +0100239
David Cunadofee86532017-04-13 22:38:29 +0100240#define SCTLR_EL1_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700241 (U(1) << 22) | (U(1) << 20) | (U(1) << 11))
Jens Wiklanderc93c9df2014-09-04 10:23:27 +0200242#define SCTLR_AARCH32_EL1_RES1 \
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700243 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \
244 (U(1) << 4) | (U(1) << 3))
Jens Wiklanderc93c9df2014-09-04 10:23:27 +0200245
David Cunadofee86532017-04-13 22:38:29 +0100246#define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
247 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
248 (U(1) << 11) | (U(1) << 5) | (U(1) << 4))
249
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000250#define SCTLR_M_BIT (ULL(1) << 0)
251#define SCTLR_A_BIT (ULL(1) << 1)
252#define SCTLR_C_BIT (ULL(1) << 2)
253#define SCTLR_SA_BIT (ULL(1) << 3)
254#define SCTLR_SA0_BIT (ULL(1) << 4)
255#define SCTLR_CP15BEN_BIT (ULL(1) << 5)
256#define SCTLR_ITD_BIT (ULL(1) << 7)
257#define SCTLR_SED_BIT (ULL(1) << 8)
258#define SCTLR_UMA_BIT (ULL(1) << 9)
259#define SCTLR_I_BIT (ULL(1) << 12)
Alexei Fedorovc31ab382019-07-10 10:49:12 +0100260#define SCTLR_EnDB_BIT (ULL(1) << 13)
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000261#define SCTLR_DZE_BIT (ULL(1) << 14)
262#define SCTLR_UCT_BIT (ULL(1) << 15)
263#define SCTLR_NTWI_BIT (ULL(1) << 16)
264#define SCTLR_NTWE_BIT (ULL(1) << 18)
265#define SCTLR_WXN_BIT (ULL(1) << 19)
266#define SCTLR_UWXN_BIT (ULL(1) << 20)
Louis Mayencourt78a0aed2019-02-20 12:11:41 +0000267#define SCTLR_IESB_BIT (ULL(1) << 21)
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000268#define SCTLR_E0E_BIT (ULL(1) << 24)
269#define SCTLR_EE_BIT (ULL(1) << 25)
270#define SCTLR_UCI_BIT (ULL(1) << 26)
Alexei Fedorovc31ab382019-07-10 10:49:12 +0100271#define SCTLR_EnDA_BIT (ULL(1) << 27)
272#define SCTLR_EnIB_BIT (ULL(1) << 30)
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000273#define SCTLR_EnIA_BIT (ULL(1) << 31)
Alexei Fedorov90f2e882019-05-24 12:17:09 +0100274#define SCTLR_BT0_BIT (ULL(1) << 35)
275#define SCTLR_BT1_BIT (ULL(1) << 36)
276#define SCTLR_BT_BIT (ULL(1) << 36)
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000277#define SCTLR_DSSBS_BIT (ULL(1) << 44)
David Cunadofee86532017-04-13 22:38:29 +0100278#define SCTLR_RESET_VAL SCTLR_EL3_RES1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100279
Achin Gupta4f6ad662013-10-25 09:08:21 +0100280/* CPACR_El1 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700281#define CPACR_EL1_FPEN(x) ((x) << 20)
282#define CPACR_EL1_FP_TRAP_EL0 U(0x1)
283#define CPACR_EL1_FP_TRAP_ALL U(0x2)
284#define CPACR_EL1_FP_TRAP_NONE U(0x3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100285
286/* SCR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700287#define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5))
Soby Mathew830f0ad2019-07-12 09:23:38 +0100288#define SCR_ATA_BIT (U(1) << 26)
Jeenu Viswambharanf00da742017-12-08 12:13:51 +0000289#define SCR_FIEN_BIT (U(1) << 21)
Achin Gupta023c1552019-10-11 14:44:05 +0100290#define SCR_EEL2_BIT (U(1) << 18)
Jeenu Viswambharancbad6612018-08-15 14:29:29 +0100291#define SCR_API_BIT (U(1) << 17)
292#define SCR_APK_BIT (U(1) << 16)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700293#define SCR_TWE_BIT (U(1) << 13)
294#define SCR_TWI_BIT (U(1) << 12)
295#define SCR_ST_BIT (U(1) << 11)
296#define SCR_RW_BIT (U(1) << 10)
297#define SCR_SIF_BIT (U(1) << 9)
298#define SCR_HCE_BIT (U(1) << 8)
299#define SCR_SMD_BIT (U(1) << 7)
300#define SCR_EA_BIT (U(1) << 3)
301#define SCR_FIQ_BIT (U(1) << 2)
302#define SCR_IRQ_BIT (U(1) << 1)
303#define SCR_NS_BIT (U(1) << 0)
304#define SCR_VALID_BIT_MASK U(0x2f8f)
David Cunadofee86532017-04-13 22:38:29 +0100305#define SCR_RESET_VAL SCR_RES1_BITS
Achin Gupta4f6ad662013-10-25 09:08:21 +0100306
David Cunadofee86532017-04-13 22:38:29 +0100307/* MDCR_EL3 definitions */
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100308#define MDCR_SCCD_BIT (ULL(1) << 23)
309#define MDCR_SPME_BIT (ULL(1) << 17)
310#define MDCR_SDD_BIT (ULL(1) << 16)
dp-arm595d0d52017-02-08 11:51:50 +0000311#define MDCR_SPD32(x) ((x) << 14)
Antonio Nino Diaz3fbd3f52019-02-18 16:55:43 +0000312#define MDCR_SPD32_LEGACY ULL(0x0)
313#define MDCR_SPD32_DISABLE ULL(0x2)
314#define MDCR_SPD32_ENABLE ULL(0x3)
dp-armee3457b2017-05-23 09:32:49 +0100315#define MDCR_NSPB(x) ((x) << 12)
Antonio Nino Diaz3fbd3f52019-02-18 16:55:43 +0000316#define MDCR_NSPB_EL1 ULL(0x3)
317#define MDCR_TDOSA_BIT (ULL(1) << 10)
318#define MDCR_TDA_BIT (ULL(1) << 9)
319#define MDCR_TPM_BIT (ULL(1) << 6)
Antonio Nino Diaz3fbd3f52019-02-18 16:55:43 +0000320#define MDCR_EL3_RESET_VAL ULL(0x0)
dp-arm595d0d52017-02-08 11:51:50 +0000321
David Cunadofee86532017-04-13 22:38:29 +0100322/* MDCR_EL2 definitions */
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100323#define MDCR_EL2_HLP (U(1) << 26)
324#define MDCR_EL2_HCCD (U(1) << 23)
325#define MDCR_EL2_TTRF (U(1) << 19)
326#define MDCR_EL2_HPMD (U(1) << 17)
dp-armee3457b2017-05-23 09:32:49 +0100327#define MDCR_EL2_TPMS (U(1) << 14)
328#define MDCR_EL2_E2PB(x) ((x) << 12)
329#define MDCR_EL2_E2PB_EL1 U(0x3)
David Cunadofee86532017-04-13 22:38:29 +0100330#define MDCR_EL2_TDRA_BIT (U(1) << 11)
331#define MDCR_EL2_TDOSA_BIT (U(1) << 10)
332#define MDCR_EL2_TDA_BIT (U(1) << 9)
333#define MDCR_EL2_TDE_BIT (U(1) << 8)
334#define MDCR_EL2_HPME_BIT (U(1) << 7)
335#define MDCR_EL2_TPM_BIT (U(1) << 6)
336#define MDCR_EL2_TPMCR_BIT (U(1) << 5)
337#define MDCR_EL2_RESET_VAL U(0x0)
338
339/* HSTR_EL2 definitions */
340#define HSTR_EL2_RESET_VAL U(0x0)
341#define HSTR_EL2_T_MASK U(0xff)
342
343/* CNTHP_CTL_EL2 definitions */
344#define CNTHP_CTL_ENABLE_BIT (U(1) << 0)
345#define CNTHP_CTL_RESET_VAL U(0x0)
346
347/* VTTBR_EL2 definitions */
348#define VTTBR_RESET_VAL ULL(0x0)
349#define VTTBR_VMID_MASK ULL(0xff)
350#define VTTBR_VMID_SHIFT U(48)
351#define VTTBR_BADDR_MASK ULL(0xffffffffffff)
352#define VTTBR_BADDR_SHIFT U(0)
dp-arm595d0d52017-02-08 11:51:50 +0000353
Achin Gupta4f6ad662013-10-25 09:08:21 +0100354/* HCR definitions */
Jeenu Viswambharancbad6612018-08-15 14:29:29 +0100355#define HCR_API_BIT (ULL(1) << 41)
356#define HCR_APK_BIT (ULL(1) << 40)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000357#define HCR_TGE_BIT (ULL(1) << 27)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700358#define HCR_RW_SHIFT U(31)
359#define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100360#define HCR_AMO_BIT (ULL(1) << 5)
361#define HCR_IMO_BIT (ULL(1) << 4)
362#define HCR_FMO_BIT (ULL(1) << 3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100363
Gerald Lejeune851dc7e2016-03-22 11:11:46 +0100364/* ISR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700365#define ISR_A_SHIFT U(8)
366#define ISR_I_SHIFT U(7)
367#define ISR_F_SHIFT U(6)
Gerald Lejeune851dc7e2016-03-22 11:11:46 +0100368
Achin Gupta4f6ad662013-10-25 09:08:21 +0100369/* CNTHCTL_EL2 definitions */
David Cunadofee86532017-04-13 22:38:29 +0100370#define CNTHCTL_RESET_VAL U(0x0)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700371#define EVNTEN_BIT (U(1) << 2)
372#define EL1PCEN_BIT (U(1) << 1)
373#define EL1PCTEN_BIT (U(1) << 0)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100374
375/* CNTKCTL_EL1 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700376#define EL0PTEN_BIT (U(1) << 9)
377#define EL0VTEN_BIT (U(1) << 8)
378#define EL0PCTEN_BIT (U(1) << 0)
379#define EL0VCTEN_BIT (U(1) << 1)
380#define EVNTEN_BIT (U(1) << 2)
381#define EVNTDIR_BIT (U(1) << 3)
382#define EVNTI_SHIFT U(4)
383#define EVNTI_MASK U(0xf)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100384
385/* CPTR_EL3 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700386#define TCPAC_BIT (U(1) << 31)
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100387#define TAM_BIT (U(1) << 30)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700388#define TTA_BIT (U(1) << 20)
389#define TFP_BIT (U(1) << 10)
David Cunadoce88eee2017-10-20 11:30:57 +0100390#define CPTR_EZ_BIT (U(1) << 8)
David Cunadofee86532017-04-13 22:38:29 +0100391#define CPTR_EL3_RESET_VAL U(0x0)
392
393/* CPTR_EL2 definitions */
394#define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff)))
395#define CPTR_EL2_TCPAC_BIT (U(1) << 31)
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100396#define CPTR_EL2_TAM_BIT (U(1) << 30)
David Cunadofee86532017-04-13 22:38:29 +0100397#define CPTR_EL2_TTA_BIT (U(1) << 20)
398#define CPTR_EL2_TFP_BIT (U(1) << 10)
David Cunadoce88eee2017-10-20 11:30:57 +0100399#define CPTR_EL2_TZ_BIT (U(1) << 8)
David Cunadofee86532017-04-13 22:38:29 +0100400#define CPTR_EL2_RESET_VAL CPTR_EL2_RES1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100401
402/* CPSR/SPSR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700403#define DAIF_FIQ_BIT (U(1) << 0)
404#define DAIF_IRQ_BIT (U(1) << 1)
405#define DAIF_ABT_BIT (U(1) << 2)
406#define DAIF_DBG_BIT (U(1) << 3)
407#define SPSR_DAIF_SHIFT U(6)
408#define SPSR_DAIF_MASK U(0xf)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100409
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700410#define SPSR_AIF_SHIFT U(6)
411#define SPSR_AIF_MASK U(0x7)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100412
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700413#define SPSR_E_SHIFT U(9)
414#define SPSR_E_MASK U(0x1)
415#define SPSR_E_LITTLE U(0x0)
416#define SPSR_E_BIG U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100417
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700418#define SPSR_T_SHIFT U(5)
419#define SPSR_T_MASK U(0x1)
420#define SPSR_T_ARM U(0x0)
421#define SPSR_T_THUMB U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100422
Dimitris Papastamosc52ebdc2017-12-18 13:46:21 +0000423#define SPSR_M_SHIFT U(4)
424#define SPSR_M_MASK U(0x1)
425#define SPSR_M_AARCH64 U(0x0)
426#define SPSR_M_AARCH32 U(0x1)
427
John Tsichritzis55534172019-07-23 11:12:41 +0100428#define SPSR_SSBS_BIT_AARCH64 BIT_64(12)
429#define SPSR_SSBS_BIT_AARCH32 BIT_64(23)
430
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100431#define DISABLE_ALL_EXCEPTIONS \
432 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT)
433
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000434#define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT)
435
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000436/*
437 * RMR_EL3 definitions
438 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700439#define RMR_EL3_RR_BIT (U(1) << 1)
440#define RMR_EL3_AA64_BIT (U(1) << 0)
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000441
442/*
443 * HI-VECTOR address for AArch32 state
444 */
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000445#define HI_VECTOR_BASE U(0xFFFF0000)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100446
447/*
448 * TCR defintions
449 */
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000450#define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23))
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100451#define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23))
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700452#define TCR_EL1_IPS_SHIFT U(32)
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100453#define TCR_EL2_PS_SHIFT U(16)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700454#define TCR_EL3_PS_SHIFT U(16)
Lin Ma741a3822014-06-27 16:56:30 -0700455
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100456#define TCR_TxSZ_MIN ULL(16)
457#define TCR_TxSZ_MAX ULL(39)
Sathees Balya74155972019-01-25 11:36:01 +0000458#define TCR_TxSZ_MAX_TTST ULL(48)
Antonio Nino Diazd48ae612016-08-02 09:21:41 +0100459
Antonio Nino Diaz37f97a52019-03-27 11:10:31 +0000460#define TCR_T0SZ_SHIFT U(0)
461#define TCR_T1SZ_SHIFT U(16)
462
Lin Ma741a3822014-06-27 16:56:30 -0700463/* (internal) physical address size bits in EL3/EL1 */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100464#define TCR_PS_BITS_4GB ULL(0x0)
465#define TCR_PS_BITS_64GB ULL(0x1)
466#define TCR_PS_BITS_1TB ULL(0x2)
467#define TCR_PS_BITS_4TB ULL(0x3)
468#define TCR_PS_BITS_16TB ULL(0x4)
469#define TCR_PS_BITS_256TB ULL(0x5)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100470
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700471#define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000)
472#define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000)
473#define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000)
474#define ADDR_MASK_40_TO_41 ULL(0x0000030000000000)
475#define ADDR_MASK_36_TO_39 ULL(0x000000F000000000)
476#define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100477
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100478#define TCR_RGN_INNER_NC (ULL(0x0) << 8)
479#define TCR_RGN_INNER_WBA (ULL(0x1) << 8)
480#define TCR_RGN_INNER_WT (ULL(0x2) << 8)
481#define TCR_RGN_INNER_WBNA (ULL(0x3) << 8)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100482
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100483#define TCR_RGN_OUTER_NC (ULL(0x0) << 10)
484#define TCR_RGN_OUTER_WBA (ULL(0x1) << 10)
485#define TCR_RGN_OUTER_WT (ULL(0x2) << 10)
486#define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100487
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100488#define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12)
489#define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12)
490#define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100491
Antonio Nino Diaz37f97a52019-03-27 11:10:31 +0000492#define TCR_RGN1_INNER_NC (ULL(0x0) << 24)
493#define TCR_RGN1_INNER_WBA (ULL(0x1) << 24)
494#define TCR_RGN1_INNER_WT (ULL(0x2) << 24)
495#define TCR_RGN1_INNER_WBNA (ULL(0x3) << 24)
496
497#define TCR_RGN1_OUTER_NC (ULL(0x0) << 26)
498#define TCR_RGN1_OUTER_WBA (ULL(0x1) << 26)
499#define TCR_RGN1_OUTER_WT (ULL(0x2) << 26)
500#define TCR_RGN1_OUTER_WBNA (ULL(0x3) << 26)
501
502#define TCR_SH1_NON_SHAREABLE (ULL(0x0) << 28)
503#define TCR_SH1_OUTER_SHAREABLE (ULL(0x2) << 28)
504#define TCR_SH1_INNER_SHAREABLE (ULL(0x3) << 28)
505
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100506#define TCR_TG0_SHIFT U(14)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100507#define TCR_TG0_MASK ULL(3)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100508#define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT)
509#define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT)
510#define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT)
511
Antonio Nino Diaz37f97a52019-03-27 11:10:31 +0000512#define TCR_TG1_SHIFT U(30)
513#define TCR_TG1_MASK ULL(3)
514#define TCR_TG1_16K (ULL(1) << TCR_TG1_SHIFT)
515#define TCR_TG1_4K (ULL(2) << TCR_TG1_SHIFT)
516#define TCR_TG1_64K (ULL(3) << TCR_TG1_SHIFT)
517
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100518#define TCR_EPD0_BIT (ULL(1) << 7)
519#define TCR_EPD1_BIT (ULL(1) << 23)
Antonio Nino Diazc8274a82017-09-15 10:30:34 +0100520
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700521#define MODE_SP_SHIFT U(0x0)
522#define MODE_SP_MASK U(0x1)
523#define MODE_SP_EL0 U(0x0)
524#define MODE_SP_ELX U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100525
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700526#define MODE_RW_SHIFT U(0x4)
527#define MODE_RW_MASK U(0x1)
528#define MODE_RW_64 U(0x0)
529#define MODE_RW_32 U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100530
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700531#define MODE_EL_SHIFT U(0x2)
532#define MODE_EL_MASK U(0x3)
533#define MODE_EL3 U(0x3)
534#define MODE_EL2 U(0x2)
535#define MODE_EL1 U(0x1)
536#define MODE_EL0 U(0x0)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100537
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700538#define MODE32_SHIFT U(0)
539#define MODE32_MASK U(0xf)
540#define MODE32_usr U(0x0)
541#define MODE32_fiq U(0x1)
542#define MODE32_irq U(0x2)
543#define MODE32_svc U(0x3)
544#define MODE32_mon U(0x6)
545#define MODE32_abt U(0x7)
546#define MODE32_hyp U(0xa)
547#define MODE32_und U(0xb)
548#define MODE32_sys U(0xf)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100549
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100550#define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK)
551#define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK)
552#define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK)
553#define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100554
John Tsichritzis55534172019-07-23 11:12:41 +0100555#define SPSR_64(el, sp, daif) \
556 (((MODE_RW_64 << MODE_RW_SHIFT) | \
557 (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \
558 (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \
559 (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) & \
560 (~(SPSR_SSBS_BIT_AARCH64)))
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100561
562#define SPSR_MODE32(mode, isa, endian, aif) \
John Tsichritzis55534172019-07-23 11:12:41 +0100563 (((MODE_RW_32 << MODE_RW_SHIFT) | \
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700564 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \
565 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \
566 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \
John Tsichritzis55534172019-07-23 11:12:41 +0100567 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) & \
568 (~(SPSR_SSBS_BIT_AARCH32)))
Achin Gupta4f6ad662013-10-25 09:08:21 +0100569
Dan Handley0cdebbd2015-03-30 17:15:16 +0100570/*
Isla Mitchellc4a1a072017-08-07 11:20:13 +0100571 * TTBR Definitions
572 */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100573#define TTBR_CNP_BIT ULL(0x1)
Isla Mitchellc4a1a072017-08-07 11:20:13 +0100574
575/*
Dan Handley0cdebbd2015-03-30 17:15:16 +0100576 * CTR_EL0 definitions
577 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700578#define CTR_CWG_SHIFT U(24)
579#define CTR_CWG_MASK U(0xf)
580#define CTR_ERG_SHIFT U(20)
581#define CTR_ERG_MASK U(0xf)
582#define CTR_DMINLINE_SHIFT U(16)
583#define CTR_DMINLINE_MASK U(0xf)
584#define CTR_L1IP_SHIFT U(14)
585#define CTR_L1IP_MASK U(0x3)
586#define CTR_IMINLINE_SHIFT U(0)
587#define CTR_IMINLINE_MASK U(0xf)
Dan Handley0cdebbd2015-03-30 17:15:16 +0100588
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700589#define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100590
Achin Gupta405406d2014-05-09 12:00:17 +0100591/* Physical timer control register bit fields shifts and masks */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700592#define CNTP_CTL_ENABLE_SHIFT U(0)
593#define CNTP_CTL_IMASK_SHIFT U(1)
594#define CNTP_CTL_ISTATUS_SHIFT U(2)
Achin Gupta405406d2014-05-09 12:00:17 +0100595
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700596#define CNTP_CTL_ENABLE_MASK U(1)
597#define CNTP_CTL_IMASK_MASK U(1)
598#define CNTP_CTL_ISTATUS_MASK U(1)
Achin Gupta405406d2014-05-09 12:00:17 +0100599
Achin Gupta4f6ad662013-10-25 09:08:21 +0100600/* Exception Syndrome register bits and bobs */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700601#define ESR_EC_SHIFT U(26)
602#define ESR_EC_MASK U(0x3f)
603#define ESR_EC_LENGTH U(6)
Justin Chadwell83e04882019-08-20 11:01:52 +0100604#define ESR_ISS_SHIFT U(0)
605#define ESR_ISS_LENGTH U(25)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700606#define EC_UNKNOWN U(0x0)
607#define EC_WFE_WFI U(0x1)
608#define EC_AARCH32_CP15_MRC_MCR U(0x3)
609#define EC_AARCH32_CP15_MRRC_MCRR U(0x4)
610#define EC_AARCH32_CP14_MRC_MCR U(0x5)
611#define EC_AARCH32_CP14_LDC_STC U(0x6)
612#define EC_FP_SIMD U(0x7)
613#define EC_AARCH32_CP10_MRC U(0x8)
614#define EC_AARCH32_CP14_MRRC_MCRR U(0xc)
615#define EC_ILLEGAL U(0xe)
616#define EC_AARCH32_SVC U(0x11)
617#define EC_AARCH32_HVC U(0x12)
618#define EC_AARCH32_SMC U(0x13)
619#define EC_AARCH64_SVC U(0x15)
620#define EC_AARCH64_HVC U(0x16)
621#define EC_AARCH64_SMC U(0x17)
622#define EC_AARCH64_SYS U(0x18)
623#define EC_IABORT_LOWER_EL U(0x20)
624#define EC_IABORT_CUR_EL U(0x21)
625#define EC_PC_ALIGN U(0x22)
626#define EC_DABORT_LOWER_EL U(0x24)
627#define EC_DABORT_CUR_EL U(0x25)
628#define EC_SP_ALIGN U(0x26)
629#define EC_AARCH32_FP U(0x28)
630#define EC_AARCH64_FP U(0x2c)
631#define EC_SERROR U(0x2f)
Justin Chadwell83e04882019-08-20 11:01:52 +0100632#define EC_BRK U(0x3c)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100633
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +0000634/*
635 * External Abort bit in Instruction and Data Aborts synchronous exception
636 * syndromes.
637 */
638#define ESR_ISS_EABORT_EA_BIT U(9)
639
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700640#define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100641
Vignesh Radhakrishnanb4a72942017-03-03 10:58:05 -0800642/* Reset bit inside the Reset management register for EL3 (RMR_EL3) */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700643#define RMR_RESET_REQUEST_SHIFT U(0x1)
644#define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT)
Vignesh Radhakrishnanb4a72942017-03-03 10:58:05 -0800645
Dan Handleyed6ff952014-05-14 17:44:19 +0100646/*******************************************************************************
Antonio Nino Diazac998032017-02-27 17:23:54 +0000647 * Definitions of register offsets, fields and macros for CPU system
648 * instructions.
649 ******************************************************************************/
650
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700651#define TLBI_ADDR_SHIFT U(12)
Antonio Nino Diazac998032017-02-27 17:23:54 +0000652#define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF)
653#define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK)
654
655/*******************************************************************************
Dan Handleyed6ff952014-05-14 17:44:19 +0100656 * Definitions of register offsets and fields in the CNTCTLBase Frame of the
657 * system level implementation of the Generic Timer.
658 ******************************************************************************/
Soby Mathew2d9f7952018-06-11 16:21:30 +0100659#define CNTCTLBASE_CNTFRQ U(0x0)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700660#define CNTNSAR U(0x4)
661#define CNTNSAR_NS_SHIFT(x) (x)
Dan Handleyed6ff952014-05-14 17:44:19 +0100662
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700663#define CNTACR_BASE(x) (U(0x40) + ((x) << 2))
664#define CNTACR_RPCT_SHIFT U(0x0)
665#define CNTACR_RVCT_SHIFT U(0x1)
666#define CNTACR_RFRQ_SHIFT U(0x2)
667#define CNTACR_RVOFF_SHIFT U(0x3)
668#define CNTACR_RWVT_SHIFT U(0x4)
669#define CNTACR_RWPT_SHIFT U(0x5)
Dan Handleyed6ff952014-05-14 17:44:19 +0100670
Soby Mathew2d9f7952018-06-11 16:21:30 +0100671/*******************************************************************************
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000672 * Definitions of register offsets and fields in the CNTBaseN Frame of the
Soby Mathew2d9f7952018-06-11 16:21:30 +0100673 * system level implementation of the Generic Timer.
674 ******************************************************************************/
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000675/* Physical Count register. */
676#define CNTPCT_LO U(0x0)
677/* Counter Frequency register. */
678#define CNTBASEN_CNTFRQ U(0x10)
679/* Physical Timer CompareValue register. */
680#define CNTP_CVAL_LO U(0x20)
681/* Physical Timer Control register. */
682#define CNTP_CTL U(0x2c)
Soby Mathew2d9f7952018-06-11 16:21:30 +0100683
David Cunado5f55e282016-10-31 17:37:34 +0000684/* PMCR_EL0 definitions */
David Cunado4168f2f2017-10-02 17:41:39 +0100685#define PMCR_EL0_RESET_VAL U(0x0)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700686#define PMCR_EL0_N_SHIFT U(11)
687#define PMCR_EL0_N_MASK U(0x1f)
David Cunado5f55e282016-10-31 17:37:34 +0000688#define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT)
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100689#define PMCR_EL0_LP_BIT (U(1) << 7)
David Cunado4168f2f2017-10-02 17:41:39 +0100690#define PMCR_EL0_LC_BIT (U(1) << 6)
691#define PMCR_EL0_DP_BIT (U(1) << 5)
692#define PMCR_EL0_X_BIT (U(1) << 4)
693#define PMCR_EL0_D_BIT (U(1) << 3)
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100694#define PMCR_EL0_C_BIT (U(1) << 2)
695#define PMCR_EL0_P_BIT (U(1) << 1)
696#define PMCR_EL0_E_BIT (U(1) << 0)
David Cunado5f55e282016-10-31 17:37:34 +0000697
Isla Mitchell02c63072017-07-21 14:44:36 +0100698/*******************************************************************************
David Cunadoce88eee2017-10-20 11:30:57 +0100699 * Definitions for system register interface to SVE
700 ******************************************************************************/
701#define ZCR_EL3 S3_6_C1_C2_0
702#define ZCR_EL2 S3_4_C1_C2_0
703
704/* ZCR_EL3 definitions */
705#define ZCR_EL3_LEN_MASK U(0xf)
706
707/* ZCR_EL2 definitions */
708#define ZCR_EL2_LEN_MASK U(0xf)
709
710/*******************************************************************************
Isla Mitchell02c63072017-07-21 14:44:36 +0100711 * Definitions of MAIR encodings for device and normal memory
712 ******************************************************************************/
713/*
714 * MAIR encodings for device memory attributes.
715 */
716#define MAIR_DEV_nGnRnE ULL(0x0)
717#define MAIR_DEV_nGnRE ULL(0x4)
718#define MAIR_DEV_nGRE ULL(0x8)
719#define MAIR_DEV_GRE ULL(0xc)
720
721/*
722 * MAIR encodings for normal memory attributes.
723 *
724 * Cache Policy
725 * WT: Write Through
726 * WB: Write Back
727 * NC: Non-Cacheable
728 *
729 * Transient Hint
730 * NTR: Non-Transient
731 * TR: Transient
732 *
733 * Allocation Policy
734 * RA: Read Allocate
735 * WA: Write Allocate
736 * RWA: Read and Write Allocate
737 * NA: No Allocation
738 */
739#define MAIR_NORM_WT_TR_WA ULL(0x1)
740#define MAIR_NORM_WT_TR_RA ULL(0x2)
741#define MAIR_NORM_WT_TR_RWA ULL(0x3)
742#define MAIR_NORM_NC ULL(0x4)
743#define MAIR_NORM_WB_TR_WA ULL(0x5)
744#define MAIR_NORM_WB_TR_RA ULL(0x6)
745#define MAIR_NORM_WB_TR_RWA ULL(0x7)
746#define MAIR_NORM_WT_NTR_NA ULL(0x8)
747#define MAIR_NORM_WT_NTR_WA ULL(0x9)
748#define MAIR_NORM_WT_NTR_RA ULL(0xa)
749#define MAIR_NORM_WT_NTR_RWA ULL(0xb)
750#define MAIR_NORM_WB_NTR_NA ULL(0xc)
751#define MAIR_NORM_WB_NTR_WA ULL(0xd)
752#define MAIR_NORM_WB_NTR_RA ULL(0xe)
753#define MAIR_NORM_WB_NTR_RWA ULL(0xf)
754
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100755#define MAIR_NORM_OUTER_SHIFT U(4)
Isla Mitchell02c63072017-07-21 14:44:36 +0100756
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100757#define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \
758 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT))
Isla Mitchell02c63072017-07-21 14:44:36 +0100759
Jeenu Viswambharan1dc771b2017-10-19 09:15:15 +0100760/* PAR_EL1 fields */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100761#define PAR_F_SHIFT U(0)
762#define PAR_F_MASK ULL(0x1)
763#define PAR_ADDR_SHIFT U(12)
764#define PAR_ADDR_MASK (BIT(40) - ULL(1)) /* 40-bits-wide page address */
Jeenu Viswambharan1dc771b2017-10-19 09:15:15 +0100765
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +0100766/*******************************************************************************
767 * Definitions for system register interface to SPE
768 ******************************************************************************/
769#define PMBLIMITR_EL1 S3_0_C9_C10_0
770
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100771/*******************************************************************************
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +0100772 * Definitions for system register interface to MPAM
773 ******************************************************************************/
774#define MPAMIDR_EL1 S3_0_C10_C4_4
775#define MPAM2_EL2 S3_4_C10_C5_0
776#define MPAMHCR_EL2 S3_4_C10_C4_0
777#define MPAM3_EL3 S3_6_C10_C5_0
778
779/*******************************************************************************
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100780 * Definitions for system register interface to AMU for ARMv8.4 onwards
781 ******************************************************************************/
782#define AMCR_EL0 S3_3_C13_C2_0
783#define AMCFGR_EL0 S3_3_C13_C2_1
784#define AMCGCR_EL0 S3_3_C13_C2_2
785#define AMUSERENR_EL0 S3_3_C13_C2_3
786#define AMCNTENCLR0_EL0 S3_3_C13_C2_4
787#define AMCNTENSET0_EL0 S3_3_C13_C2_5
788#define AMCNTENCLR1_EL0 S3_3_C13_C3_0
789#define AMCNTENSET1_EL0 S3_3_C13_C3_1
790
791/* Activity Monitor Group 0 Event Counter Registers */
792#define AMEVCNTR00_EL0 S3_3_C13_C4_0
793#define AMEVCNTR01_EL0 S3_3_C13_C4_1
794#define AMEVCNTR02_EL0 S3_3_C13_C4_2
795#define AMEVCNTR03_EL0 S3_3_C13_C4_3
796
797/* Activity Monitor Group 0 Event Type Registers */
798#define AMEVTYPER00_EL0 S3_3_C13_C6_0
799#define AMEVTYPER01_EL0 S3_3_C13_C6_1
800#define AMEVTYPER02_EL0 S3_3_C13_C6_2
801#define AMEVTYPER03_EL0 S3_3_C13_C6_3
802
Dimitris Papastamos525c37a2017-11-13 09:49:45 +0000803/* Activity Monitor Group 1 Event Counter Registers */
804#define AMEVCNTR10_EL0 S3_3_C13_C12_0
805#define AMEVCNTR11_EL0 S3_3_C13_C12_1
806#define AMEVCNTR12_EL0 S3_3_C13_C12_2
807#define AMEVCNTR13_EL0 S3_3_C13_C12_3
808#define AMEVCNTR14_EL0 S3_3_C13_C12_4
809#define AMEVCNTR15_EL0 S3_3_C13_C12_5
810#define AMEVCNTR16_EL0 S3_3_C13_C12_6
811#define AMEVCNTR17_EL0 S3_3_C13_C12_7
812#define AMEVCNTR18_EL0 S3_3_C13_C13_0
813#define AMEVCNTR19_EL0 S3_3_C13_C13_1
814#define AMEVCNTR1A_EL0 S3_3_C13_C13_2
815#define AMEVCNTR1B_EL0 S3_3_C13_C13_3
816#define AMEVCNTR1C_EL0 S3_3_C13_C13_4
817#define AMEVCNTR1D_EL0 S3_3_C13_C13_5
818#define AMEVCNTR1E_EL0 S3_3_C13_C13_6
819#define AMEVCNTR1F_EL0 S3_3_C13_C13_7
820
821/* Activity Monitor Group 1 Event Type Registers */
822#define AMEVTYPER10_EL0 S3_3_C13_C14_0
823#define AMEVTYPER11_EL0 S3_3_C13_C14_1
824#define AMEVTYPER12_EL0 S3_3_C13_C14_2
825#define AMEVTYPER13_EL0 S3_3_C13_C14_3
826#define AMEVTYPER14_EL0 S3_3_C13_C14_4
827#define AMEVTYPER15_EL0 S3_3_C13_C14_5
828#define AMEVTYPER16_EL0 S3_3_C13_C14_6
829#define AMEVTYPER17_EL0 S3_3_C13_C14_7
830#define AMEVTYPER18_EL0 S3_3_C13_C15_0
831#define AMEVTYPER19_EL0 S3_3_C13_C15_1
832#define AMEVTYPER1A_EL0 S3_3_C13_C15_2
833#define AMEVTYPER1B_EL0 S3_3_C13_C15_3
834#define AMEVTYPER1C_EL0 S3_3_C13_C15_4
835#define AMEVTYPER1D_EL0 S3_3_C13_C15_5
836#define AMEVTYPER1E_EL0 S3_3_C13_C15_6
837#define AMEVTYPER1F_EL0 S3_3_C13_C15_7
838
839/* AMCGCR_EL0 definitions */
840#define AMCGCR_EL0_CG1NC_SHIFT U(8)
841#define AMCGCR_EL0_CG1NC_LENGTH U(8)
842#define AMCGCR_EL0_CG1NC_MASK U(0xff)
843
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +0100844/* MPAM register definitions */
845#define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63)
Louis Mayencourtbdfa1032019-02-11 11:25:50 +0000846#define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31)
847
848#define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49)
849#define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48)
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +0100850
851#define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17)
852
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100853/*******************************************************************************
854 * RAS system registers
Sathees Balya0911df12018-12-06 13:33:24 +0000855 ******************************************************************************/
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100856#define DISR_EL1 S3_0_C12_C1_1
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100857#define DISR_A_BIT U(31)
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100858
Jeenu Viswambharan19f6cf22017-12-07 08:43:05 +0000859#define ERRIDR_EL1 S3_0_C5_C3_0
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100860#define ERRIDR_MASK U(0xffff)
Jeenu Viswambharan19f6cf22017-12-07 08:43:05 +0000861
862#define ERRSELR_EL1 S3_0_C5_C3_1
863
864/* System register access to Standard Error Record registers */
865#define ERXFR_EL1 S3_0_C5_C4_0
866#define ERXCTLR_EL1 S3_0_C5_C4_1
867#define ERXSTATUS_EL1 S3_0_C5_C4_2
868#define ERXADDR_EL1 S3_0_C5_C4_3
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000869#define ERXPFGF_EL1 S3_0_C5_C4_4
870#define ERXPFGCTL_EL1 S3_0_C5_C4_5
871#define ERXPFGCDN_EL1 S3_0_C5_C4_6
Jan Dabros82ef8bf2018-08-30 13:52:23 +0200872#define ERXMISC0_EL1 S3_0_C5_C5_0
873#define ERXMISC1_EL1 S3_0_C5_C5_1
Jeenu Viswambharan19f6cf22017-12-07 08:43:05 +0000874
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000875#define ERXCTLR_ED_BIT (U(1) << 0)
876#define ERXCTLR_UE_BIT (U(1) << 4)
877
878#define ERXPFGCTL_UC_BIT (U(1) << 1)
879#define ERXPFGCTL_UEU_BIT (U(1) << 2)
880#define ERXPFGCTL_CDEN_BIT (U(1) << 31)
881
882/*******************************************************************************
883 * Armv8.3 Pointer Authentication Registers
Sathees Balya0911df12018-12-06 13:33:24 +0000884 ******************************************************************************/
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000885#define APIAKeyLo_EL1 S3_0_C2_C1_0
886#define APIAKeyHi_EL1 S3_0_C2_C1_1
887#define APIBKeyLo_EL1 S3_0_C2_C1_2
888#define APIBKeyHi_EL1 S3_0_C2_C1_3
889#define APDAKeyLo_EL1 S3_0_C2_C2_0
890#define APDAKeyHi_EL1 S3_0_C2_C2_1
891#define APDBKeyLo_EL1 S3_0_C2_C2_2
892#define APDBKeyHi_EL1 S3_0_C2_C2_3
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000893#define APGAKeyLo_EL1 S3_0_C2_C3_0
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000894#define APGAKeyHi_EL1 S3_0_C2_C3_1
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000895
Sathees Balya0911df12018-12-06 13:33:24 +0000896/*******************************************************************************
897 * Armv8.4 Data Independent Timing Registers
898 ******************************************************************************/
899#define DIT S3_3_C4_C2_5
900#define DIT_BIT BIT(24)
901
John Tsichritzis1f9ff492019-03-04 16:41:26 +0000902/*******************************************************************************
903 * Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field
904 ******************************************************************************/
905#define SSBS S3_3_C4_C2_6
906
Justin Chadwell1c7c13a2019-07-18 14:25:33 +0100907/*******************************************************************************
908 * Armv8.5 - Memory Tagging Extension Registers
909 ******************************************************************************/
910#define TFSRE0_EL1 S3_0_C5_C6_1
911#define TFSR_EL1 S3_0_C5_C6_0
912#define RGSR_EL1 S3_0_C1_C0_5
913#define GCR_EL1 S3_0_C1_C0_6
914
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +0100915#endif /* ARCH_H */