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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Rohit Mathew3dc3cad2022-11-11 18:45:11 +00002 * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
Varun Wadekar423045d2022-05-25 12:45:22 +01003 * Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01004 *
dp-armfa3cf0b2017-05-03 09:38:09 +01005 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01006 */
7
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +01008#ifndef ARCH_H
9#define ARCH_H
Achin Gupta4f6ad662013-10-25 09:08:21 +010010
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <lib/utils_def.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010012
13/*******************************************************************************
14 * MIDR bit definitions
15 ******************************************************************************/
Varun Wadekarc6a11f62017-05-25 18:04:48 -070016#define MIDR_IMPL_MASK U(0xff)
17#define MIDR_IMPL_SHIFT U(0x18)
18#define MIDR_VAR_SHIFT U(20)
19#define MIDR_VAR_BITS U(4)
20#define MIDR_VAR_MASK U(0xf)
21#define MIDR_REV_SHIFT U(0)
22#define MIDR_REV_BITS U(4)
23#define MIDR_REV_MASK U(0xf)
24#define MIDR_PN_MASK U(0xfff)
25#define MIDR_PN_SHIFT U(0x4)
Achin Gupta4f6ad662013-10-25 09:08:21 +010026
27/*******************************************************************************
28 * MPIDR macros
29 ******************************************************************************/
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010030#define MPIDR_MT_MASK (ULL(1) << 24)
Achin Gupta4f6ad662013-10-25 09:08:21 +010031#define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK
Varun Wadekarc6a11f62017-05-25 18:04:48 -070032#define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS)
33#define MPIDR_AFFINITY_BITS U(8)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010034#define MPIDR_AFFLVL_MASK ULL(0xff)
Varun Wadekarc6a11f62017-05-25 18:04:48 -070035#define MPIDR_AFF0_SHIFT U(0)
36#define MPIDR_AFF1_SHIFT U(8)
37#define MPIDR_AFF2_SHIFT U(16)
38#define MPIDR_AFF3_SHIFT U(32)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000039#define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010040#define MPIDR_AFFINITY_MASK ULL(0xff00ffffff)
Varun Wadekarc6a11f62017-05-25 18:04:48 -070041#define MPIDR_AFFLVL_SHIFT U(3)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000042#define MPIDR_AFFLVL0 ULL(0x0)
43#define MPIDR_AFFLVL1 ULL(0x1)
44#define MPIDR_AFFLVL2 ULL(0x2)
45#define MPIDR_AFFLVL3 ULL(0x3)
46#define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000047#define MPIDR_AFFLVL0_VAL(mpidr) \
Antonio Nino Diaz34235a32018-07-11 16:45:49 +010048 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK)
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000049#define MPIDR_AFFLVL1_VAL(mpidr) \
Antonio Nino Diaz34235a32018-07-11 16:45:49 +010050 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK)
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000051#define MPIDR_AFFLVL2_VAL(mpidr) \
Antonio Nino Diaz34235a32018-07-11 16:45:49 +010052 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK)
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000053#define MPIDR_AFFLVL3_VAL(mpidr) \
Antonio Nino Diaz34235a32018-07-11 16:45:49 +010054 (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK)
Soby Mathewe2b2d8f2014-12-04 14:14:12 +000055/*
56 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to
57 * add one while using this macro to define array sizes.
58 * TODO: Support only the first 3 affinity levels for now.
59 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070060#define MPIDR_MAX_AFFLVL U(2)
Achin Gupta4f6ad662013-10-25 09:08:21 +010061
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000062#define MPID_MASK (MPIDR_MT_MASK | \
63 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \
64 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \
65 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \
66 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT))
67
68#define MPIDR_AFF_ID(mpid, n) \
69 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK)
70
71/*
72 * An invalid MPID. This value can be used by functions that return an MPID to
73 * indicate an error.
74 */
75#define INVALID_MPID U(0xFFFFFFFF)
Achin Gupta4f6ad662013-10-25 09:08:21 +010076
77/*******************************************************************************
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010078 * Definitions for CPU system register interface to GICv3
79 ******************************************************************************/
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000080#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7
81#define ICC_SGI1R S3_0_C12_C11_5
Florian Lugoud4e25032021-09-08 12:40:24 +020082#define ICC_ASGI1R S3_0_C12_C11_6
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000083#define ICC_SRE_EL1 S3_0_C12_C12_5
84#define ICC_SRE_EL2 S3_4_C12_C9_5
85#define ICC_SRE_EL3 S3_6_C12_C12_5
86#define ICC_CTLR_EL1 S3_0_C12_C12_4
87#define ICC_CTLR_EL3 S3_6_C12_C12_4
88#define ICC_PMR_EL1 S3_0_C4_C6_0
89#define ICC_RPR_EL1 S3_0_C12_C11_3
90#define ICC_IGRPEN1_EL3 S3_6_c12_c12_7
91#define ICC_IGRPEN0_EL1 S3_0_c12_c12_6
92#define ICC_HPPIR0_EL1 S3_0_c12_c8_2
93#define ICC_HPPIR1_EL1 S3_0_c12_c12_2
94#define ICC_IAR0_EL1 S3_0_c12_c8_0
95#define ICC_IAR1_EL1 S3_0_c12_c12_0
96#define ICC_EOIR0_EL1 S3_0_c12_c8_1
97#define ICC_EOIR1_EL1 S3_0_c12_c12_1
98#define ICC_SGI0R_EL1 S3_0_c12_c11_7
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010099
100/*******************************************************************************
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000101 * Definitions for EL2 system registers for save/restore routine
102 ******************************************************************************/
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000103#define CNTPOFF_EL2 S3_4_C14_C0_6
104#define HAFGRTR_EL2 S3_4_C3_C1_6
105#define HDFGRTR_EL2 S3_4_C3_C1_4
106#define HDFGWTR_EL2 S3_4_C3_C1_5
107#define HFGITR_EL2 S3_4_C1_C1_6
108#define HFGRTR_EL2 S3_4_C1_C1_4
109#define HFGWTR_EL2 S3_4_C1_C1_5
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000110#define ICH_HCR_EL2 S3_4_C12_C11_0
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000111#define ICH_VMCR_EL2 S3_4_C12_C11_7
Varun Wadekar423045d2022-05-25 12:45:22 +0100112#define MPAMVPM0_EL2 S3_4_C10_C6_0
113#define MPAMVPM1_EL2 S3_4_C10_C6_1
114#define MPAMVPM2_EL2 S3_4_C10_C6_2
115#define MPAMVPM3_EL2 S3_4_C10_C6_3
116#define MPAMVPM4_EL2 S3_4_C10_C6_4
117#define MPAMVPM5_EL2 S3_4_C10_C6_5
118#define MPAMVPM6_EL2 S3_4_C10_C6_6
119#define MPAMVPM7_EL2 S3_4_C10_C6_7
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000120#define MPAMVPMV_EL2 S3_4_C10_C4_1
Max Shvetsovc9e2c922020-02-17 16:15:47 +0000121#define TRFCR_EL2 S3_4_C1_C2_1
Andre Przywaraedc449d2023-01-27 14:09:20 +0000122#define VNCR_EL2 S3_4_C2_C2_0
Max Shvetsovc9e2c922020-02-17 16:15:47 +0000123#define PMSCR_EL2 S3_4_C9_C9_0
124#define TFSR_EL2 S3_4_C5_C6_0
Andre Przywara98908b32022-11-17 16:42:09 +0000125#define CONTEXTIDR_EL2 S3_4_C13_C0_1
126#define TTBR1_EL2 S3_4_C2_C0_1
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000127
128/*******************************************************************************
Achin Guptac2b43af2013-10-31 11:27:43 +0000129 * Generic timer memory mapped registers & offsets
130 ******************************************************************************/
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700131#define CNTCR_OFF U(0x000)
Yann Gautier007d7452019-04-17 13:47:07 +0200132#define CNTCV_OFF U(0x008)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700133#define CNTFID_OFF U(0x020)
Achin Guptac2b43af2013-10-31 11:27:43 +0000134
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700135#define CNTCR_EN (U(1) << 0)
136#define CNTCR_HDBG (U(1) << 1)
Sandrine Bailleux3fa98472014-03-31 11:25:18 +0100137#define CNTCR_FCREQ(x) ((x) << 8)
Achin Guptac2b43af2013-10-31 11:27:43 +0000138
139/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +0100140 * System register bit definitions
141 ******************************************************************************/
142/* CLIDR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700143#define LOUIS_SHIFT U(21)
144#define LOC_SHIFT U(24)
Alexei Fedorova95a5892019-07-29 17:22:53 +0100145#define CTYPE_SHIFT(n) U(3 * (n - 1))
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700146#define CLIDR_FIELD_WIDTH U(3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100147
148/* CSSELR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700149#define LEVEL_SHIFT U(1)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100150
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100151/* Data cache set/way op type defines */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700152#define DCISW U(0x0)
153#define DCCISW U(0x1)
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +0000154#if ERRATA_A53_827319
155#define DCCSW DCCISW
156#else
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700157#define DCCSW U(0x2)
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +0000158#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100159
160/* ID_AA64PFR0_EL1 definitions */
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000161#define ID_AA64PFR0_EL0_SHIFT U(0)
162#define ID_AA64PFR0_EL1_SHIFT U(4)
163#define ID_AA64PFR0_EL2_SHIFT U(8)
164#define ID_AA64PFR0_EL3_SHIFT U(12)
165
166#define ID_AA64PFR0_AMU_SHIFT U(44)
167#define ID_AA64PFR0_AMU_MASK ULL(0xf)
168#define ID_AA64PFR0_AMU_NOT_SUPPORTED U(0x0)
169#define ID_AA64PFR0_AMU_V1 ULL(0x1)
170#define ID_AA64PFR0_AMU_V1P1 U(0x2)
171
172#define ID_AA64PFR0_ELX_MASK ULL(0xf)
173
174#define ID_AA64PFR0_GIC_SHIFT U(24)
175#define ID_AA64PFR0_GIC_WIDTH U(4)
176#define ID_AA64PFR0_GIC_MASK ULL(0xf)
177
178#define ID_AA64PFR0_SVE_SHIFT U(32)
179#define ID_AA64PFR0_SVE_MASK ULL(0xf)
180#define ID_AA64PFR0_SVE_SUPPORTED ULL(0x1)
181#define ID_AA64PFR0_SVE_LENGTH U(4)
182
183#define ID_AA64PFR0_SEL2_SHIFT U(36)
184#define ID_AA64PFR0_SEL2_MASK ULL(0xf)
185
186#define ID_AA64PFR0_MPAM_SHIFT U(40)
187#define ID_AA64PFR0_MPAM_MASK ULL(0xf)
188
189#define ID_AA64PFR0_DIT_SHIFT U(48)
190#define ID_AA64PFR0_DIT_MASK ULL(0xf)
191#define ID_AA64PFR0_DIT_LENGTH U(4)
192#define ID_AA64PFR0_DIT_SUPPORTED U(1)
193
194#define ID_AA64PFR0_CSV2_SHIFT U(56)
195#define ID_AA64PFR0_CSV2_MASK ULL(0xf)
196#define ID_AA64PFR0_CSV2_LENGTH U(4)
197#define ID_AA64PFR0_CSV2_2_SUPPORTED ULL(0x2)
198
Zelalem Aweke79e3d292021-07-08 16:51:14 -0500199#define ID_AA64PFR0_FEAT_RME_SHIFT U(52)
200#define ID_AA64PFR0_FEAT_RME_MASK ULL(0xf)
201#define ID_AA64PFR0_FEAT_RME_LENGTH U(4)
202#define ID_AA64PFR0_FEAT_RME_NOT_SUPPORTED U(0)
203#define ID_AA64PFR0_FEAT_RME_V1 U(1)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100204
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000205#define ID_AA64PFR0_RAS_SHIFT U(28)
206#define ID_AA64PFR0_RAS_MASK ULL(0xf)
207#define ID_AA64PFR0_RAS_NOT_SUPPORTED ULL(0x0)
208#define ID_AA64PFR0_RAS_LENGTH U(4)
209
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100210/* Exception level handling */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100211#define EL_IMPL_NONE ULL(0)
212#define EL_IMPL_A64ONLY ULL(1)
213#define EL_IMPL_A64_A32 ULL(2)
Jeenu Viswambharan2a9b8822017-02-21 14:40:44 +0000214
Manish V Badarkhef7ee0642021-07-07 16:27:10 +0100215/* ID_AA64DFR0_EL1.TraceVer definitions */
216#define ID_AA64DFR0_TRACEVER_SHIFT U(4)
217#define ID_AA64DFR0_TRACEVER_MASK ULL(0xf)
218#define ID_AA64DFR0_TRACEVER_SUPPORTED ULL(1)
219#define ID_AA64DFR0_TRACEVER_LENGTH U(4)
Manish V Badarkhe8ce33942021-07-18 02:26:27 +0100220#define ID_AA64DFR0_TRACEFILT_SHIFT U(40)
221#define ID_AA64DFR0_TRACEFILT_MASK U(0xf)
222#define ID_AA64DFR0_TRACEFILT_SUPPORTED U(1)
223#define ID_AA64DFR0_TRACEFILT_LENGTH U(4)
Boyan Karatotev05504ba2023-02-15 13:21:50 +0000224#define ID_AA64DFR0_PMUVER_LENGTH U(4)
225#define ID_AA64DFR0_PMUVER_SHIFT U(8)
226#define ID_AA64DFR0_PMUVER_MASK U(0xf)
227#define ID_AA64DFR0_PMUVER_PMUV3 U(1)
228#define ID_AA64DFR0_PMUVER_PMUV3P7 U(7)
229#define ID_AA64DFR0_PMUVER_IMP_DEF U(0xf)
Manish V Badarkhef7ee0642021-07-07 16:27:10 +0100230
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100231/* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000232#define ID_AA64DFR0_PMS_SHIFT U(32)
233#define ID_AA64DFR0_PMS_MASK ULL(0xf)
234#define ID_AA64DFR0_SPE_SUPPORTED ULL(0x1)
235#define ID_AA64DFR0_SPE_NOT_SUPPORTED ULL(0x0)
Achin Gupta92712a52015-09-03 14:18:02 +0100236
Manish V Badarkhe20df29c2021-07-02 09:10:56 +0100237/* ID_AA64DFR0_EL1.TraceBuffer definitions */
238#define ID_AA64DFR0_TRACEBUFFER_SHIFT U(44)
239#define ID_AA64DFR0_TRACEBUFFER_MASK ULL(0xf)
240#define ID_AA64DFR0_TRACEBUFFER_SUPPORTED ULL(1)
241
Javier Almansa Sobrinof3a4c542020-11-23 18:38:15 +0000242/* ID_AA64DFR0_EL1.MTPMU definitions (for ARMv8.6+) */
243#define ID_AA64DFR0_MTPMU_SHIFT U(48)
244#define ID_AA64DFR0_MTPMU_MASK ULL(0xf)
245#define ID_AA64DFR0_MTPMU_SUPPORTED ULL(1)
Boyan Karatotev677ed8a2023-02-16 09:45:29 +0000246#define ID_AA64DFR0_MTPMU_DISABLED ULL(15)
Javier Almansa Sobrinof3a4c542020-11-23 18:38:15 +0000247
johpow0181865962022-01-28 17:06:20 -0600248/* ID_AA64DFR0_EL1.BRBE definitions */
249#define ID_AA64DFR0_BRBE_SHIFT U(52)
250#define ID_AA64DFR0_BRBE_MASK ULL(0xf)
251#define ID_AA64DFR0_BRBE_SUPPORTED ULL(1)
252
Tomas Pilar6fd816e2020-10-28 15:34:12 +0000253/* ID_AA64ISAR0_EL1 definitions */
johpow019baade32021-07-08 14:14:00 -0500254#define ID_AA64ISAR0_RNDR_SHIFT U(60)
255#define ID_AA64ISAR0_RNDR_MASK ULL(0xf)
Tomas Pilar6fd816e2020-10-28 15:34:12 +0000256
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000257/* ID_AA64ISAR1_EL1 definitions */
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000258#define ID_AA64ISAR1_EL1 S3_0_C0_C6_1
259
260#define ID_AA64ISAR1_GPI_SHIFT U(28)
261#define ID_AA64ISAR1_GPI_MASK ULL(0xf)
262#define ID_AA64ISAR1_GPA_SHIFT U(24)
263#define ID_AA64ISAR1_GPA_MASK ULL(0xf)
264
265#define ID_AA64ISAR1_API_SHIFT U(8)
266#define ID_AA64ISAR1_API_MASK ULL(0xf)
267#define ID_AA64ISAR1_APA_SHIFT U(4)
268#define ID_AA64ISAR1_APA_MASK ULL(0xf)
269
270#define ID_AA64ISAR1_SB_SHIFT U(36)
271#define ID_AA64ISAR1_SB_MASK ULL(0xf)
272#define ID_AA64ISAR1_SB_SUPPORTED ULL(0x1)
273#define ID_AA64ISAR1_SB_NOT_SUPPORTED ULL(0x0)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000274
Juan Pablo Condee089a172022-06-29 17:44:43 -0400275/* ID_AA64ISAR2_EL1 definitions */
276#define ID_AA64ISAR2_EL1 S3_0_C0_C6_2
277
Maksims Svecovsdf4ad842023-03-24 13:05:09 +0000278/* ID_AA64PFR2_EL1 definitions */
279#define ID_AA64PFR2_EL1 S3_0_C0_C4_2
280
Juan Pablo Condee089a172022-06-29 17:44:43 -0400281#define ID_AA64ISAR2_GPA3_SHIFT U(8)
282#define ID_AA64ISAR2_GPA3_MASK ULL(0xf)
283
284#define ID_AA64ISAR2_APA3_SHIFT U(12)
285#define ID_AA64ISAR2_APA3_MASK ULL(0xf)
286
Antonio Nino Diazc326c342019-01-11 11:20:10 +0000287/* ID_AA64MMFR0_EL1 definitions */
288#define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0)
289#define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf)
290
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700291#define PARANGE_0000 U(32)
292#define PARANGE_0001 U(36)
293#define PARANGE_0010 U(40)
294#define PARANGE_0011 U(42)
295#define PARANGE_0100 U(44)
296#define PARANGE_0101 U(48)
Antonio Nino Diazb9ef6642017-11-17 09:52:53 +0000297#define PARANGE_0110 U(52)
Antonio Nino Diazd1beee22016-12-13 15:28:54 +0000298
Jimmy Brisson83573892020-04-16 10:48:02 -0500299#define ID_AA64MMFR0_EL1_ECV_SHIFT U(60)
300#define ID_AA64MMFR0_EL1_ECV_MASK ULL(0xf)
301#define ID_AA64MMFR0_EL1_ECV_NOT_SUPPORTED ULL(0x0)
302#define ID_AA64MMFR0_EL1_ECV_SUPPORTED ULL(0x1)
303#define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2)
304
Jimmy Brissonecc3c672020-04-16 10:47:56 -0500305#define ID_AA64MMFR0_EL1_FGT_SHIFT U(56)
306#define ID_AA64MMFR0_EL1_FGT_MASK ULL(0xf)
307#define ID_AA64MMFR0_EL1_FGT_SUPPORTED ULL(0x1)
308#define ID_AA64MMFR0_EL1_FGT_NOT_SUPPORTED ULL(0x0)
309
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100310#define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100311#define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf)
312#define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0)
Javier Almansa Sobrino8c8107e2023-05-03 12:16:11 +0100313#define ID_AA64MMFR0_EL1_TGRAN4_52B_SUPPORTED ULL(0x1)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100314#define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100315
316#define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100317#define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf)
318#define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED ULL(0x0)
319#define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED ULL(0xf)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100320
321#define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100322#define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf)
323#define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1)
324#define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0)
Javier Almansa Sobrino8c8107e2023-05-03 12:16:11 +0100325#define ID_AA64MMFR0_EL1_TGRAN16_52B_SUPPORTED ULL(0x2)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100326
johpow013e24c162020-04-22 14:05:13 -0500327/* ID_AA64MMFR1_EL1 definitions */
328#define ID_AA64MMFR1_EL1_TWED_SHIFT U(32)
329#define ID_AA64MMFR1_EL1_TWED_MASK ULL(0xf)
330#define ID_AA64MMFR1_EL1_TWED_SUPPORTED ULL(0x1)
331#define ID_AA64MMFR1_EL1_TWED_NOT_SUPPORTED ULL(0x0)
332
Alexei Fedorovc082f032020-11-25 14:07:05 +0000333#define ID_AA64MMFR1_EL1_PAN_SHIFT U(20)
334#define ID_AA64MMFR1_EL1_PAN_MASK ULL(0xf)
335#define ID_AA64MMFR1_EL1_PAN_NOT_SUPPORTED ULL(0x0)
336#define ID_AA64MMFR1_EL1_PAN_SUPPORTED ULL(0x1)
337#define ID_AA64MMFR1_EL1_PAN2_SUPPORTED ULL(0x2)
338#define ID_AA64MMFR1_EL1_PAN3_SUPPORTED ULL(0x3)
339
Daniel Boulby44b43332020-11-25 16:36:46 +0000340#define ID_AA64MMFR1_EL1_VHE_SHIFT U(8)
341#define ID_AA64MMFR1_EL1_VHE_MASK ULL(0xf)
342
johpow019baade32021-07-08 14:14:00 -0500343#define ID_AA64MMFR1_EL1_HCX_SHIFT U(40)
344#define ID_AA64MMFR1_EL1_HCX_MASK ULL(0xf)
345#define ID_AA64MMFR1_EL1_HCX_SUPPORTED ULL(0x1)
346#define ID_AA64MMFR1_EL1_HCX_NOT_SUPPORTED ULL(0x0)
johpow01f91e59f2021-08-04 19:38:18 -0500347
Antonio Nino Diazc326c342019-01-11 11:20:10 +0000348/* ID_AA64MMFR2_EL1 definitions */
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000349#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2
Sathees Balya74155972019-01-25 11:36:01 +0000350
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000351#define ID_AA64MMFR2_EL1_ST_SHIFT U(28)
352#define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf)
Sathees Balya74155972019-01-25 11:36:01 +0000353
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000354#define ID_AA64MMFR2_EL1_CCIDX_SHIFT U(20)
355#define ID_AA64MMFR2_EL1_CCIDX_MASK ULL(0xf)
356#define ID_AA64MMFR2_EL1_CCIDX_LENGTH U(4)
357
358#define ID_AA64MMFR2_EL1_CNP_SHIFT U(0)
359#define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf)
johpow0174b7e442021-12-01 13:18:30 -0600360
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000361#define ID_AA64MMFR2_EL1_NV_SHIFT U(24)
362#define ID_AA64MMFR2_EL1_NV_MASK ULL(0xf)
363#define ID_AA64MMFR2_EL1_NV_NOT_SUPPORTED ULL(0x0)
364#define ID_AA64MMFR2_EL1_NV_SUPPORTED ULL(0x1)
365#define ID_AA64MMFR2_EL1_NV2_SUPPORTED ULL(0x2)
Antonio Nino Diazc326c342019-01-11 11:20:10 +0000366
Mark Brownc37eee72023-03-14 20:13:03 +0000367/* ID_AA64MMFR3_EL1 definitions */
368#define ID_AA64MMFR3_EL1 S3_0_C0_C7_3
369
Mark Brown293a6612023-03-14 20:48:43 +0000370#define ID_AA64MMFR3_EL1_S2POE_SHIFT U(20)
371#define ID_AA64MMFR3_EL1_S2POE_MASK ULL(0xf)
372
373#define ID_AA64MMFR3_EL1_S1POE_SHIFT U(16)
374#define ID_AA64MMFR3_EL1_S1POE_MASK ULL(0xf)
375
376#define ID_AA64MMFR3_EL1_S2PIE_SHIFT U(12)
377#define ID_AA64MMFR3_EL1_S2PIE_MASK ULL(0xf)
378
379#define ID_AA64MMFR3_EL1_S1PIE_SHIFT U(8)
380#define ID_AA64MMFR3_EL1_S1PIE_MASK ULL(0xf)
381
Mark Brownc37eee72023-03-14 20:13:03 +0000382#define ID_AA64MMFR3_EL1_TCRX_SHIFT U(0)
383#define ID_AA64MMFR3_EL1_TCRX_MASK ULL(0xf)
384
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000385/* ID_AA64PFR1_EL1 definitions */
Mark Brown326f2952023-03-14 21:33:04 +0000386#define ID_AA64PFR1_EL1_GCS_SHIFT U(44)
387#define ID_AA64PFR1_EL1_GCS_MASK ULL(0xf)
388
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000389#define ID_AA64PFR1_EL1_SSBS_SHIFT U(4)
390#define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf)
391
392#define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */
393
Alexei Fedorov90f2e882019-05-24 12:17:09 +0100394#define ID_AA64PFR1_EL1_BT_SHIFT U(0)
395#define ID_AA64PFR1_EL1_BT_MASK ULL(0xf)
396
397#define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */
398
Soby Mathew830f0ad2019-07-12 09:23:38 +0100399#define ID_AA64PFR1_EL1_MTE_SHIFT U(8)
400#define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf)
401
Juan Pablo Conde42305f22022-07-12 16:40:29 -0400402#define ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT U(28)
403#define ID_AA64PFR1_EL1_RNDR_TRAP_MASK U(0xf)
404
405#define ID_AA64PFR1_EL1_RNG_TRAP_SUPPORTED ULL(0x1)
406#define ID_AA64PFR1_EL1_RNG_TRAP_NOT_SUPPORTED ULL(0x0)
407
Maksims Svecovsdf4ad842023-03-24 13:05:09 +0000408/* ID_AA64PFR2_EL1 definitions */
409#define ID_AA64PFR2_EL1_MTEPERM_SHIFT U(0)
410#define ID_AA64PFR2_EL1_MTEPERM_MASK ULL(0xf)
411
412#define ID_AA64PFR2_EL1_MTESTOREONLY_SHIFT U(4)
413#define ID_AA64PFR2_EL1_MTESTOREONLY_MASK ULL(0xf)
414
415#define ID_AA64PFR2_EL1_MTEFAR_SHIFT U(8)
416#define ID_AA64PFR2_EL1_MTEFAR_MASK ULL(0xf)
417
Andre Przywara870627e2023-01-27 12:25:49 +0000418#define VDISR_EL2 S3_4_C12_C1_1
419#define VSESR_EL2 S3_4_C5_C2_3
420
Alexei Fedorovaf54f6e2020-12-01 13:22:25 +0000421/* Memory Tagging Extension is not implemented */
422#define MTE_UNIMPLEMENTED U(0)
423/* FEAT_MTE: MTE instructions accessible at EL0 are implemented */
424#define MTE_IMPLEMENTED_EL0 U(1)
425/* FEAT_MTE2: Full MTE is implemented */
426#define MTE_IMPLEMENTED_ELX U(2)
427/*
428 * FEAT_MTE3: MTE is implemented with support for
429 * asymmetric Tag Check Fault handling
430 */
431#define MTE_IMPLEMENTED_ASY U(3)
Soby Mathew830f0ad2019-07-12 09:23:38 +0100432
Alexei Fedorov19933552020-05-26 13:16:41 +0100433#define ID_AA64PFR1_MPAM_FRAC_SHIFT ULL(16)
434#define ID_AA64PFR1_MPAM_FRAC_MASK ULL(0xf)
435
Jayanth Dodderi Chidanand605419a2023-03-06 23:56:14 +0000436#define ID_AA64PFR1_EL1_SME_SHIFT U(24)
437#define ID_AA64PFR1_EL1_SME_MASK ULL(0xf)
438#define ID_AA64PFR1_EL1_SME_NOT_SUPPORTED ULL(0x0)
439#define ID_AA64PFR1_EL1_SME_SUPPORTED ULL(0x1)
Jayanth Dodderi Chidanandcfe053a2022-11-08 10:31:07 +0000440#define ID_AA64PFR1_EL1_SME2_SUPPORTED ULL(0x2)
johpow019baade32021-07-08 14:14:00 -0500441
Achin Gupta4f6ad662013-10-25 09:08:21 +0100442/* ID_PFR1_EL1 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700443#define ID_PFR1_VIRTEXT_SHIFT U(12)
444#define ID_PFR1_VIRTEXT_MASK U(0xf)
Antonio Nino Diaz34235a32018-07-11 16:45:49 +0100445#define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \
Achin Gupta4f6ad662013-10-25 09:08:21 +0100446 & ID_PFR1_VIRTEXT_MASK)
447
448/* SCTLR definitions */
David Cunadofee86532017-04-13 22:38:29 +0100449#define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700450 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
451 (U(1) << 11) | (U(1) << 5) | (U(1) << 4))
Achin Gupta4f6ad662013-10-25 09:08:21 +0100452
John Powella5c66362020-03-20 14:21:05 -0500453#define SCTLR_EL1_RES1 ((UL(1) << 29) | (UL(1) << 28) | (UL(1) << 23) | \
454 (UL(1) << 22) | (UL(1) << 20) | (UL(1) << 11))
Alexei Fedorovc082f032020-11-25 14:07:05 +0000455
Jens Wiklanderc93c9df2014-09-04 10:23:27 +0200456#define SCTLR_AARCH32_EL1_RES1 \
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700457 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \
458 (U(1) << 4) | (U(1) << 3))
Jens Wiklanderc93c9df2014-09-04 10:23:27 +0200459
David Cunadofee86532017-04-13 22:38:29 +0100460#define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
461 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
462 (U(1) << 11) | (U(1) << 5) | (U(1) << 4))
463
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000464#define SCTLR_M_BIT (ULL(1) << 0)
465#define SCTLR_A_BIT (ULL(1) << 1)
466#define SCTLR_C_BIT (ULL(1) << 2)
467#define SCTLR_SA_BIT (ULL(1) << 3)
468#define SCTLR_SA0_BIT (ULL(1) << 4)
469#define SCTLR_CP15BEN_BIT (ULL(1) << 5)
Alexei Fedorovc082f032020-11-25 14:07:05 +0000470#define SCTLR_nAA_BIT (ULL(1) << 6)
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000471#define SCTLR_ITD_BIT (ULL(1) << 7)
472#define SCTLR_SED_BIT (ULL(1) << 8)
473#define SCTLR_UMA_BIT (ULL(1) << 9)
Alexei Fedorovc082f032020-11-25 14:07:05 +0000474#define SCTLR_EnRCTX_BIT (ULL(1) << 10)
475#define SCTLR_EOS_BIT (ULL(1) << 11)
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000476#define SCTLR_I_BIT (ULL(1) << 12)
Alexei Fedorovc31ab382019-07-10 10:49:12 +0100477#define SCTLR_EnDB_BIT (ULL(1) << 13)
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000478#define SCTLR_DZE_BIT (ULL(1) << 14)
479#define SCTLR_UCT_BIT (ULL(1) << 15)
480#define SCTLR_NTWI_BIT (ULL(1) << 16)
481#define SCTLR_NTWE_BIT (ULL(1) << 18)
482#define SCTLR_WXN_BIT (ULL(1) << 19)
Alexei Fedorovc082f032020-11-25 14:07:05 +0000483#define SCTLR_TSCXT_BIT (ULL(1) << 20)
Louis Mayencourt78a0aed2019-02-20 12:11:41 +0000484#define SCTLR_IESB_BIT (ULL(1) << 21)
Alexei Fedorovc082f032020-11-25 14:07:05 +0000485#define SCTLR_EIS_BIT (ULL(1) << 22)
486#define SCTLR_SPAN_BIT (ULL(1) << 23)
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000487#define SCTLR_E0E_BIT (ULL(1) << 24)
488#define SCTLR_EE_BIT (ULL(1) << 25)
489#define SCTLR_UCI_BIT (ULL(1) << 26)
Alexei Fedorovc31ab382019-07-10 10:49:12 +0100490#define SCTLR_EnDA_BIT (ULL(1) << 27)
Alexei Fedorovc082f032020-11-25 14:07:05 +0000491#define SCTLR_nTLSMD_BIT (ULL(1) << 28)
492#define SCTLR_LSMAOE_BIT (ULL(1) << 29)
Alexei Fedorovc31ab382019-07-10 10:49:12 +0100493#define SCTLR_EnIB_BIT (ULL(1) << 30)
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000494#define SCTLR_EnIA_BIT (ULL(1) << 31)
Alexei Fedorov90f2e882019-05-24 12:17:09 +0100495#define SCTLR_BT0_BIT (ULL(1) << 35)
496#define SCTLR_BT1_BIT (ULL(1) << 36)
497#define SCTLR_BT_BIT (ULL(1) << 36)
Alexei Fedorovc082f032020-11-25 14:07:05 +0000498#define SCTLR_ITFSB_BIT (ULL(1) << 37)
499#define SCTLR_TCF0_SHIFT U(38)
500#define SCTLR_TCF0_MASK ULL(3)
johpow019baade32021-07-08 14:14:00 -0500501#define SCTLR_ENTP2_BIT (ULL(1) << 60)
Alexei Fedorovc082f032020-11-25 14:07:05 +0000502
503/* Tag Check Faults in EL0 have no effect on the PE */
504#define SCTLR_TCF0_NO_EFFECT U(0)
505/* Tag Check Faults in EL0 cause a synchronous exception */
506#define SCTLR_TCF0_SYNC U(1)
507/* Tag Check Faults in EL0 are asynchronously accumulated */
508#define SCTLR_TCF0_ASYNC U(2)
509/*
510 * Tag Check Faults in EL0 cause a synchronous exception on reads,
511 * and are asynchronously accumulated on writes
512 */
513#define SCTLR_TCF0_SYNCR_ASYNCW U(3)
514
515#define SCTLR_TCF_SHIFT U(40)
516#define SCTLR_TCF_MASK ULL(3)
517
518/* Tag Check Faults in EL1 have no effect on the PE */
519#define SCTLR_TCF_NO_EFFECT U(0)
520/* Tag Check Faults in EL1 cause a synchronous exception */
521#define SCTLR_TCF_SYNC U(1)
522/* Tag Check Faults in EL1 are asynchronously accumulated */
523#define SCTLR_TCF_ASYNC U(2)
524/*
525 * Tag Check Faults in EL1 cause a synchronous exception on reads,
526 * and are asynchronously accumulated on writes
527 */
528#define SCTLR_TCF_SYNCR_ASYNCW U(3)
529
530#define SCTLR_ATA0_BIT (ULL(1) << 42)
531#define SCTLR_ATA_BIT (ULL(1) << 43)
Daniel Boulby44b43332020-11-25 16:36:46 +0000532#define SCTLR_DSSBS_SHIFT U(44)
533#define SCTLR_DSSBS_BIT (ULL(1) << SCTLR_DSSBS_SHIFT)
Alexei Fedorovc082f032020-11-25 14:07:05 +0000534#define SCTLR_TWEDEn_BIT (ULL(1) << 45)
535#define SCTLR_TWEDEL_SHIFT U(46)
536#define SCTLR_TWEDEL_MASK ULL(0xf)
537#define SCTLR_EnASR_BIT (ULL(1) << 54)
538#define SCTLR_EnAS0_BIT (ULL(1) << 55)
539#define SCTLR_EnALS_BIT (ULL(1) << 56)
540#define SCTLR_EPAN_BIT (ULL(1) << 57)
David Cunadofee86532017-04-13 22:38:29 +0100541#define SCTLR_RESET_VAL SCTLR_EL3_RES1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100542
Alexei Fedorovc082f032020-11-25 14:07:05 +0000543/* CPACR_EL1 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700544#define CPACR_EL1_FPEN(x) ((x) << 20)
Jimmy Brissoned202072020-08-04 16:18:52 -0500545#define CPACR_EL1_FP_TRAP_EL0 UL(0x1)
546#define CPACR_EL1_FP_TRAP_ALL UL(0x2)
547#define CPACR_EL1_FP_TRAP_NONE UL(0x3)
Jayanth Dodderi Chidanandcfe053a2022-11-08 10:31:07 +0000548#define CPACR_EL1_SMEN_SHIFT U(24)
549#define CPACR_EL1_SMEN_MASK ULL(0x3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100550
551/* SCR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700552#define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5))
Zelalem Aweke79e3d292021-07-08 16:51:14 -0500553#define SCR_NSE_SHIFT U(62)
554#define SCR_NSE_BIT (ULL(1) << SCR_NSE_SHIFT)
555#define SCR_GPF_BIT (UL(1) << 48)
johpow013e24c162020-04-22 14:05:13 -0500556#define SCR_TWEDEL_SHIFT U(30)
557#define SCR_TWEDEL_MASK ULL(0xf)
Mark Brown293a6612023-03-14 20:48:43 +0000558#define SCR_PIEN_BIT (UL(1) << 45)
Mark Brownc37eee72023-03-14 20:13:03 +0000559#define SCR_TCR2EN_BIT (UL(1) << 43)
Juan Pablo Conde42305f22022-07-12 16:40:29 -0400560#define SCR_TRNDR_BIT (UL(1) << 40)
Mark Brown326f2952023-03-14 21:33:04 +0000561#define SCR_GCSEn_BIT (UL(1) << 39)
johpow019baade32021-07-08 14:14:00 -0500562#define SCR_HXEn_BIT (UL(1) << 38)
563#define SCR_ENTP2_SHIFT U(41)
564#define SCR_ENTP2_BIT (UL(1) << SCR_ENTP2_SHIFT)
John Powellcc799272022-03-29 00:25:59 -0500565#define SCR_AMVOFFEN_SHIFT U(35)
566#define SCR_AMVOFFEN_BIT (UL(1) << SCR_AMVOFFEN_SHIFT)
johpow013e24c162020-04-22 14:05:13 -0500567#define SCR_TWEDEn_BIT (UL(1) << 29)
johpow01fa59c6f2020-10-02 13:41:11 -0500568#define SCR_ECVEN_BIT (UL(1) << 28)
569#define SCR_FGTEN_BIT (UL(1) << 27)
Jimmy Brissoned202072020-08-04 16:18:52 -0500570#define SCR_ATA_BIT (UL(1) << 26)
Zelalem Aweke13dc8f12021-07-09 14:20:03 -0500571#define SCR_EnSCXT_BIT (UL(1) << 25)
Jimmy Brissoned202072020-08-04 16:18:52 -0500572#define SCR_FIEN_BIT (UL(1) << 21)
573#define SCR_EEL2_BIT (UL(1) << 18)
574#define SCR_API_BIT (UL(1) << 17)
575#define SCR_APK_BIT (UL(1) << 16)
576#define SCR_TERR_BIT (UL(1) << 15)
577#define SCR_TWE_BIT (UL(1) << 13)
578#define SCR_TWI_BIT (UL(1) << 12)
579#define SCR_ST_BIT (UL(1) << 11)
580#define SCR_RW_BIT (UL(1) << 10)
581#define SCR_SIF_BIT (UL(1) << 9)
582#define SCR_HCE_BIT (UL(1) << 8)
583#define SCR_SMD_BIT (UL(1) << 7)
584#define SCR_EA_BIT (UL(1) << 3)
585#define SCR_FIQ_BIT (UL(1) << 2)
586#define SCR_IRQ_BIT (UL(1) << 1)
587#define SCR_NS_BIT (UL(1) << 0)
johpow019baade32021-07-08 14:14:00 -0500588#define SCR_VALID_BIT_MASK U(0x24000002F8F)
David Cunadofee86532017-04-13 22:38:29 +0100589#define SCR_RESET_VAL SCR_RES1_BITS
Achin Gupta4f6ad662013-10-25 09:08:21 +0100590
David Cunadofee86532017-04-13 22:38:29 +0100591/* MDCR_EL3 definitions */
Alexei Fedorov307f34b2021-05-14 11:21:56 +0100592#define MDCR_EnPMSN_BIT (ULL(1) << 36)
593#define MDCR_MPMX_BIT (ULL(1) << 35)
594#define MDCR_MCCD_BIT (ULL(1) << 34)
johpow0181865962022-01-28 17:06:20 -0600595#define MDCR_SBRBE_SHIFT U(32)
596#define MDCR_SBRBE_MASK ULL(0x3)
Manish V Badarkhee1cccb42021-06-23 20:02:39 +0100597#define MDCR_NSTB(x) ((x) << 24)
598#define MDCR_NSTB_EL1 ULL(0x3)
Boyan Karatotev919d3c82023-02-13 16:32:47 +0000599#define MDCR_NSTBE_BIT (ULL(1) << 26)
Javier Almansa Sobrinof3a4c542020-11-23 18:38:15 +0000600#define MDCR_MTPME_BIT (ULL(1) << 28)
Alexei Fedorov307f34b2021-05-14 11:21:56 +0100601#define MDCR_TDCC_BIT (ULL(1) << 27)
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100602#define MDCR_SCCD_BIT (ULL(1) << 23)
Alexei Fedorov307f34b2021-05-14 11:21:56 +0100603#define MDCR_EPMAD_BIT (ULL(1) << 21)
604#define MDCR_EDAD_BIT (ULL(1) << 20)
605#define MDCR_TTRF_BIT (ULL(1) << 19)
606#define MDCR_STE_BIT (ULL(1) << 18)
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100607#define MDCR_SPME_BIT (ULL(1) << 17)
608#define MDCR_SDD_BIT (ULL(1) << 16)
dp-arm595d0d52017-02-08 11:51:50 +0000609#define MDCR_SPD32(x) ((x) << 14)
Antonio Nino Diaz3fbd3f52019-02-18 16:55:43 +0000610#define MDCR_SPD32_LEGACY ULL(0x0)
611#define MDCR_SPD32_DISABLE ULL(0x2)
612#define MDCR_SPD32_ENABLE ULL(0x3)
dp-armee3457b2017-05-23 09:32:49 +0100613#define MDCR_NSPB(x) ((x) << 12)
Antonio Nino Diaz3fbd3f52019-02-18 16:55:43 +0000614#define MDCR_NSPB_EL1 ULL(0x3)
Boyan Karatotev6e2fd8b2023-02-13 16:38:37 +0000615#define MDCR_NSPBE_BIT (ULL(1) << 11)
Antonio Nino Diaz3fbd3f52019-02-18 16:55:43 +0000616#define MDCR_TDOSA_BIT (ULL(1) << 10)
617#define MDCR_TDA_BIT (ULL(1) << 9)
618#define MDCR_TPM_BIT (ULL(1) << 6)
Boyan Karatotevb7e74432023-06-15 14:46:20 +0100619#define MDCR_EL3_RESET_VAL MDCR_MTPME_BIT
dp-arm595d0d52017-02-08 11:51:50 +0000620
David Cunadofee86532017-04-13 22:38:29 +0100621/* MDCR_EL2 definitions */
Javier Almansa Sobrinof3a4c542020-11-23 18:38:15 +0000622#define MDCR_EL2_MTPME (U(1) << 28)
Boyan Karatotev05504ba2023-02-15 13:21:50 +0000623#define MDCR_EL2_HLP_BIT (U(1) << 26)
Manish V Badarkhee1cccb42021-06-23 20:02:39 +0100624#define MDCR_EL2_E2TB(x) ((x) << 24)
625#define MDCR_EL2_E2TB_EL1 U(0x3)
Boyan Karatotev05504ba2023-02-15 13:21:50 +0000626#define MDCR_EL2_HCCD_BIT (U(1) << 23)
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100627#define MDCR_EL2_TTRF (U(1) << 19)
Boyan Karatotev05504ba2023-02-15 13:21:50 +0000628#define MDCR_EL2_HPMD_BIT (U(1) << 17)
dp-armee3457b2017-05-23 09:32:49 +0100629#define MDCR_EL2_TPMS (U(1) << 14)
630#define MDCR_EL2_E2PB(x) ((x) << 12)
631#define MDCR_EL2_E2PB_EL1 U(0x3)
David Cunadofee86532017-04-13 22:38:29 +0100632#define MDCR_EL2_TDRA_BIT (U(1) << 11)
633#define MDCR_EL2_TDOSA_BIT (U(1) << 10)
634#define MDCR_EL2_TDA_BIT (U(1) << 9)
635#define MDCR_EL2_TDE_BIT (U(1) << 8)
636#define MDCR_EL2_HPME_BIT (U(1) << 7)
637#define MDCR_EL2_TPM_BIT (U(1) << 6)
638#define MDCR_EL2_TPMCR_BIT (U(1) << 5)
Boyan Karatotev05504ba2023-02-15 13:21:50 +0000639#define MDCR_EL2_HPMN_MASK U(0x1f)
David Cunadofee86532017-04-13 22:38:29 +0100640#define MDCR_EL2_RESET_VAL U(0x0)
641
642/* HSTR_EL2 definitions */
643#define HSTR_EL2_RESET_VAL U(0x0)
644#define HSTR_EL2_T_MASK U(0xff)
645
646/* CNTHP_CTL_EL2 definitions */
647#define CNTHP_CTL_ENABLE_BIT (U(1) << 0)
648#define CNTHP_CTL_RESET_VAL U(0x0)
649
650/* VTTBR_EL2 definitions */
651#define VTTBR_RESET_VAL ULL(0x0)
652#define VTTBR_VMID_MASK ULL(0xff)
653#define VTTBR_VMID_SHIFT U(48)
654#define VTTBR_BADDR_MASK ULL(0xffffffffffff)
655#define VTTBR_BADDR_SHIFT U(0)
dp-arm595d0d52017-02-08 11:51:50 +0000656
Achin Gupta4f6ad662013-10-25 09:08:21 +0100657/* HCR definitions */
Gary Morrison3d7f6542021-01-27 13:08:47 -0600658#define HCR_RESET_VAL ULL(0x0)
Chris Kaya5fde282021-05-26 11:58:23 +0100659#define HCR_AMVOFFEN_SHIFT U(51)
660#define HCR_AMVOFFEN_BIT (ULL(1) << HCR_AMVOFFEN_SHIFT)
Gary Morrison3d7f6542021-01-27 13:08:47 -0600661#define HCR_TEA_BIT (ULL(1) << 47)
Jeenu Viswambharancbad6612018-08-15 14:29:29 +0100662#define HCR_API_BIT (ULL(1) << 41)
663#define HCR_APK_BIT (ULL(1) << 40)
Manish V Badarkhe2801ed42020-04-28 04:53:32 +0100664#define HCR_E2H_BIT (ULL(1) << 34)
Gary Morrison3d7f6542021-01-27 13:08:47 -0600665#define HCR_HCD_BIT (ULL(1) << 29)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000666#define HCR_TGE_BIT (ULL(1) << 27)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700667#define HCR_RW_SHIFT U(31)
668#define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT)
Gary Morrison3d7f6542021-01-27 13:08:47 -0600669#define HCR_TWE_BIT (ULL(1) << 14)
670#define HCR_TWI_BIT (ULL(1) << 13)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100671#define HCR_AMO_BIT (ULL(1) << 5)
672#define HCR_IMO_BIT (ULL(1) << 4)
673#define HCR_FMO_BIT (ULL(1) << 3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100674
Gerald Lejeune851dc7e2016-03-22 11:11:46 +0100675/* ISR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700676#define ISR_A_SHIFT U(8)
677#define ISR_I_SHIFT U(7)
678#define ISR_F_SHIFT U(6)
Gerald Lejeune851dc7e2016-03-22 11:11:46 +0100679
Achin Gupta4f6ad662013-10-25 09:08:21 +0100680/* CNTHCTL_EL2 definitions */
David Cunadofee86532017-04-13 22:38:29 +0100681#define CNTHCTL_RESET_VAL U(0x0)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700682#define EVNTEN_BIT (U(1) << 2)
683#define EL1PCEN_BIT (U(1) << 1)
684#define EL1PCTEN_BIT (U(1) << 0)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100685
686/* CNTKCTL_EL1 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700687#define EL0PTEN_BIT (U(1) << 9)
688#define EL0VTEN_BIT (U(1) << 8)
689#define EL0PCTEN_BIT (U(1) << 0)
690#define EL0VCTEN_BIT (U(1) << 1)
691#define EVNTEN_BIT (U(1) << 2)
692#define EVNTDIR_BIT (U(1) << 3)
693#define EVNTI_SHIFT U(4)
694#define EVNTI_MASK U(0xf)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100695
696/* CPTR_EL3 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700697#define TCPAC_BIT (U(1) << 31)
Chris Kaya5fde282021-05-26 11:58:23 +0100698#define TAM_SHIFT U(30)
699#define TAM_BIT (U(1) << TAM_SHIFT)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700700#define TTA_BIT (U(1) << 20)
johpow019baade32021-07-08 14:14:00 -0500701#define ESM_BIT (U(1) << 12)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700702#define TFP_BIT (U(1) << 10)
David Cunadoce88eee2017-10-20 11:30:57 +0100703#define CPTR_EZ_BIT (U(1) << 8)
johpow019baade32021-07-08 14:14:00 -0500704#define CPTR_EL3_RESET_VAL ((TCPAC_BIT | TAM_BIT | TTA_BIT | TFP_BIT) & \
705 ~(CPTR_EZ_BIT | ESM_BIT))
David Cunadofee86532017-04-13 22:38:29 +0100706
707/* CPTR_EL2 definitions */
708#define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff)))
709#define CPTR_EL2_TCPAC_BIT (U(1) << 31)
Chris Kaya5fde282021-05-26 11:58:23 +0100710#define CPTR_EL2_TAM_SHIFT U(30)
711#define CPTR_EL2_TAM_BIT (U(1) << CPTR_EL2_TAM_SHIFT)
johpow019baade32021-07-08 14:14:00 -0500712#define CPTR_EL2_SMEN_MASK ULL(0x3)
713#define CPTR_EL2_SMEN_SHIFT U(24)
David Cunadofee86532017-04-13 22:38:29 +0100714#define CPTR_EL2_TTA_BIT (U(1) << 20)
johpow019baade32021-07-08 14:14:00 -0500715#define CPTR_EL2_TSM_BIT (U(1) << 12)
David Cunadofee86532017-04-13 22:38:29 +0100716#define CPTR_EL2_TFP_BIT (U(1) << 10)
David Cunadoce88eee2017-10-20 11:30:57 +0100717#define CPTR_EL2_TZ_BIT (U(1) << 8)
David Cunadofee86532017-04-13 22:38:29 +0100718#define CPTR_EL2_RESET_VAL CPTR_EL2_RES1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100719
Manish Pandey5693afe2021-10-06 17:28:09 +0100720/* VTCR_EL2 definitions */
johpow019baade32021-07-08 14:14:00 -0500721#define VTCR_RESET_VAL U(0x0)
722#define VTCR_EL2_MSA (U(1) << 31)
Manish Pandey5693afe2021-10-06 17:28:09 +0100723
Achin Gupta4f6ad662013-10-25 09:08:21 +0100724/* CPSR/SPSR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700725#define DAIF_FIQ_BIT (U(1) << 0)
726#define DAIF_IRQ_BIT (U(1) << 1)
727#define DAIF_ABT_BIT (U(1) << 2)
728#define DAIF_DBG_BIT (U(1) << 3)
729#define SPSR_DAIF_SHIFT U(6)
730#define SPSR_DAIF_MASK U(0xf)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100731
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700732#define SPSR_AIF_SHIFT U(6)
733#define SPSR_AIF_MASK U(0x7)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100734
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700735#define SPSR_E_SHIFT U(9)
736#define SPSR_E_MASK U(0x1)
737#define SPSR_E_LITTLE U(0x0)
738#define SPSR_E_BIG U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100739
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700740#define SPSR_T_SHIFT U(5)
741#define SPSR_T_MASK U(0x1)
742#define SPSR_T_ARM U(0x0)
743#define SPSR_T_THUMB U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100744
Dimitris Papastamosc52ebdc2017-12-18 13:46:21 +0000745#define SPSR_M_SHIFT U(4)
746#define SPSR_M_MASK U(0x1)
747#define SPSR_M_AARCH64 U(0x0)
748#define SPSR_M_AARCH32 U(0x1)
Zelalem Aweke13dc8f12021-07-09 14:20:03 -0500749#define SPSR_M_EL2H U(0x9)
Dimitris Papastamosc52ebdc2017-12-18 13:46:21 +0000750
Alexei Fedorov813c9f92020-03-03 13:31:58 +0000751#define SPSR_EL_SHIFT U(2)
752#define SPSR_EL_WIDTH U(2)
753
Daniel Boulby44b43332020-11-25 16:36:46 +0000754#define SPSR_SSBS_SHIFT_AARCH64 U(12)
755#define SPSR_SSBS_BIT_AARCH64 (ULL(1) << SPSR_SSBS_SHIFT_AARCH64)
756#define SPSR_SSBS_SHIFT_AARCH32 U(23)
757#define SPSR_SSBS_BIT_AARCH32 (ULL(1) << SPSR_SSBS_SHIFT_AARCH32)
758
759#define SPSR_PAN_BIT BIT_64(22)
760
761#define SPSR_DIT_BIT BIT(24)
762
763#define SPSR_TCO_BIT_AARCH64 BIT_64(25)
John Tsichritzis55534172019-07-23 11:12:41 +0100764
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100765#define DISABLE_ALL_EXCEPTIONS \
766 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT)
767
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000768#define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT)
769
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000770/*
771 * RMR_EL3 definitions
772 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700773#define RMR_EL3_RR_BIT (U(1) << 1)
774#define RMR_EL3_AA64_BIT (U(1) << 0)
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000775
776/*
777 * HI-VECTOR address for AArch32 state
778 */
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000779#define HI_VECTOR_BASE U(0xFFFF0000)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100780
781/*
Elyes Haouas2be03c02023-02-13 09:14:48 +0100782 * TCR definitions
Achin Gupta4f6ad662013-10-25 09:08:21 +0100783 */
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000784#define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23))
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100785#define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23))
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700786#define TCR_EL1_IPS_SHIFT U(32)
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100787#define TCR_EL2_PS_SHIFT U(16)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700788#define TCR_EL3_PS_SHIFT U(16)
Lin Ma741a3822014-06-27 16:56:30 -0700789
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100790#define TCR_TxSZ_MIN ULL(16)
791#define TCR_TxSZ_MAX ULL(39)
Sathees Balya74155972019-01-25 11:36:01 +0000792#define TCR_TxSZ_MAX_TTST ULL(48)
Antonio Nino Diazd48ae612016-08-02 09:21:41 +0100793
Antonio Nino Diaz37f97a52019-03-27 11:10:31 +0000794#define TCR_T0SZ_SHIFT U(0)
795#define TCR_T1SZ_SHIFT U(16)
796
Lin Ma741a3822014-06-27 16:56:30 -0700797/* (internal) physical address size bits in EL3/EL1 */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100798#define TCR_PS_BITS_4GB ULL(0x0)
799#define TCR_PS_BITS_64GB ULL(0x1)
800#define TCR_PS_BITS_1TB ULL(0x2)
801#define TCR_PS_BITS_4TB ULL(0x3)
802#define TCR_PS_BITS_16TB ULL(0x4)
803#define TCR_PS_BITS_256TB ULL(0x5)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100804
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700805#define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000)
806#define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000)
807#define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000)
808#define ADDR_MASK_40_TO_41 ULL(0x0000030000000000)
809#define ADDR_MASK_36_TO_39 ULL(0x000000F000000000)
810#define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100811
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100812#define TCR_RGN_INNER_NC (ULL(0x0) << 8)
813#define TCR_RGN_INNER_WBA (ULL(0x1) << 8)
814#define TCR_RGN_INNER_WT (ULL(0x2) << 8)
815#define TCR_RGN_INNER_WBNA (ULL(0x3) << 8)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100816
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100817#define TCR_RGN_OUTER_NC (ULL(0x0) << 10)
818#define TCR_RGN_OUTER_WBA (ULL(0x1) << 10)
819#define TCR_RGN_OUTER_WT (ULL(0x2) << 10)
820#define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100821
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100822#define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12)
823#define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12)
824#define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100825
Antonio Nino Diaz37f97a52019-03-27 11:10:31 +0000826#define TCR_RGN1_INNER_NC (ULL(0x0) << 24)
827#define TCR_RGN1_INNER_WBA (ULL(0x1) << 24)
828#define TCR_RGN1_INNER_WT (ULL(0x2) << 24)
829#define TCR_RGN1_INNER_WBNA (ULL(0x3) << 24)
830
831#define TCR_RGN1_OUTER_NC (ULL(0x0) << 26)
832#define TCR_RGN1_OUTER_WBA (ULL(0x1) << 26)
833#define TCR_RGN1_OUTER_WT (ULL(0x2) << 26)
834#define TCR_RGN1_OUTER_WBNA (ULL(0x3) << 26)
835
836#define TCR_SH1_NON_SHAREABLE (ULL(0x0) << 28)
837#define TCR_SH1_OUTER_SHAREABLE (ULL(0x2) << 28)
838#define TCR_SH1_INNER_SHAREABLE (ULL(0x3) << 28)
839
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100840#define TCR_TG0_SHIFT U(14)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100841#define TCR_TG0_MASK ULL(3)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100842#define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT)
843#define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT)
844#define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT)
845
Antonio Nino Diaz37f97a52019-03-27 11:10:31 +0000846#define TCR_TG1_SHIFT U(30)
847#define TCR_TG1_MASK ULL(3)
848#define TCR_TG1_16K (ULL(1) << TCR_TG1_SHIFT)
849#define TCR_TG1_4K (ULL(2) << TCR_TG1_SHIFT)
850#define TCR_TG1_64K (ULL(3) << TCR_TG1_SHIFT)
851
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100852#define TCR_EPD0_BIT (ULL(1) << 7)
853#define TCR_EPD1_BIT (ULL(1) << 23)
Antonio Nino Diazc8274a82017-09-15 10:30:34 +0100854
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700855#define MODE_SP_SHIFT U(0x0)
856#define MODE_SP_MASK U(0x1)
857#define MODE_SP_EL0 U(0x0)
858#define MODE_SP_ELX U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100859
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700860#define MODE_RW_SHIFT U(0x4)
861#define MODE_RW_MASK U(0x1)
862#define MODE_RW_64 U(0x0)
863#define MODE_RW_32 U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100864
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700865#define MODE_EL_SHIFT U(0x2)
866#define MODE_EL_MASK U(0x3)
Alexei Fedorov813c9f92020-03-03 13:31:58 +0000867#define MODE_EL_WIDTH U(0x2)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700868#define MODE_EL3 U(0x3)
869#define MODE_EL2 U(0x2)
870#define MODE_EL1 U(0x1)
871#define MODE_EL0 U(0x0)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100872
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700873#define MODE32_SHIFT U(0)
874#define MODE32_MASK U(0xf)
875#define MODE32_usr U(0x0)
876#define MODE32_fiq U(0x1)
877#define MODE32_irq U(0x2)
878#define MODE32_svc U(0x3)
879#define MODE32_mon U(0x6)
880#define MODE32_abt U(0x7)
881#define MODE32_hyp U(0xa)
882#define MODE32_und U(0xb)
883#define MODE32_sys U(0xf)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100884
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100885#define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK)
886#define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK)
887#define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK)
888#define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100889
John Tsichritzis55534172019-07-23 11:12:41 +0100890#define SPSR_64(el, sp, daif) \
891 (((MODE_RW_64 << MODE_RW_SHIFT) | \
892 (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \
893 (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \
894 (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) & \
895 (~(SPSR_SSBS_BIT_AARCH64)))
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100896
897#define SPSR_MODE32(mode, isa, endian, aif) \
John Tsichritzis55534172019-07-23 11:12:41 +0100898 (((MODE_RW_32 << MODE_RW_SHIFT) | \
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700899 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \
900 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \
901 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \
John Tsichritzis55534172019-07-23 11:12:41 +0100902 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) & \
903 (~(SPSR_SSBS_BIT_AARCH32)))
Achin Gupta4f6ad662013-10-25 09:08:21 +0100904
Dan Handley0cdebbd2015-03-30 17:15:16 +0100905/*
Isla Mitchellc4a1a072017-08-07 11:20:13 +0100906 * TTBR Definitions
907 */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100908#define TTBR_CNP_BIT ULL(0x1)
Isla Mitchellc4a1a072017-08-07 11:20:13 +0100909
910/*
Dan Handley0cdebbd2015-03-30 17:15:16 +0100911 * CTR_EL0 definitions
912 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700913#define CTR_CWG_SHIFT U(24)
914#define CTR_CWG_MASK U(0xf)
915#define CTR_ERG_SHIFT U(20)
916#define CTR_ERG_MASK U(0xf)
917#define CTR_DMINLINE_SHIFT U(16)
918#define CTR_DMINLINE_MASK U(0xf)
919#define CTR_L1IP_SHIFT U(14)
920#define CTR_L1IP_MASK U(0x3)
921#define CTR_IMINLINE_SHIFT U(0)
922#define CTR_IMINLINE_MASK U(0xf)
Dan Handley0cdebbd2015-03-30 17:15:16 +0100923
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700924#define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100925
Achin Gupta405406d2014-05-09 12:00:17 +0100926/* Physical timer control register bit fields shifts and masks */
johpow01fa59c6f2020-10-02 13:41:11 -0500927#define CNTP_CTL_ENABLE_SHIFT U(0)
928#define CNTP_CTL_IMASK_SHIFT U(1)
929#define CNTP_CTL_ISTATUS_SHIFT U(2)
Achin Gupta405406d2014-05-09 12:00:17 +0100930
johpow01fa59c6f2020-10-02 13:41:11 -0500931#define CNTP_CTL_ENABLE_MASK U(1)
932#define CNTP_CTL_IMASK_MASK U(1)
933#define CNTP_CTL_ISTATUS_MASK U(1)
Achin Gupta405406d2014-05-09 12:00:17 +0100934
Varun Wadekar787a1292018-06-18 16:15:51 -0700935/* Physical timer control macros */
936#define CNTP_CTL_ENABLE_BIT (U(1) << CNTP_CTL_ENABLE_SHIFT)
937#define CNTP_CTL_IMASK_BIT (U(1) << CNTP_CTL_IMASK_SHIFT)
938
Achin Gupta4f6ad662013-10-25 09:08:21 +0100939/* Exception Syndrome register bits and bobs */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700940#define ESR_EC_SHIFT U(26)
941#define ESR_EC_MASK U(0x3f)
942#define ESR_EC_LENGTH U(6)
Justin Chadwell83e04882019-08-20 11:01:52 +0100943#define ESR_ISS_SHIFT U(0)
944#define ESR_ISS_LENGTH U(25)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700945#define EC_UNKNOWN U(0x0)
946#define EC_WFE_WFI U(0x1)
947#define EC_AARCH32_CP15_MRC_MCR U(0x3)
948#define EC_AARCH32_CP15_MRRC_MCRR U(0x4)
949#define EC_AARCH32_CP14_MRC_MCR U(0x5)
950#define EC_AARCH32_CP14_LDC_STC U(0x6)
951#define EC_FP_SIMD U(0x7)
952#define EC_AARCH32_CP10_MRC U(0x8)
953#define EC_AARCH32_CP14_MRRC_MCRR U(0xc)
954#define EC_ILLEGAL U(0xe)
955#define EC_AARCH32_SVC U(0x11)
956#define EC_AARCH32_HVC U(0x12)
957#define EC_AARCH32_SMC U(0x13)
958#define EC_AARCH64_SVC U(0x15)
959#define EC_AARCH64_HVC U(0x16)
960#define EC_AARCH64_SMC U(0x17)
961#define EC_AARCH64_SYS U(0x18)
962#define EC_IABORT_LOWER_EL U(0x20)
963#define EC_IABORT_CUR_EL U(0x21)
964#define EC_PC_ALIGN U(0x22)
965#define EC_DABORT_LOWER_EL U(0x24)
966#define EC_DABORT_CUR_EL U(0x25)
967#define EC_SP_ALIGN U(0x26)
968#define EC_AARCH32_FP U(0x28)
969#define EC_AARCH64_FP U(0x2c)
970#define EC_SERROR U(0x2f)
Justin Chadwell83e04882019-08-20 11:01:52 +0100971#define EC_BRK U(0x3c)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100972
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +0000973/*
974 * External Abort bit in Instruction and Data Aborts synchronous exception
975 * syndromes.
976 */
977#define ESR_ISS_EABORT_EA_BIT U(9)
978
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700979#define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100980
Vignesh Radhakrishnanb4a72942017-03-03 10:58:05 -0800981/* Reset bit inside the Reset management register for EL3 (RMR_EL3) */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700982#define RMR_RESET_REQUEST_SHIFT U(0x1)
983#define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT)
Vignesh Radhakrishnanb4a72942017-03-03 10:58:05 -0800984
Dan Handleyed6ff952014-05-14 17:44:19 +0100985/*******************************************************************************
Antonio Nino Diazac998032017-02-27 17:23:54 +0000986 * Definitions of register offsets, fields and macros for CPU system
987 * instructions.
988 ******************************************************************************/
989
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700990#define TLBI_ADDR_SHIFT U(12)
Antonio Nino Diazac998032017-02-27 17:23:54 +0000991#define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF)
992#define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK)
993
994/*******************************************************************************
Dan Handleyed6ff952014-05-14 17:44:19 +0100995 * Definitions of register offsets and fields in the CNTCTLBase Frame of the
996 * system level implementation of the Generic Timer.
997 ******************************************************************************/
Soby Mathew2d9f7952018-06-11 16:21:30 +0100998#define CNTCTLBASE_CNTFRQ U(0x0)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700999#define CNTNSAR U(0x4)
1000#define CNTNSAR_NS_SHIFT(x) (x)
Dan Handleyed6ff952014-05-14 17:44:19 +01001001
Varun Wadekarc6a11f62017-05-25 18:04:48 -07001002#define CNTACR_BASE(x) (U(0x40) + ((x) << 2))
1003#define CNTACR_RPCT_SHIFT U(0x0)
1004#define CNTACR_RVCT_SHIFT U(0x1)
1005#define CNTACR_RFRQ_SHIFT U(0x2)
1006#define CNTACR_RVOFF_SHIFT U(0x3)
1007#define CNTACR_RWVT_SHIFT U(0x4)
1008#define CNTACR_RWPT_SHIFT U(0x5)
Dan Handleyed6ff952014-05-14 17:44:19 +01001009
Soby Mathew2d9f7952018-06-11 16:21:30 +01001010/*******************************************************************************
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +00001011 * Definitions of register offsets and fields in the CNTBaseN Frame of the
Soby Mathew2d9f7952018-06-11 16:21:30 +01001012 * system level implementation of the Generic Timer.
1013 ******************************************************************************/
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +00001014/* Physical Count register. */
1015#define CNTPCT_LO U(0x0)
1016/* Counter Frequency register. */
1017#define CNTBASEN_CNTFRQ U(0x10)
1018/* Physical Timer CompareValue register. */
1019#define CNTP_CVAL_LO U(0x20)
1020/* Physical Timer Control register. */
1021#define CNTP_CTL U(0x2c)
Soby Mathew2d9f7952018-06-11 16:21:30 +01001022
David Cunado5f55e282016-10-31 17:37:34 +00001023/* PMCR_EL0 definitions */
David Cunado4168f2f2017-10-02 17:41:39 +01001024#define PMCR_EL0_RESET_VAL U(0x0)
Varun Wadekarc6a11f62017-05-25 18:04:48 -07001025#define PMCR_EL0_N_SHIFT U(11)
1026#define PMCR_EL0_N_MASK U(0x1f)
David Cunado5f55e282016-10-31 17:37:34 +00001027#define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT)
Alexei Fedorov503bbf32019-08-13 15:17:53 +01001028#define PMCR_EL0_LP_BIT (U(1) << 7)
David Cunado4168f2f2017-10-02 17:41:39 +01001029#define PMCR_EL0_LC_BIT (U(1) << 6)
1030#define PMCR_EL0_DP_BIT (U(1) << 5)
1031#define PMCR_EL0_X_BIT (U(1) << 4)
1032#define PMCR_EL0_D_BIT (U(1) << 3)
Alexei Fedorov503bbf32019-08-13 15:17:53 +01001033#define PMCR_EL0_C_BIT (U(1) << 2)
1034#define PMCR_EL0_P_BIT (U(1) << 1)
1035#define PMCR_EL0_E_BIT (U(1) << 0)
David Cunado5f55e282016-10-31 17:37:34 +00001036
Isla Mitchell02c63072017-07-21 14:44:36 +01001037/*******************************************************************************
David Cunadoce88eee2017-10-20 11:30:57 +01001038 * Definitions for system register interface to SVE
1039 ******************************************************************************/
1040#define ZCR_EL3 S3_6_C1_C2_0
1041#define ZCR_EL2 S3_4_C1_C2_0
1042
1043/* ZCR_EL3 definitions */
1044#define ZCR_EL3_LEN_MASK U(0xf)
1045
1046/* ZCR_EL2 definitions */
1047#define ZCR_EL2_LEN_MASK U(0xf)
1048
1049/*******************************************************************************
johpow019baade32021-07-08 14:14:00 -05001050 * Definitions for system register interface to SME as needed in EL3
1051 ******************************************************************************/
1052#define ID_AA64SMFR0_EL1 S3_0_C0_C4_5
1053#define SMCR_EL3 S3_6_C1_C2_6
1054
1055/* ID_AA64SMFR0_EL1 definitions */
Jayanth Dodderi Chidanand605419a2023-03-06 23:56:14 +00001056#define ID_AA64SMFR0_EL1_SME_FA64_SHIFT U(63)
1057#define ID_AA64SMFR0_EL1_SME_FA64_MASK U(0x1)
1058#define ID_AA64SMFR0_EL1_SME_FA64_SUPPORTED U(0x1)
Jayanth Dodderi Chidanandcfe053a2022-11-08 10:31:07 +00001059#define ID_AA64SMFR0_EL1_SME_VER_SHIFT U(55)
1060#define ID_AA64SMFR0_EL1_SME_VER_MASK ULL(0xf)
1061#define ID_AA64SMFR0_EL1_SME_INST_SUPPORTED ULL(0x0)
1062#define ID_AA64SMFR0_EL1_SME2_INST_SUPPORTED ULL(0x1)
johpow019baade32021-07-08 14:14:00 -05001063
1064/* SMCR_ELx definitions */
1065#define SMCR_ELX_LEN_SHIFT U(0)
Jayanth Dodderi Chidanandcfe053a2022-11-08 10:31:07 +00001066#define SMCR_ELX_LEN_MAX U(0x1ff)
johpow019baade32021-07-08 14:14:00 -05001067#define SMCR_ELX_FA64_BIT (U(1) << 31)
Jayanth Dodderi Chidanandcfe053a2022-11-08 10:31:07 +00001068#define SMCR_ELX_EZT0_BIT (U(1) << 30)
johpow019baade32021-07-08 14:14:00 -05001069
1070/*******************************************************************************
Isla Mitchell02c63072017-07-21 14:44:36 +01001071 * Definitions of MAIR encodings for device and normal memory
1072 ******************************************************************************/
1073/*
1074 * MAIR encodings for device memory attributes.
1075 */
1076#define MAIR_DEV_nGnRnE ULL(0x0)
1077#define MAIR_DEV_nGnRE ULL(0x4)
1078#define MAIR_DEV_nGRE ULL(0x8)
1079#define MAIR_DEV_GRE ULL(0xc)
1080
1081/*
1082 * MAIR encodings for normal memory attributes.
1083 *
1084 * Cache Policy
1085 * WT: Write Through
1086 * WB: Write Back
1087 * NC: Non-Cacheable
1088 *
1089 * Transient Hint
1090 * NTR: Non-Transient
1091 * TR: Transient
1092 *
1093 * Allocation Policy
1094 * RA: Read Allocate
1095 * WA: Write Allocate
1096 * RWA: Read and Write Allocate
1097 * NA: No Allocation
1098 */
1099#define MAIR_NORM_WT_TR_WA ULL(0x1)
1100#define MAIR_NORM_WT_TR_RA ULL(0x2)
1101#define MAIR_NORM_WT_TR_RWA ULL(0x3)
1102#define MAIR_NORM_NC ULL(0x4)
1103#define MAIR_NORM_WB_TR_WA ULL(0x5)
1104#define MAIR_NORM_WB_TR_RA ULL(0x6)
1105#define MAIR_NORM_WB_TR_RWA ULL(0x7)
1106#define MAIR_NORM_WT_NTR_NA ULL(0x8)
1107#define MAIR_NORM_WT_NTR_WA ULL(0x9)
1108#define MAIR_NORM_WT_NTR_RA ULL(0xa)
1109#define MAIR_NORM_WT_NTR_RWA ULL(0xb)
1110#define MAIR_NORM_WB_NTR_NA ULL(0xc)
1111#define MAIR_NORM_WB_NTR_WA ULL(0xd)
1112#define MAIR_NORM_WB_NTR_RA ULL(0xe)
1113#define MAIR_NORM_WB_NTR_RWA ULL(0xf)
1114
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +01001115#define MAIR_NORM_OUTER_SHIFT U(4)
Isla Mitchell02c63072017-07-21 14:44:36 +01001116
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +01001117#define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \
1118 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT))
Isla Mitchell02c63072017-07-21 14:44:36 +01001119
Jeenu Viswambharan1dc771b2017-10-19 09:15:15 +01001120/* PAR_EL1 fields */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +01001121#define PAR_F_SHIFT U(0)
1122#define PAR_F_MASK ULL(0x1)
1123#define PAR_ADDR_SHIFT U(12)
1124#define PAR_ADDR_MASK (BIT(40) - ULL(1)) /* 40-bits-wide page address */
Jeenu Viswambharan1dc771b2017-10-19 09:15:15 +01001125
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +01001126/*******************************************************************************
1127 * Definitions for system register interface to SPE
1128 ******************************************************************************/
1129#define PMBLIMITR_EL1 S3_0_C9_C10_0
1130
Dimitris Papastamose08005a2017-10-12 13:02:29 +01001131/*******************************************************************************
Rohit Mathew3dc3cad2022-11-11 18:45:11 +00001132 * Definitions for system register interface, shifts and masks for MPAM
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +01001133 ******************************************************************************/
1134#define MPAMIDR_EL1 S3_0_C10_C4_4
1135#define MPAM2_EL2 S3_4_C10_C5_0
1136#define MPAMHCR_EL2 S3_4_C10_C4_0
1137#define MPAM3_EL3 S3_6_C10_C5_0
1138
Andre Przywara84b86532022-11-17 16:42:09 +00001139#define MPAMIDR_EL1_VPMR_MAX_SHIFT ULL(18)
1140#define MPAMIDR_EL1_VPMR_MAX_MASK ULL(0x7)
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +01001141/*******************************************************************************
johpow01fa59c6f2020-10-02 13:41:11 -05001142 * Definitions for system register interface to AMU for FEAT_AMUv1
Dimitris Papastamose08005a2017-10-12 13:02:29 +01001143 ******************************************************************************/
1144#define AMCR_EL0 S3_3_C13_C2_0
1145#define AMCFGR_EL0 S3_3_C13_C2_1
1146#define AMCGCR_EL0 S3_3_C13_C2_2
1147#define AMUSERENR_EL0 S3_3_C13_C2_3
1148#define AMCNTENCLR0_EL0 S3_3_C13_C2_4
1149#define AMCNTENSET0_EL0 S3_3_C13_C2_5
1150#define AMCNTENCLR1_EL0 S3_3_C13_C3_0
1151#define AMCNTENSET1_EL0 S3_3_C13_C3_1
1152
1153/* Activity Monitor Group 0 Event Counter Registers */
1154#define AMEVCNTR00_EL0 S3_3_C13_C4_0
1155#define AMEVCNTR01_EL0 S3_3_C13_C4_1
1156#define AMEVCNTR02_EL0 S3_3_C13_C4_2
1157#define AMEVCNTR03_EL0 S3_3_C13_C4_3
1158
1159/* Activity Monitor Group 0 Event Type Registers */
1160#define AMEVTYPER00_EL0 S3_3_C13_C6_0
1161#define AMEVTYPER01_EL0 S3_3_C13_C6_1
1162#define AMEVTYPER02_EL0 S3_3_C13_C6_2
1163#define AMEVTYPER03_EL0 S3_3_C13_C6_3
1164
Dimitris Papastamos525c37a2017-11-13 09:49:45 +00001165/* Activity Monitor Group 1 Event Counter Registers */
1166#define AMEVCNTR10_EL0 S3_3_C13_C12_0
1167#define AMEVCNTR11_EL0 S3_3_C13_C12_1
1168#define AMEVCNTR12_EL0 S3_3_C13_C12_2
1169#define AMEVCNTR13_EL0 S3_3_C13_C12_3
1170#define AMEVCNTR14_EL0 S3_3_C13_C12_4
1171#define AMEVCNTR15_EL0 S3_3_C13_C12_5
1172#define AMEVCNTR16_EL0 S3_3_C13_C12_6
1173#define AMEVCNTR17_EL0 S3_3_C13_C12_7
1174#define AMEVCNTR18_EL0 S3_3_C13_C13_0
1175#define AMEVCNTR19_EL0 S3_3_C13_C13_1
1176#define AMEVCNTR1A_EL0 S3_3_C13_C13_2
1177#define AMEVCNTR1B_EL0 S3_3_C13_C13_3
1178#define AMEVCNTR1C_EL0 S3_3_C13_C13_4
1179#define AMEVCNTR1D_EL0 S3_3_C13_C13_5
1180#define AMEVCNTR1E_EL0 S3_3_C13_C13_6
1181#define AMEVCNTR1F_EL0 S3_3_C13_C13_7
1182
1183/* Activity Monitor Group 1 Event Type Registers */
1184#define AMEVTYPER10_EL0 S3_3_C13_C14_0
1185#define AMEVTYPER11_EL0 S3_3_C13_C14_1
1186#define AMEVTYPER12_EL0 S3_3_C13_C14_2
1187#define AMEVTYPER13_EL0 S3_3_C13_C14_3
1188#define AMEVTYPER14_EL0 S3_3_C13_C14_4
1189#define AMEVTYPER15_EL0 S3_3_C13_C14_5
1190#define AMEVTYPER16_EL0 S3_3_C13_C14_6
1191#define AMEVTYPER17_EL0 S3_3_C13_C14_7
1192#define AMEVTYPER18_EL0 S3_3_C13_C15_0
1193#define AMEVTYPER19_EL0 S3_3_C13_C15_1
1194#define AMEVTYPER1A_EL0 S3_3_C13_C15_2
1195#define AMEVTYPER1B_EL0 S3_3_C13_C15_3
1196#define AMEVTYPER1C_EL0 S3_3_C13_C15_4
1197#define AMEVTYPER1D_EL0 S3_3_C13_C15_5
1198#define AMEVTYPER1E_EL0 S3_3_C13_C15_6
1199#define AMEVTYPER1F_EL0 S3_3_C13_C15_7
1200
Chris Kaya5fde282021-05-26 11:58:23 +01001201/* AMCNTENSET0_EL0 definitions */
1202#define AMCNTENSET0_EL0_Pn_SHIFT U(0)
1203#define AMCNTENSET0_EL0_Pn_MASK ULL(0xffff)
1204
1205/* AMCNTENSET1_EL0 definitions */
1206#define AMCNTENSET1_EL0_Pn_SHIFT U(0)
1207#define AMCNTENSET1_EL0_Pn_MASK ULL(0xffff)
1208
1209/* AMCNTENCLR0_EL0 definitions */
1210#define AMCNTENCLR0_EL0_Pn_SHIFT U(0)
1211#define AMCNTENCLR0_EL0_Pn_MASK ULL(0xffff)
1212
1213/* AMCNTENCLR1_EL0 definitions */
1214#define AMCNTENCLR1_EL0_Pn_SHIFT U(0)
1215#define AMCNTENCLR1_EL0_Pn_MASK ULL(0xffff)
1216
Alexei Fedorov7e6306b2020-07-14 08:17:56 +01001217/* AMCFGR_EL0 definitions */
1218#define AMCFGR_EL0_NCG_SHIFT U(28)
1219#define AMCFGR_EL0_NCG_MASK U(0xf)
1220#define AMCFGR_EL0_N_SHIFT U(0)
1221#define AMCFGR_EL0_N_MASK U(0xff)
1222
Dimitris Papastamos525c37a2017-11-13 09:49:45 +00001223/* AMCGCR_EL0 definitions */
Chris Kaya40141d2021-05-25 12:33:18 +01001224#define AMCGCR_EL0_CG0NC_SHIFT U(0)
1225#define AMCGCR_EL0_CG0NC_MASK U(0xff)
Dimitris Papastamos525c37a2017-11-13 09:49:45 +00001226#define AMCGCR_EL0_CG1NC_SHIFT U(8)
Dimitris Papastamos525c37a2017-11-13 09:49:45 +00001227#define AMCGCR_EL0_CG1NC_MASK U(0xff)
1228
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +01001229/* MPAM register definitions */
1230#define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63)
Louis Mayencourtbdfa1032019-02-11 11:25:50 +00001231#define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31)
1232
1233#define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49)
1234#define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48)
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +01001235
1236#define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17)
1237
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +01001238/*******************************************************************************
johpow01fa59c6f2020-10-02 13:41:11 -05001239 * Definitions for system register interface to AMU for FEAT_AMUv1p1
1240 ******************************************************************************/
1241
1242/* Definition for register defining which virtual offsets are implemented. */
1243#define AMCG1IDR_EL0 S3_3_C13_C2_6
1244#define AMCG1IDR_CTR_MASK ULL(0xffff)
1245#define AMCG1IDR_CTR_SHIFT U(0)
1246#define AMCG1IDR_VOFF_MASK ULL(0xffff)
1247#define AMCG1IDR_VOFF_SHIFT U(16)
1248
1249/* New bit added to AMCR_EL0 */
Chris Kaya5fde282021-05-26 11:58:23 +01001250#define AMCR_CG1RZ_SHIFT U(17)
1251#define AMCR_CG1RZ_BIT (ULL(0x1) << AMCR_CG1RZ_SHIFT)
johpow01fa59c6f2020-10-02 13:41:11 -05001252
1253/*
1254 * Definitions for virtual offset registers for architected activity monitor
1255 * event counters.
1256 * AMEVCNTVOFF01_EL2 intentionally left undefined, as it does not exist.
1257 */
1258#define AMEVCNTVOFF00_EL2 S3_4_C13_C8_0
1259#define AMEVCNTVOFF02_EL2 S3_4_C13_C8_2
1260#define AMEVCNTVOFF03_EL2 S3_4_C13_C8_3
1261
1262/*
1263 * Definitions for virtual offset registers for auxiliary activity monitor event
1264 * counters.
1265 */
1266#define AMEVCNTVOFF10_EL2 S3_4_C13_C10_0
1267#define AMEVCNTVOFF11_EL2 S3_4_C13_C10_1
1268#define AMEVCNTVOFF12_EL2 S3_4_C13_C10_2
1269#define AMEVCNTVOFF13_EL2 S3_4_C13_C10_3
1270#define AMEVCNTVOFF14_EL2 S3_4_C13_C10_4
1271#define AMEVCNTVOFF15_EL2 S3_4_C13_C10_5
1272#define AMEVCNTVOFF16_EL2 S3_4_C13_C10_6
1273#define AMEVCNTVOFF17_EL2 S3_4_C13_C10_7
1274#define AMEVCNTVOFF18_EL2 S3_4_C13_C11_0
1275#define AMEVCNTVOFF19_EL2 S3_4_C13_C11_1
1276#define AMEVCNTVOFF1A_EL2 S3_4_C13_C11_2
1277#define AMEVCNTVOFF1B_EL2 S3_4_C13_C11_3
1278#define AMEVCNTVOFF1C_EL2 S3_4_C13_C11_4
1279#define AMEVCNTVOFF1D_EL2 S3_4_C13_C11_5
1280#define AMEVCNTVOFF1E_EL2 S3_4_C13_C11_6
1281#define AMEVCNTVOFF1F_EL2 S3_4_C13_C11_7
1282
1283/*******************************************************************************
Zelalem Aweke79e3d292021-07-08 16:51:14 -05001284 * Realm management extension register definitions
1285 ******************************************************************************/
Zelalem Aweke79e3d292021-07-08 16:51:14 -05001286#define GPCCR_EL3 S3_6_C2_C1_6
Zelalem Aweke79e3d292021-07-08 16:51:14 -05001287#define GPTBR_EL3 S3_6_C2_C1_4
1288
Andre Przywara3edbfa72023-03-28 16:55:06 +01001289#define SCXTNUM_EL2 S3_4_C13_C0_7
1290
Zelalem Aweke79e3d292021-07-08 16:51:14 -05001291/*******************************************************************************
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +01001292 * RAS system registers
Sathees Balya0911df12018-12-06 13:33:24 +00001293 ******************************************************************************/
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +01001294#define DISR_EL1 S3_0_C12_C1_1
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +01001295#define DISR_A_BIT U(31)
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +01001296
Jeenu Viswambharan19f6cf22017-12-07 08:43:05 +00001297#define ERRIDR_EL1 S3_0_C5_C3_0
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +01001298#define ERRIDR_MASK U(0xffff)
Jeenu Viswambharan19f6cf22017-12-07 08:43:05 +00001299
1300#define ERRSELR_EL1 S3_0_C5_C3_1
1301
1302/* System register access to Standard Error Record registers */
1303#define ERXFR_EL1 S3_0_C5_C4_0
1304#define ERXCTLR_EL1 S3_0_C5_C4_1
1305#define ERXSTATUS_EL1 S3_0_C5_C4_2
1306#define ERXADDR_EL1 S3_0_C5_C4_3
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +00001307#define ERXPFGF_EL1 S3_0_C5_C4_4
1308#define ERXPFGCTL_EL1 S3_0_C5_C4_5
1309#define ERXPFGCDN_EL1 S3_0_C5_C4_6
Jan Dabros82ef8bf2018-08-30 13:52:23 +02001310#define ERXMISC0_EL1 S3_0_C5_C5_0
1311#define ERXMISC1_EL1 S3_0_C5_C5_1
Jeenu Viswambharan19f6cf22017-12-07 08:43:05 +00001312
johpow017d52a8f2022-03-09 16:23:04 -06001313#define ERXCTLR_ED_SHIFT U(0)
1314#define ERXCTLR_ED_BIT (U(1) << ERXCTLR_ED_SHIFT)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +00001315#define ERXCTLR_UE_BIT (U(1) << 4)
1316
1317#define ERXPFGCTL_UC_BIT (U(1) << 1)
1318#define ERXPFGCTL_UEU_BIT (U(1) << 2)
1319#define ERXPFGCTL_CDEN_BIT (U(1) << 31)
1320
1321/*******************************************************************************
1322 * Armv8.3 Pointer Authentication Registers
Sathees Balya0911df12018-12-06 13:33:24 +00001323 ******************************************************************************/
Antonio Nino Diaz594811b2019-01-31 11:58:00 +00001324#define APIAKeyLo_EL1 S3_0_C2_C1_0
1325#define APIAKeyHi_EL1 S3_0_C2_C1_1
1326#define APIBKeyLo_EL1 S3_0_C2_C1_2
1327#define APIBKeyHi_EL1 S3_0_C2_C1_3
1328#define APDAKeyLo_EL1 S3_0_C2_C2_0
1329#define APDAKeyHi_EL1 S3_0_C2_C2_1
1330#define APDBKeyLo_EL1 S3_0_C2_C2_2
1331#define APDBKeyHi_EL1 S3_0_C2_C2_3
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +00001332#define APGAKeyLo_EL1 S3_0_C2_C3_0
Antonio Nino Diaz594811b2019-01-31 11:58:00 +00001333#define APGAKeyHi_EL1 S3_0_C2_C3_1
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +00001334
Sathees Balya0911df12018-12-06 13:33:24 +00001335/*******************************************************************************
1336 * Armv8.4 Data Independent Timing Registers
1337 ******************************************************************************/
1338#define DIT S3_3_C4_C2_5
1339#define DIT_BIT BIT(24)
1340
John Tsichritzis1f9ff492019-03-04 16:41:26 +00001341/*******************************************************************************
1342 * Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field
1343 ******************************************************************************/
1344#define SSBS S3_3_C4_C2_6
1345
Justin Chadwell1c7c13a2019-07-18 14:25:33 +01001346/*******************************************************************************
1347 * Armv8.5 - Memory Tagging Extension Registers
1348 ******************************************************************************/
1349#define TFSRE0_EL1 S3_0_C5_C6_1
1350#define TFSR_EL1 S3_0_C5_C6_0
1351#define RGSR_EL1 S3_0_C1_C0_5
1352#define GCR_EL1 S3_0_C1_C0_6
1353
Madhukar Pappireddy90d65322019-10-30 14:24:39 -05001354/*******************************************************************************
Andre Przywarabdc76f12022-11-21 17:07:25 +00001355 * Armv8.5 - Random Number Generator Registers
1356 ******************************************************************************/
1357#define RNDR S3_3_C2_C4_0
1358#define RNDRRS S3_3_C2_C4_1
1359
1360/*******************************************************************************
johpow01f91e59f2021-08-04 19:38:18 -05001361 * FEAT_HCX - Extended Hypervisor Configuration Register
1362 ******************************************************************************/
johpow019baade32021-07-08 14:14:00 -05001363#define HCRX_EL2 S3_4_C1_C2_2
Juan Pablo Conde72e0da12023-02-22 10:09:52 -06001364#define HCRX_EL2_MSCEn_BIT (UL(1) << 11)
1365#define HCRX_EL2_MCE2_BIT (UL(1) << 10)
1366#define HCRX_EL2_CMOW_BIT (UL(1) << 9)
1367#define HCRX_EL2_VFNMI_BIT (UL(1) << 8)
1368#define HCRX_EL2_VINMI_BIT (UL(1) << 7)
1369#define HCRX_EL2_TALLINT_BIT (UL(1) << 6)
1370#define HCRX_EL2_SMPME_BIT (UL(1) << 5)
johpow019baade32021-07-08 14:14:00 -05001371#define HCRX_EL2_FGTnXS_BIT (UL(1) << 4)
1372#define HCRX_EL2_FnXS_BIT (UL(1) << 3)
1373#define HCRX_EL2_EnASR_BIT (UL(1) << 2)
1374#define HCRX_EL2_EnALS_BIT (UL(1) << 1)
1375#define HCRX_EL2_EnAS0_BIT (UL(1) << 0)
Juan Pablo Conde72e0da12023-02-22 10:09:52 -06001376#define HCRX_EL2_INIT_VAL ULL(0x0)
johpow01f91e59f2021-08-04 19:38:18 -05001377
1378/*******************************************************************************
Mark Brownc37eee72023-03-14 20:13:03 +00001379 * FEAT_TCR2 - Extended Translation Control Register
1380 ******************************************************************************/
1381#define TCR2_EL2 S3_4_C2_C0_3
1382
1383/*******************************************************************************
Mark Brown293a6612023-03-14 20:48:43 +00001384 * Permission indirection and overlay
1385 ******************************************************************************/
1386
1387#define PIRE0_EL2 S3_4_C10_C2_2
1388#define PIR_EL2 S3_4_C10_C2_3
1389#define POR_EL2 S3_4_C10_C2_4
1390#define S2PIR_EL2 S3_4_C10_C2_5
1391
1392/*******************************************************************************
Mark Brown326f2952023-03-14 21:33:04 +00001393 * FEAT_GCS - Guarded Control Stack Registers
1394 ******************************************************************************/
1395#define GCSCR_EL2 S3_4_C2_C5_0
1396#define GCSPR_EL2 S3_4_C2_C5_1
1397
1398/*******************************************************************************
Madhukar Pappireddy90d65322019-10-30 14:24:39 -05001399 * Definitions for DynamicIQ Shared Unit registers
1400 ******************************************************************************/
1401#define CLUSTERPWRDN_EL1 S3_0_c15_c3_6
1402
1403/* CLUSTERPWRDN_EL1 register definitions */
1404#define DSU_CLUSTER_PWR_OFF 0
1405#define DSU_CLUSTER_PWR_ON 1
1406#define DSU_CLUSTER_PWR_MASK U(1)
1407
Chris Kay03be39d2021-05-05 13:38:30 +01001408/*******************************************************************************
1409 * Definitions for CPU Power/Performance Management registers
1410 ******************************************************************************/
1411
1412#define CPUPPMCR_EL3 S3_6_C15_C2_0
1413#define CPUPPMCR_EL3_MPMMPINCTL_SHIFT UINT64_C(0)
1414#define CPUPPMCR_EL3_MPMMPINCTL_MASK UINT64_C(0x1)
1415
1416#define CPUMPMMCR_EL3 S3_6_C15_C2_1
1417#define CPUMPMMCR_EL3_MPMM_EN_SHIFT UINT64_C(0)
1418#define CPUMPMMCR_EL3_MPMM_EN_MASK UINT64_C(0x1)
1419
Andre Przywarac735f1c2022-11-25 14:10:13 +00001420/* alternative system register encoding for the "sb" speculation barrier */
1421#define SYSREG_SB S0_3_C3_C0_7
1422
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +01001423#endif /* ARCH_H */