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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Manish V Badarkheeba13bd2022-01-08 23:08:02 +00002 * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <assert.h>
8
9#include <common/debug.h>
10#include <drivers/arm/cci.h>
11#include <drivers/arm/ccn.h>
12#include <drivers/arm/gicv2.h>
Alexei Fedorov7131d832019-08-16 14:15:59 +010013#include <drivers/arm/sp804_delay_timer.h>
14#include <drivers/generic_delay_timer.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000015#include <lib/mmio.h>
Manish V Badarkhea637c3f2020-08-04 17:09:10 +010016#include <lib/smccc.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000017#include <lib/xlat_tables/xlat_tables_compat.h>
Antonio Nino Diaza320ecd2019-01-15 14:19:50 +000018#include <platform_def.h>
Manish V Badarkhea637c3f2020-08-04 17:09:10 +010019#include <services/arm_arch_svc.h>
Javier Almansa Sobrino4165e842022-04-25 17:18:15 +010020#if ENABLE_RME
21#include <services/rmm_core_manifest.h>
22#endif
Olivier Deprez21cf3602020-07-30 17:18:33 +020023#if SPM_MM
Paul Beesley45f40282019-10-15 10:57:42 +000024#include <services/spm_mm_partition.h>
Olivier Deprez21cf3602020-07-30 17:18:33 +020025#endif
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000026
Manish V Badarkhea637c3f2020-08-04 17:09:10 +010027#include <plat/arm/common/arm_config.h>
28#include <plat/arm/common/plat_arm.h>
29#include <plat/common/platform.h>
30
Roberto Vargas2ca18d92018-02-12 12:36:17 +000031#include "fvp_private.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010032
Achin Gupta1fa7eb62015-11-03 14:18:34 +000033/* Defines for GIC Driver build time selection */
34#define FVP_GICV2 1
35#define FVP_GICV3 2
Achin Gupta1fa7eb62015-11-03 14:18:34 +000036
Achin Gupta4f6ad662013-10-25 09:08:21 +010037/*******************************************************************************
Dan Handley2b6b5742015-03-19 19:17:53 +000038 * arm_config holds the characteristics of the differences between the three FVP
39 * platforms (Base, A53_A57 & Foundation). It will be populated during cold boot
Vikram Kanigirifbb13012016-02-15 11:54:14 +000040 * at each boot stage by the primary before enabling the MMU (to allow
41 * interconnect configuration) & used thereafter. Each BL will have its own copy
42 * to allow independent operation.
Achin Gupta4f6ad662013-10-25 09:08:21 +010043 ******************************************************************************/
Dan Handley2b6b5742015-03-19 19:17:53 +000044arm_config_t arm_config;
Soby Mathewb08bc042014-09-03 17:48:44 +010045
46#define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \
47 DEVICE0_SIZE, \
48 MT_DEVICE | MT_RW | MT_SECURE)
49
50#define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \
51 DEVICE1_SIZE, \
52 MT_DEVICE | MT_RW | MT_SECURE)
53
Manish V Badarkheb24c6372021-01-24 03:26:50 +000054#if FVP_GICR_REGION_PROTECTION
55#define MAP_GICD_MEM MAP_REGION_FLAT(BASE_GICD_BASE, \
56 BASE_GICD_SIZE, \
57 MT_DEVICE | MT_RW | MT_SECURE)
58
59/* Map all core's redistributor memory as read-only. After boots up,
60 * per-core map its redistributor memory as read-write */
61#define MAP_GICR_MEM MAP_REGION_FLAT(BASE_GICR_BASE, \
62 (BASE_GICR_SIZE * PLATFORM_CORE_COUNT),\
63 MT_DEVICE | MT_RO | MT_SECURE)
64#endif /* FVP_GICR_REGION_PROTECTION */
65
Sandrine Bailleuxd9160a52017-05-26 15:48:10 +010066/*
67 * Need to be mapped with write permissions in order to set a new non-volatile
68 * counter value.
69 */
Juan Castillo31a68f02015-04-14 12:49:03 +010070#define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \
71 DEVICE2_SIZE, \
Antonio Nino Diaz9d602fe2016-05-20 14:14:16 +010072 MT_DEVICE | MT_RW | MT_SECURE)
Juan Castillo31a68f02015-04-14 12:49:03 +010073
Jon Medhurstb1eb0932014-02-26 16:27:53 +000074/*
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +010075 * Table of memory regions for various BL stages to map using the MMU.
Roberto Vargas344ff022018-10-19 16:44:18 +010076 * This doesn't include Trusted SRAM as setup_page_tables() already takes care
77 * of mapping it.
Jon Medhurstb1eb0932014-02-26 16:27:53 +000078 */
Masahiro Yamada441bfdd2016-12-25 23:36:24 +090079#ifdef IMAGE_BL1
Dan Handley2b6b5742015-03-19 19:17:53 +000080const mmap_region_t plat_arm_mmap[] = {
81 ARM_MAP_SHARED_RAM,
Manish V Badarkhe76bf27b2021-06-16 16:50:43 +010082 V2M_MAP_FLASH0_RO,
Dan Handley2b6b5742015-03-19 19:17:53 +000083 V2M_MAP_IOFPGA,
Soby Mathewb08bc042014-09-03 17:48:44 +010084 MAP_DEVICE0,
Manish V Badarkhee40334d2021-01-23 10:55:12 +000085#if FVP_INTERCONNECT_DRIVER == FVP_CCN
Soby Mathewb08bc042014-09-03 17:48:44 +010086 MAP_DEVICE1,
Manish V Badarkhee40334d2021-01-23 10:55:12 +000087#endif
Yatharth Kochar736a3bf2015-10-11 14:14:55 +010088#if TRUSTED_BOARD_BOOT
Sandrine Bailleuxd9160a52017-05-26 15:48:10 +010089 /* To access the Root of Trust Public Key registers. */
90 MAP_DEVICE2,
91 /* Map DRAM to authenticate NS_BL2U image. */
Yatharth Kochar736a3bf2015-10-11 14:14:55 +010092 ARM_MAP_NS_DRAM1,
93#endif
Soby Mathewb08bc042014-09-03 17:48:44 +010094 {0}
95};
96#endif
Masahiro Yamada441bfdd2016-12-25 23:36:24 +090097#ifdef IMAGE_BL2
Dan Handley2b6b5742015-03-19 19:17:53 +000098const mmap_region_t plat_arm_mmap[] = {
99 ARM_MAP_SHARED_RAM,
Juan Castillob6132f12015-10-06 14:01:35 +0100100 V2M_MAP_FLASH0_RW,
Dan Handley2b6b5742015-03-19 19:17:53 +0000101 V2M_MAP_IOFPGA,
Soby Mathewb08bc042014-09-03 17:48:44 +0100102 MAP_DEVICE0,
Manish V Badarkhee40334d2021-01-23 10:55:12 +0000103#if FVP_INTERCONNECT_DRIVER == FVP_CCN
Soby Mathewb08bc042014-09-03 17:48:44 +0100104 MAP_DEVICE1,
Manish V Badarkhee40334d2021-01-23 10:55:12 +0000105#endif
Dan Handley2b6b5742015-03-19 19:17:53 +0000106 ARM_MAP_NS_DRAM1,
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700107#ifdef __aarch64__
Roberto Vargasf8fda102017-08-08 11:27:20 +0100108 ARM_MAP_DRAM2,
109#endif
Manish V Badarkhe86854e72022-03-15 16:05:58 +0000110 /*
111 * Required to load HW_CONFIG, SPMC and SPs to trusted DRAM.
112 */
Achin Guptae97351d2019-10-11 15:15:19 +0100113 ARM_MAP_TRUSTED_DRAM,
Zelalem Awekec43c5632021-07-12 23:41:05 -0500114#if ENABLE_RME
115 ARM_MAP_RMM_DRAM,
116 ARM_MAP_GPT_L1_DRAM,
117#endif /* ENABLE_RME */
Sandrine Bailleuxb260c3a2017-08-30 10:59:22 +0100118#ifdef SPD_tspd
Dan Handley2b6b5742015-03-19 19:17:53 +0000119 ARM_MAP_TSP_SEC_MEM,
Sandrine Bailleuxb260c3a2017-08-30 10:59:22 +0100120#endif
Sandrine Bailleuxd9160a52017-05-26 15:48:10 +0100121#if TRUSTED_BOARD_BOOT
122 /* To access the Root of Trust Public Key registers. */
123 MAP_DEVICE2,
John Tsichritzisc34341a2018-07-30 13:41:52 +0100124#endif /* TRUSTED_BOARD_BOOT */
Manish V Badarkheeba13bd2022-01-08 23:08:02 +0000125
126#if CRYPTO_SUPPORT && !BL2_AT_EL3
127 /*
128 * To access shared the Mbed TLS heap while booting the
129 * system with Crypto support
130 */
131 ARM_MAP_BL1_RW,
132#endif /* CRYPTO_SUPPORT && !BL2_AT_EL3 */
Marc Bonnici6ba5abe2021-11-29 16:59:02 +0000133#if SPM_MM || SPMC_AT_EL3
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000134 ARM_SP_IMAGE_MMAP,
135#endif
David Wang0ba499f2016-03-07 11:02:57 +0800136#if ARM_BL31_IN_DRAM
137 ARM_MAP_BL31_SEC_DRAM,
138#endif
Jens Wiklander0814c6a2017-08-25 10:07:20 +0200139#ifdef SPD_opteed
Soby Mathew874fc9e2017-09-01 13:43:50 +0100140 ARM_MAP_OPTEE_CORE_MEM,
Jens Wiklander0814c6a2017-08-25 10:07:20 +0200141 ARM_OPTEE_PAGEABLE_LOAD_MEM,
142#endif
Soby Mathewb08bc042014-09-03 17:48:44 +0100143 {0}
144};
145#endif
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900146#ifdef IMAGE_BL2U
Yatharth Kochar3a11eda2015-10-14 15:28:11 +0100147const mmap_region_t plat_arm_mmap[] = {
148 MAP_DEVICE0,
149 V2M_MAP_IOFPGA,
150 {0}
151};
152#endif
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900153#ifdef IMAGE_BL31
Dan Handley2b6b5742015-03-19 19:17:53 +0000154const mmap_region_t plat_arm_mmap[] = {
155 ARM_MAP_SHARED_RAM,
Ambroise Vincent9660dc12019-07-12 13:47:03 +0100156#if USE_DEBUGFS
157 /* Required by devfip, can be removed if devfip is not used */
158 V2M_MAP_FLASH0_RW,
159#endif /* USE_DEBUGFS */
Soby Mathew9ca28062017-10-11 16:08:58 +0100160 ARM_MAP_EL3_TZC_DRAM,
Dan Handley2b6b5742015-03-19 19:17:53 +0000161 V2M_MAP_IOFPGA,
Soby Mathewb08bc042014-09-03 17:48:44 +0100162 MAP_DEVICE0,
Manish V Badarkheb24c6372021-01-24 03:26:50 +0000163#if FVP_GICR_REGION_PROTECTION
164 MAP_GICD_MEM,
165 MAP_GICR_MEM,
166#else
Soby Mathewb08bc042014-09-03 17:48:44 +0100167 MAP_DEVICE1,
Manish V Badarkheb24c6372021-01-24 03:26:50 +0000168#endif /* FVP_GICR_REGION_PROTECTION */
Roberto Vargasa1c16b62017-08-03 09:16:43 +0100169 ARM_V2M_MAP_MEM_PROTECT,
Paul Beesleyfe975b42019-09-16 11:29:03 +0000170#if SPM_MM
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000171 ARM_SPM_BUF_EL3_MMAP,
172#endif
Zelalem Awekec43c5632021-07-12 23:41:05 -0500173#if ENABLE_RME
174 ARM_MAP_GPT_L1_DRAM,
Javier Almansa Sobrino7176a772021-11-24 18:37:37 +0000175 ARM_MAP_EL3_RMM_SHARED_MEM,
Zelalem Awekec43c5632021-07-12 23:41:05 -0500176#endif
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000177 {0}
178};
179
Paul Beesleyfe975b42019-09-16 11:29:03 +0000180#if defined(IMAGE_BL31) && SPM_MM
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000181const mmap_region_t plat_arm_secure_partition_mmap[] = {
182 V2M_MAP_IOFPGA_EL0, /* for the UART */
Sandrine Bailleux4808f8b2018-01-12 15:50:12 +0100183 MAP_REGION_FLAT(DEVICE0_BASE, \
184 DEVICE0_SIZE, \
185 MT_DEVICE | MT_RO | MT_SECURE | MT_USER),
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000186 ARM_SP_IMAGE_MMAP,
187 ARM_SP_IMAGE_NS_BUF_MMAP,
188 ARM_SP_IMAGE_RW_MMAP,
189 ARM_SPM_BUF_EL0_MMAP,
Soby Mathewb08bc042014-09-03 17:48:44 +0100190 {0}
191};
192#endif
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000193#endif
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900194#ifdef IMAGE_BL32
Dan Handley2b6b5742015-03-19 19:17:53 +0000195const mmap_region_t plat_arm_mmap[] = {
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700196#ifndef __aarch64__
Soby Mathew0d268dc2016-07-11 14:13:56 +0100197 ARM_MAP_SHARED_RAM,
Joel Hutton10503cc2018-03-15 11:33:44 +0000198 ARM_V2M_MAP_MEM_PROTECT,
Soby Mathew0d268dc2016-07-11 14:13:56 +0100199#endif
Dan Handley2b6b5742015-03-19 19:17:53 +0000200 V2M_MAP_IOFPGA,
Soby Mathewb08bc042014-09-03 17:48:44 +0100201 MAP_DEVICE0,
202 MAP_DEVICE1,
Jon Medhurstb1eb0932014-02-26 16:27:53 +0000203 {0}
204};
Soby Mathewb08bc042014-09-03 17:48:44 +0100205#endif
Jon Medhurstb1eb0932014-02-26 16:27:53 +0000206
Zelalem Aweke96c0bab2021-07-11 18:39:39 -0500207#ifdef IMAGE_RMM
208const mmap_region_t plat_arm_mmap[] = {
209 V2M_MAP_IOFPGA,
210 MAP_DEVICE0,
211 MAP_DEVICE1,
212 {0}
213};
214#endif
215
Dan Handley2b6b5742015-03-19 19:17:53 +0000216ARM_CASSERT_MMAP
Soby Mathew13ee9682015-01-22 11:22:22 +0000217
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100218#if FVP_INTERCONNECT_DRIVER != FVP_CCN
219static const int fvp_cci400_map[] = {
220 PLAT_FVP_CCI400_CLUS0_SL_PORT,
221 PLAT_FVP_CCI400_CLUS1_SL_PORT,
222};
223
224static const int fvp_cci5xx_map[] = {
225 PLAT_FVP_CCI5XX_CLUS0_SL_PORT,
226 PLAT_FVP_CCI5XX_CLUS1_SL_PORT,
227};
228
229static unsigned int get_interconnect_master(void)
230{
231 unsigned int master;
232 u_register_t mpidr;
233
234 mpidr = read_mpidr_el1();
Antonio Nino Diaz6971f002018-11-06 13:14:21 +0000235 master = ((arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) != 0U) ?
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100236 MPIDR_AFFLVL2_VAL(mpidr) : MPIDR_AFFLVL1_VAL(mpidr);
237
238 assert(master < FVP_CLUSTER_COUNT);
239 return master;
240}
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000241#endif
242
Paul Beesleyfe975b42019-09-16 11:29:03 +0000243#if defined(IMAGE_BL31) && SPM_MM
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000244/*
245 * Boot information passed to a secure partition during initialisation. Linear
246 * indices in MP information will be filled at runtime.
247 */
Paul Beesley45f40282019-10-15 10:57:42 +0000248static spm_mm_mp_info_t sp_mp_info[] = {
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000249 [0] = {0x80000000, 0},
250 [1] = {0x80000001, 0},
251 [2] = {0x80000002, 0},
252 [3] = {0x80000003, 0},
253 [4] = {0x80000100, 0},
254 [5] = {0x80000101, 0},
255 [6] = {0x80000102, 0},
256 [7] = {0x80000103, 0},
257};
258
Paul Beesley45f40282019-10-15 10:57:42 +0000259const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = {
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000260 .h.type = PARAM_SP_IMAGE_BOOT_INFO,
261 .h.version = VERSION_1,
Paul Beesley45f40282019-10-15 10:57:42 +0000262 .h.size = sizeof(spm_mm_boot_info_t),
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000263 .h.attr = 0,
264 .sp_mem_base = ARM_SP_IMAGE_BASE,
265 .sp_mem_limit = ARM_SP_IMAGE_LIMIT,
266 .sp_image_base = ARM_SP_IMAGE_BASE,
267 .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE,
268 .sp_heap_base = ARM_SP_IMAGE_HEAP_BASE,
Ard Biesheuvel8b034fc2018-12-29 19:43:21 +0100269 .sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE,
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000270 .sp_shared_buf_base = PLAT_SPM_BUF_BASE,
271 .sp_image_size = ARM_SP_IMAGE_SIZE,
272 .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE,
273 .sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE,
Ard Biesheuvel8b034fc2018-12-29 19:43:21 +0100274 .sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE,
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000275 .sp_shared_buf_size = PLAT_SPM_BUF_SIZE,
276 .num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS,
277 .num_cpus = PLATFORM_CORE_COUNT,
278 .mp_info = &sp_mp_info[0],
279};
280
281const struct mmap_region *plat_get_secure_partition_mmap(void *cookie)
282{
283 return plat_arm_secure_partition_mmap;
284}
285
Paul Beesley45f40282019-10-15 10:57:42 +0000286const struct spm_mm_boot_info *plat_get_secure_partition_boot_info(
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000287 void *cookie)
288{
289 return &plat_arm_secure_partition_boot_info;
290}
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100291#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100292
Achin Gupta4f6ad662013-10-25 09:08:21 +0100293/*******************************************************************************
294 * A single boot loader stack is expected to work on both the Foundation FVP
295 * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The
296 * SYS_ID register provides a mechanism for detecting the differences between
297 * these platforms. This information is stored in a per-BL array to allow the
298 * code to take the correct path.Per BL platform configuration.
299 ******************************************************************************/
Daniel Boulbyf45a4bb2018-09-18 13:26:03 +0100300void __init fvp_config_setup(void)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100301{
Soby Mathew8e2f2872014-08-14 12:49:05 +0100302 unsigned int rev, hbi, bld, arch, sys_id;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100303
Dan Handley2b6b5742015-03-19 19:17:53 +0000304 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID);
305 rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK;
306 hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK;
307 bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK;
308 arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100309
Andrew Thoelke960347d2014-06-26 14:27:26 +0100310 if (arch != ARCH_MODEL) {
311 ERROR("This firmware is for FVP models\n");
James Morrissey40a6f642014-02-10 14:24:36 +0000312 panic();
Andrew Thoelke960347d2014-06-26 14:27:26 +0100313 }
Achin Gupta4f6ad662013-10-25 09:08:21 +0100314
315 /*
316 * The build field in the SYS_ID tells which variant of the GIC
317 * memory is implemented by the model.
318 */
319 switch (bld) {
320 case BLD_GIC_VE_MMAP:
Soby Mathewcf022c52016-01-13 17:06:00 +0000321 ERROR("Legacy Versatile Express memory map for GIC peripheral"
322 " is not supported\n");
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000323 panic();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100324 break;
325 case BLD_GIC_A53A57_MMAP:
Achin Gupta4f6ad662013-10-25 09:08:21 +0100326 break;
327 default:
Andrew Thoelke960347d2014-06-26 14:27:26 +0100328 ERROR("Unsupported board build %x\n", bld);
329 panic();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100330 }
331
332 /*
333 * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010
334 * for the Foundation FVP.
335 */
336 switch (hbi) {
Dan Handley2b6b5742015-03-19 19:17:53 +0000337 case HBI_FOUNDATION_FVP:
Dan Handley2b6b5742015-03-19 19:17:53 +0000338 arm_config.flags = 0;
Andrew Thoelke960347d2014-06-26 14:27:26 +0100339
340 /*
341 * Check for supported revisions of Foundation FVP
342 * Allow future revisions to run but emit warning diagnostic
343 */
344 switch (rev) {
Dan Handley2b6b5742015-03-19 19:17:53 +0000345 case REV_FOUNDATION_FVP_V2_0:
346 case REV_FOUNDATION_FVP_V2_1:
347 case REV_FOUNDATION_FVP_v9_1:
Sandrine Bailleux8b33d702016-09-22 09:46:50 +0100348 case REV_FOUNDATION_FVP_v9_6:
Andrew Thoelke960347d2014-06-26 14:27:26 +0100349 break;
350 default:
351 WARN("Unrecognized Foundation FVP revision %x\n", rev);
352 break;
353 }
Achin Gupta4f6ad662013-10-25 09:08:21 +0100354 break;
Dan Handley2b6b5742015-03-19 19:17:53 +0000355 case HBI_BASE_FVP:
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100356 arm_config.flags |= (ARM_CONFIG_BASE_MMAP | ARM_CONFIG_HAS_TZC);
Andrew Thoelke960347d2014-06-26 14:27:26 +0100357
358 /*
359 * Check for supported revisions
360 * Allow future revisions to run but emit warning diagnostic
361 */
362 switch (rev) {
Dan Handley2b6b5742015-03-19 19:17:53 +0000363 case REV_BASE_FVP_V0:
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100364 arm_config.flags |= ARM_CONFIG_FVP_HAS_CCI400;
365 break;
366 case REV_BASE_FVP_REVC:
Isla Mitchellc7860cf2017-08-17 12:25:34 +0100367 arm_config.flags |= (ARM_CONFIG_FVP_HAS_SMMUV3 |
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100368 ARM_CONFIG_FVP_HAS_CCI5XX);
Andrew Thoelke960347d2014-06-26 14:27:26 +0100369 break;
370 default:
371 WARN("Unrecognized Base FVP revision %x\n", rev);
372 break;
373 }
Achin Gupta4f6ad662013-10-25 09:08:21 +0100374 break;
375 default:
Andrew Thoelke960347d2014-06-26 14:27:26 +0100376 ERROR("Unsupported board HBI number 0x%x\n", hbi);
377 panic();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100378 }
Isla Mitchellc7860cf2017-08-17 12:25:34 +0100379
380 /*
381 * We assume that the presence of MT bit, and therefore shifted
382 * affinities, is uniform across the platform: either all CPUs, or no
383 * CPUs implement it.
384 */
Antonio Nino Diaz6971f002018-11-06 13:14:21 +0000385 if ((read_mpidr_el1() & MPIDR_MT_MASK) != 0U)
Isla Mitchellc7860cf2017-08-17 12:25:34 +0100386 arm_config.flags |= ARM_CONFIG_FVP_SHIFTED_AFF;
Sandrine Bailleux3fa98472014-03-31 11:25:18 +0100387}
Vikram Kanigiri96377452014-04-24 11:02:16 +0100388
Vikram Kanigiri4e97e542015-02-26 15:25:58 +0000389
Daniel Boulbyf45a4bb2018-09-18 13:26:03 +0100390void __init fvp_interconnect_init(void)
Vikram Kanigiri96377452014-04-24 11:02:16 +0100391{
Soby Mathew7356b1e2016-03-24 10:12:42 +0000392#if FVP_INTERCONNECT_DRIVER == FVP_CCN
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100393 if (ccn_get_part0_id(PLAT_ARM_CCN_BASE) != CCN_502_PART0_ID) {
Antonio Nino Diaz6971f002018-11-06 13:14:21 +0000394 ERROR("Unrecognized CCN variant detected. Only CCN-502 is supported");
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100395 panic();
396 }
397
398 plat_arm_interconnect_init();
399#else
Antonio Nino Diaz6971f002018-11-06 13:14:21 +0000400 uintptr_t cci_base = 0U;
401 const int *cci_map = NULL;
402 unsigned int map_size = 0U;
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100403
404 /* Initialize the right interconnect */
Antonio Nino Diaz6971f002018-11-06 13:14:21 +0000405 if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI5XX) != 0U) {
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100406 cci_base = PLAT_FVP_CCI5XX_BASE;
407 cci_map = fvp_cci5xx_map;
408 map_size = ARRAY_SIZE(fvp_cci5xx_map);
Antonio Nino Diaz6971f002018-11-06 13:14:21 +0000409 } else if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI400) != 0U) {
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100410 cci_base = PLAT_FVP_CCI400_BASE;
411 cci_map = fvp_cci400_map;
412 map_size = ARRAY_SIZE(fvp_cci400_map);
Antonio Nino Diaz6971f002018-11-06 13:14:21 +0000413 } else {
414 return;
Soby Mathew7356b1e2016-03-24 10:12:42 +0000415 }
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100416
Antonio Nino Diaz6971f002018-11-06 13:14:21 +0000417 assert(cci_base != 0U);
418 assert(cci_map != NULL);
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100419 cci_init(cci_base, cci_map, map_size);
420#endif
Dan Handleybe234f92014-08-04 16:11:15 +0100421}
422
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000423void fvp_interconnect_enable(void)
Dan Handleybe234f92014-08-04 16:11:15 +0100424{
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100425#if FVP_INTERCONNECT_DRIVER == FVP_CCN
426 plat_arm_interconnect_enter_coherency();
427#else
428 unsigned int master;
429
Antonio Nino Diaz6971f002018-11-06 13:14:21 +0000430 if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 |
431 ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) {
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100432 master = get_interconnect_master();
433 cci_enable_snoop_dvm_reqs(master);
434 }
435#endif
Vikram Kanigiri4e97e542015-02-26 15:25:58 +0000436}
437
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000438void fvp_interconnect_disable(void)
Vikram Kanigiri4e97e542015-02-26 15:25:58 +0000439{
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100440#if FVP_INTERCONNECT_DRIVER == FVP_CCN
441 plat_arm_interconnect_exit_coherency();
442#else
443 unsigned int master;
444
Antonio Nino Diaz6971f002018-11-06 13:14:21 +0000445 if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 |
446 ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) {
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100447 master = get_interconnect_master();
448 cci_disable_snoop_dvm_reqs(master);
449 }
450#endif
Vikram Kanigiri96377452014-04-24 11:02:16 +0100451}
John Tsichritzisc34341a2018-07-30 13:41:52 +0100452
Manish V Badarkheeba13bd2022-01-08 23:08:02 +0000453#if CRYPTO_SUPPORT
John Tsichritzisc34341a2018-07-30 13:41:52 +0100454int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
455{
456 assert(heap_addr != NULL);
457 assert(heap_size != NULL);
458
459 return arm_get_mbedtls_heap(heap_addr, heap_size);
460}
Manish V Badarkheeba13bd2022-01-08 23:08:02 +0000461#endif /* CRYPTO_SUPPORT */
Alexei Fedorov7131d832019-08-16 14:15:59 +0100462
463void fvp_timer_init(void)
464{
Madhukar Pappireddy7a554a12020-08-12 13:18:19 -0500465#if USE_SP804_TIMER
Alexei Fedorov7131d832019-08-16 14:15:59 +0100466 /* Enable the clock override for SP804 timer 0, which means that no
467 * clock dividers are applied and the raw (35MHz) clock will be used.
468 */
469 mmio_write_32(V2M_SP810_BASE, FVP_SP810_CTRL_TIM0_OV);
470
471 /* Initialize delay timer driver using SP804 dual timer 0 */
472 sp804_timer_init(V2M_SP804_TIMER0_BASE,
473 SP804_TIMER_CLKMULT, SP804_TIMER_CLKDIV);
474#else
475 generic_delay_timer_init();
476
477 /* Enable System level generic timer */
478 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF,
479 CNTCR_FCREQ(0U) | CNTCR_EN);
Madhukar Pappireddy7a554a12020-08-12 13:18:19 -0500480#endif /* USE_SP804_TIMER */
Alexei Fedorov7131d832019-08-16 14:15:59 +0100481}
Manish V Badarkhea637c3f2020-08-04 17:09:10 +0100482
483/*****************************************************************************
484 * plat_is_smccc_feature_available() - This function checks whether SMCCC
485 * feature is availabile for platform.
486 * @fid: SMCCC function id
487 *
488 * Return SMC_ARCH_CALL_SUCCESS if SMCCC feature is available and
489 * SMC_ARCH_CALL_NOT_SUPPORTED otherwise.
490 *****************************************************************************/
491int32_t plat_is_smccc_feature_available(u_register_t fid)
492{
493 switch (fid) {
494 case SMCCC_ARCH_SOC_ID:
495 return SMC_ARCH_CALL_SUCCESS;
496 default:
497 return SMC_ARCH_CALL_NOT_SUPPORTED;
498 }
499}
500
501/* Get SOC version */
502int32_t plat_get_soc_version(void)
503{
504 return (int32_t)
Yann Gautieree050772021-05-20 14:57:34 +0200505 (SOC_ID_SET_JEP_106(ARM_SOC_CONTINUATION_CODE,
506 ARM_SOC_IDENTIFICATION_CODE) |
507 (FVP_SOC_ID & SOC_ID_IMPL_DEF_MASK));
Manish V Badarkhea637c3f2020-08-04 17:09:10 +0100508}
509
510/* Get SOC revision */
511int32_t plat_get_soc_revision(void)
512{
513 unsigned int sys_id;
514
515 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID);
Yann Gautieree050772021-05-20 14:57:34 +0200516 return (int32_t)(((sys_id >> V2M_SYS_ID_REV_SHIFT) &
517 V2M_SYS_ID_REV_MASK) & SOC_ID_REV_MASK);
Manish V Badarkhea637c3f2020-08-04 17:09:10 +0100518}
Javier Almansa Sobrino7176a772021-11-24 18:37:37 +0000519
520#if ENABLE_RME
521/*
522 * Get a pointer to the RMM-EL3 Shared buffer and return it
523 * through the pointer passed as parameter.
524 *
525 * This function returns the size of the shared buffer.
526 */
527size_t plat_rmmd_get_el3_rmm_shared_mem(uintptr_t *shared)
528{
529 *shared = (uintptr_t)RMM_SHARED_BASE;
530
531 return (size_t)RMM_SHARED_SIZE;
532}
Javier Almansa Sobrino4165e842022-04-25 17:18:15 +0100533
534int plat_rmmd_load_manifest(rmm_manifest_t *manifest)
535{
536 assert(manifest != NULL);
537
538 manifest->version = RMMD_MANIFEST_VERSION;
Javier Almansa Sobrino04a6f2f2022-12-01 17:20:45 +0000539 manifest->padding = 0U; /* RES0 */
Javier Almansa Sobrino4165e842022-04-25 17:18:15 +0100540 manifest->plat_data = (uintptr_t)NULL;
541
542 return 0;
543}
544
Javier Almansa Sobrino7176a772021-11-24 18:37:37 +0000545#endif