Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Dan Handley | e83b0ca | 2014-01-14 18:17:09 +0000 | [diff] [blame] | 2 | * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 31 | #include <arch.h> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 32 | #include <arch_helpers.h> |
Dan Handley | fb42b12 | 2014-06-20 09:43:15 +0100 | [diff] [blame] | 33 | #include <arm_gic.h> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 34 | #include <bl_common.h> |
Vikram Kanigiri | 9637745 | 2014-04-24 11:02:16 +0100 | [diff] [blame] | 35 | #include <cci400.h> |
Dan Handley | 714a0d2 | 2014-04-09 13:13:04 +0100 | [diff] [blame] | 36 | #include <debug.h> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 37 | #include <mmio.h> |
Jon Medhurst | b1eb093 | 2014-02-26 16:27:53 +0000 | [diff] [blame] | 38 | #include <platform.h> |
Dan Handley | 1c54d97 | 2014-06-20 12:02:01 +0100 | [diff] [blame] | 39 | #include <plat_config.h> |
Jon Medhurst | b1eb093 | 2014-02-26 16:27:53 +0000 | [diff] [blame] | 40 | #include <xlat_tables.h> |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 41 | #include "../fvp_def.h" |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 42 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 43 | /******************************************************************************* |
Dan Handley | 1c54d97 | 2014-06-20 12:02:01 +0100 | [diff] [blame] | 44 | * plat_config holds the characteristics of the differences between the three |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 45 | * FVP platforms (Base, A53_A57 & Foundation). It will be populated during cold |
| 46 | * boot at each boot stage by the primary before enabling the MMU (to allow cci |
| 47 | * configuration) & used thereafter. Each BL will have its own copy to allow |
| 48 | * independent operation. |
| 49 | ******************************************************************************/ |
Dan Handley | 1c54d97 | 2014-06-20 12:02:01 +0100 | [diff] [blame] | 50 | plat_config_t plat_config; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 51 | |
Jon Medhurst | b1eb093 | 2014-02-26 16:27:53 +0000 | [diff] [blame] | 52 | /* |
| 53 | * Table of regions to map using the MMU. |
Sandrine Bailleux | 74a62b3 | 2014-05-09 11:35:36 +0100 | [diff] [blame] | 54 | * This doesn't include TZRAM as the 'mem_layout' argument passed to |
| 55 | * configure_mmu_elx() will give the available subset of that, |
Jon Medhurst | b1eb093 | 2014-02-26 16:27:53 +0000 | [diff] [blame] | 56 | */ |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 57 | const mmap_region_t fvp_mmap[] = { |
Juan Castillo | 48e84b3 | 2014-08-12 13:51:51 +0100 | [diff] [blame] | 58 | { FVP_SHARED_RAM_BASE, FVP_SHARED_RAM_BASE, FVP_SHARED_RAM_SIZE, |
| 59 | MT_MEMORY | MT_RW | MT_SECURE }, |
Juan Castillo | 0c70c57 | 2014-08-12 13:04:43 +0100 | [diff] [blame] | 60 | { FVP_TRUSTED_DRAM_BASE, FVP_TRUSTED_DRAM_BASE, FVP_TRUSTED_DRAM_SIZE, |
Lin Ma | 1359236 | 2014-06-02 11:45:36 -0700 | [diff] [blame] | 61 | MT_MEMORY | MT_RW | MT_SECURE }, |
| 62 | { FLASH0_BASE, FLASH0_BASE, FLASH0_SIZE, |
| 63 | MT_MEMORY | MT_RO | MT_SECURE }, |
| 64 | { FLASH1_BASE, FLASH1_BASE, FLASH1_SIZE, |
| 65 | MT_MEMORY | MT_RO | MT_SECURE }, |
| 66 | { VRAM_BASE, VRAM_BASE, VRAM_SIZE, |
| 67 | MT_MEMORY | MT_RW | MT_SECURE }, |
| 68 | { DEVICE0_BASE, DEVICE0_BASE, DEVICE0_SIZE, |
| 69 | MT_DEVICE | MT_RW | MT_SECURE }, |
Lin Ma | 1359236 | 2014-06-02 11:45:36 -0700 | [diff] [blame] | 70 | { DEVICE1_BASE, DEVICE1_BASE, DEVICE1_SIZE, |
| 71 | MT_DEVICE | MT_RW | MT_SECURE }, |
Jon Medhurst | b1eb093 | 2014-02-26 16:27:53 +0000 | [diff] [blame] | 72 | /* 2nd GB as device for now...*/ |
Lin Ma | 1359236 | 2014-06-02 11:45:36 -0700 | [diff] [blame] | 73 | { 0x40000000, 0x40000000, 0x40000000, |
| 74 | MT_DEVICE | MT_RW | MT_SECURE }, |
| 75 | { DRAM1_BASE, DRAM1_BASE, DRAM1_SIZE, |
| 76 | MT_MEMORY | MT_RW | MT_NS }, |
Jon Medhurst | b1eb093 | 2014-02-26 16:27:53 +0000 | [diff] [blame] | 77 | {0} |
| 78 | }; |
| 79 | |
Dan Handley | fb42b12 | 2014-06-20 09:43:15 +0100 | [diff] [blame] | 80 | /* Array of secure interrupts to be configured by the gic driver */ |
| 81 | const unsigned int irq_sec_array[] = { |
| 82 | IRQ_TZ_WDOG, |
| 83 | IRQ_SEC_PHY_TIMER, |
| 84 | IRQ_SEC_SGI_0, |
| 85 | IRQ_SEC_SGI_1, |
| 86 | IRQ_SEC_SGI_2, |
| 87 | IRQ_SEC_SGI_3, |
| 88 | IRQ_SEC_SGI_4, |
| 89 | IRQ_SEC_SGI_5, |
| 90 | IRQ_SEC_SGI_6, |
| 91 | IRQ_SEC_SGI_7 |
| 92 | }; |
| 93 | |
| 94 | const unsigned int num_sec_irqs = sizeof(irq_sec_array) / |
| 95 | sizeof(irq_sec_array[0]); |
| 96 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 97 | /******************************************************************************* |
Sandrine Bailleux | 74a62b3 | 2014-05-09 11:35:36 +0100 | [diff] [blame] | 98 | * Macro generating the code for the function setting up the pagetables as per |
| 99 | * the platform memory map & initialize the mmu, for the given exception level |
| 100 | ******************************************************************************/ |
| 101 | #define DEFINE_CONFIGURE_MMU_EL(_el) \ |
Lin Ma | 1359236 | 2014-06-02 11:45:36 -0700 | [diff] [blame] | 102 | void fvp_configure_mmu_el##_el(unsigned long total_base, \ |
Vikram Kanigiri | d8c9d26 | 2014-05-16 18:48:12 +0100 | [diff] [blame] | 103 | unsigned long total_size, \ |
Sandrine Bailleux | 74a62b3 | 2014-05-09 11:35:36 +0100 | [diff] [blame] | 104 | unsigned long ro_start, \ |
| 105 | unsigned long ro_limit, \ |
| 106 | unsigned long coh_start, \ |
| 107 | unsigned long coh_limit) \ |
| 108 | { \ |
Lin Ma | 1359236 | 2014-06-02 11:45:36 -0700 | [diff] [blame] | 109 | mmap_add_region(total_base, total_base, \ |
Vikram Kanigiri | d8c9d26 | 2014-05-16 18:48:12 +0100 | [diff] [blame] | 110 | total_size, \ |
Sandrine Bailleux | 74a62b3 | 2014-05-09 11:35:36 +0100 | [diff] [blame] | 111 | MT_MEMORY | MT_RW | MT_SECURE); \ |
Lin Ma | 1359236 | 2014-06-02 11:45:36 -0700 | [diff] [blame] | 112 | mmap_add_region(ro_start, ro_start, \ |
| 113 | ro_limit - ro_start, \ |
Sandrine Bailleux | 74a62b3 | 2014-05-09 11:35:36 +0100 | [diff] [blame] | 114 | MT_MEMORY | MT_RO | MT_SECURE); \ |
Lin Ma | 1359236 | 2014-06-02 11:45:36 -0700 | [diff] [blame] | 115 | mmap_add_region(coh_start, coh_start, \ |
| 116 | coh_limit - coh_start, \ |
Sandrine Bailleux | 74a62b3 | 2014-05-09 11:35:36 +0100 | [diff] [blame] | 117 | MT_DEVICE | MT_RW | MT_SECURE); \ |
| 118 | mmap_add(fvp_mmap); \ |
| 119 | init_xlat_tables(); \ |
| 120 | \ |
Achin Gupta | e998254 | 2014-06-26 08:59:07 +0100 | [diff] [blame] | 121 | enable_mmu_el##_el(0); \ |
Sandrine Bailleux | 74a62b3 | 2014-05-09 11:35:36 +0100 | [diff] [blame] | 122 | } |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 123 | |
Sandrine Bailleux | 74a62b3 | 2014-05-09 11:35:36 +0100 | [diff] [blame] | 124 | /* Define EL1 and EL3 variants of the function initialising the MMU */ |
| 125 | DEFINE_CONFIGURE_MMU_EL(1) |
| 126 | DEFINE_CONFIGURE_MMU_EL(3) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 127 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 128 | /******************************************************************************* |
| 129 | * A single boot loader stack is expected to work on both the Foundation FVP |
| 130 | * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The |
| 131 | * SYS_ID register provides a mechanism for detecting the differences between |
| 132 | * these platforms. This information is stored in a per-BL array to allow the |
| 133 | * code to take the correct path.Per BL platform configuration. |
| 134 | ******************************************************************************/ |
Dan Handley | ea45157 | 2014-05-15 14:53:30 +0100 | [diff] [blame] | 135 | int fvp_config_setup(void) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 136 | { |
| 137 | unsigned int rev, hbi, bld, arch, sys_id, midr_pn; |
| 138 | |
| 139 | sys_id = mmio_read_32(VE_SYSREGS_BASE + V2M_SYS_ID); |
| 140 | rev = (sys_id >> SYS_ID_REV_SHIFT) & SYS_ID_REV_MASK; |
| 141 | hbi = (sys_id >> SYS_ID_HBI_SHIFT) & SYS_ID_HBI_MASK; |
| 142 | bld = (sys_id >> SYS_ID_BLD_SHIFT) & SYS_ID_BLD_MASK; |
| 143 | arch = (sys_id >> SYS_ID_ARCH_SHIFT) & SYS_ID_ARCH_MASK; |
| 144 | |
Andrew Thoelke | 960347d | 2014-06-26 14:27:26 +0100 | [diff] [blame] | 145 | if (arch != ARCH_MODEL) { |
| 146 | ERROR("This firmware is for FVP models\n"); |
James Morrissey | 40a6f64 | 2014-02-10 14:24:36 +0000 | [diff] [blame] | 147 | panic(); |
Andrew Thoelke | 960347d | 2014-06-26 14:27:26 +0100 | [diff] [blame] | 148 | } |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 149 | |
| 150 | /* |
| 151 | * The build field in the SYS_ID tells which variant of the GIC |
| 152 | * memory is implemented by the model. |
| 153 | */ |
| 154 | switch (bld) { |
| 155 | case BLD_GIC_VE_MMAP: |
Dan Handley | 1c54d97 | 2014-06-20 12:02:01 +0100 | [diff] [blame] | 156 | plat_config.gicd_base = VE_GICD_BASE; |
| 157 | plat_config.gicc_base = VE_GICC_BASE; |
| 158 | plat_config.gich_base = VE_GICH_BASE; |
| 159 | plat_config.gicv_base = VE_GICV_BASE; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 160 | break; |
| 161 | case BLD_GIC_A53A57_MMAP: |
Dan Handley | 1c54d97 | 2014-06-20 12:02:01 +0100 | [diff] [blame] | 162 | plat_config.gicd_base = BASE_GICD_BASE; |
| 163 | plat_config.gicc_base = BASE_GICC_BASE; |
| 164 | plat_config.gich_base = BASE_GICH_BASE; |
| 165 | plat_config.gicv_base = BASE_GICV_BASE; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 166 | break; |
| 167 | default: |
Andrew Thoelke | 960347d | 2014-06-26 14:27:26 +0100 | [diff] [blame] | 168 | ERROR("Unsupported board build %x\n", bld); |
| 169 | panic(); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 170 | } |
| 171 | |
| 172 | /* |
| 173 | * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010 |
| 174 | * for the Foundation FVP. |
| 175 | */ |
| 176 | switch (hbi) { |
| 177 | case HBI_FOUNDATION: |
Dan Handley | 1c54d97 | 2014-06-20 12:02:01 +0100 | [diff] [blame] | 178 | plat_config.max_aff0 = 4; |
| 179 | plat_config.max_aff1 = 1; |
| 180 | plat_config.flags = 0; |
Andrew Thoelke | 960347d | 2014-06-26 14:27:26 +0100 | [diff] [blame] | 181 | |
| 182 | /* |
| 183 | * Check for supported revisions of Foundation FVP |
| 184 | * Allow future revisions to run but emit warning diagnostic |
| 185 | */ |
| 186 | switch (rev) { |
| 187 | case REV_FOUNDATION_V2_0: |
| 188 | case REV_FOUNDATION_V2_1: |
| 189 | break; |
| 190 | default: |
| 191 | WARN("Unrecognized Foundation FVP revision %x\n", rev); |
| 192 | break; |
| 193 | } |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 194 | break; |
| 195 | case HBI_FVP_BASE: |
| 196 | midr_pn = (read_midr() >> MIDR_PN_SHIFT) & MIDR_PN_MASK; |
Dan Handley | 1c54d97 | 2014-06-20 12:02:01 +0100 | [diff] [blame] | 197 | plat_config.flags = |
| 198 | ((midr_pn == MIDR_PN_A57) || (midr_pn == MIDR_PN_A53)) |
| 199 | ? CONFIG_CPUECTLR_SMP_BIT : 0; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 200 | |
Dan Handley | 1c54d97 | 2014-06-20 12:02:01 +0100 | [diff] [blame] | 201 | plat_config.max_aff0 = 4; |
| 202 | plat_config.max_aff1 = 2; |
| 203 | plat_config.flags |= CONFIG_BASE_MMAP | CONFIG_HAS_CCI | |
| 204 | CONFIG_HAS_TZC; |
Andrew Thoelke | 960347d | 2014-06-26 14:27:26 +0100 | [diff] [blame] | 205 | |
| 206 | /* |
| 207 | * Check for supported revisions |
| 208 | * Allow future revisions to run but emit warning diagnostic |
| 209 | */ |
| 210 | switch (rev) { |
| 211 | case REV_FVP_BASE_V0: |
| 212 | break; |
| 213 | default: |
| 214 | WARN("Unrecognized Base FVP revision %x\n", rev); |
| 215 | break; |
| 216 | } |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 217 | break; |
| 218 | default: |
Andrew Thoelke | 960347d | 2014-06-26 14:27:26 +0100 | [diff] [blame] | 219 | ERROR("Unsupported board HBI number 0x%x\n", hbi); |
| 220 | panic(); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 221 | } |
| 222 | |
| 223 | return 0; |
| 224 | } |
| 225 | |
Ian Spray | 8468739 | 2014-01-02 16:57:12 +0000 | [diff] [blame] | 226 | unsigned long plat_get_ns_image_entrypoint(void) |
| 227 | { |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 228 | return NS_IMAGE_OFFSET; |
| 229 | } |
Sandrine Bailleux | 3fa9847 | 2014-03-31 11:25:18 +0100 | [diff] [blame] | 230 | |
| 231 | uint64_t plat_get_syscnt_freq(void) |
| 232 | { |
| 233 | uint64_t counter_base_frequency; |
| 234 | |
| 235 | /* Read the frequency from Frequency modes table */ |
| 236 | counter_base_frequency = mmio_read_32(SYS_CNTCTL_BASE + CNTFID_OFF); |
| 237 | |
| 238 | /* The first entry of the frequency modes table must not be 0 */ |
Juan Castillo | f558cac | 2014-06-05 09:45:36 +0100 | [diff] [blame] | 239 | if (counter_base_frequency == 0) |
| 240 | panic(); |
Sandrine Bailleux | 3fa9847 | 2014-03-31 11:25:18 +0100 | [diff] [blame] | 241 | |
| 242 | return counter_base_frequency; |
| 243 | } |
Vikram Kanigiri | 9637745 | 2014-04-24 11:02:16 +0100 | [diff] [blame] | 244 | |
Dan Handley | be234f9 | 2014-08-04 16:11:15 +0100 | [diff] [blame^] | 245 | void fvp_cci_init(void) |
Vikram Kanigiri | 9637745 | 2014-04-24 11:02:16 +0100 | [diff] [blame] | 246 | { |
Vikram Kanigiri | 9637745 | 2014-04-24 11:02:16 +0100 | [diff] [blame] | 247 | /* |
Dan Handley | be234f9 | 2014-08-04 16:11:15 +0100 | [diff] [blame^] | 248 | * Initialize CCI-400 driver |
| 249 | */ |
| 250 | if (plat_config.flags & CONFIG_HAS_CCI) |
| 251 | cci_init(CCI400_BASE, |
| 252 | CCI400_SL_IFACE3_CLUSTER_IX, |
| 253 | CCI400_SL_IFACE4_CLUSTER_IX); |
| 254 | } |
| 255 | |
| 256 | void fvp_cci_enable(void) |
| 257 | { |
| 258 | /* |
| 259 | * Enable CCI-400 coherency for this cluster. No need |
Vikram Kanigiri | 9637745 | 2014-04-24 11:02:16 +0100 | [diff] [blame] | 260 | * for locks as no other cpu is active at the |
| 261 | * moment |
| 262 | */ |
Dan Handley | 1c54d97 | 2014-06-20 12:02:01 +0100 | [diff] [blame] | 263 | if (plat_config.flags & CONFIG_HAS_CCI) |
Dan Handley | be234f9 | 2014-08-04 16:11:15 +0100 | [diff] [blame^] | 264 | cci_enable_cluster_coherency(read_mpidr()); |
Vikram Kanigiri | 9637745 | 2014-04-24 11:02:16 +0100 | [diff] [blame] | 265 | } |
| 266 | |
Dan Handley | fb42b12 | 2014-06-20 09:43:15 +0100 | [diff] [blame] | 267 | void fvp_gic_init(void) |
| 268 | { |
| 269 | arm_gic_init(plat_config.gicc_base, |
| 270 | plat_config.gicd_base, |
| 271 | BASE_GICR_BASE, |
| 272 | irq_sec_array, |
| 273 | num_sec_irqs); |
| 274 | } |
| 275 | |
Vikram Kanigiri | 9637745 | 2014-04-24 11:02:16 +0100 | [diff] [blame] | 276 | |
| 277 | /******************************************************************************* |
Vikram Kanigiri | cf79bf5 | 2014-06-02 14:59:00 +0100 | [diff] [blame] | 278 | * Gets SPSR for BL32 entry |
Vikram Kanigiri | 9637745 | 2014-04-24 11:02:16 +0100 | [diff] [blame] | 279 | ******************************************************************************/ |
Vikram Kanigiri | cf79bf5 | 2014-06-02 14:59:00 +0100 | [diff] [blame] | 280 | uint32_t fvp_get_spsr_for_bl32_entry(void) |
Vikram Kanigiri | 9637745 | 2014-04-24 11:02:16 +0100 | [diff] [blame] | 281 | { |
Vikram Kanigiri | 9637745 | 2014-04-24 11:02:16 +0100 | [diff] [blame] | 282 | /* |
| 283 | * The Secure Payload Dispatcher service is responsible for |
| 284 | * setting the SPSR prior to entry into the BL32 image. |
| 285 | */ |
Vikram Kanigiri | cf79bf5 | 2014-06-02 14:59:00 +0100 | [diff] [blame] | 286 | return 0; |
Vikram Kanigiri | 9637745 | 2014-04-24 11:02:16 +0100 | [diff] [blame] | 287 | } |
| 288 | |
| 289 | /******************************************************************************* |
Vikram Kanigiri | cf79bf5 | 2014-06-02 14:59:00 +0100 | [diff] [blame] | 290 | * Gets SPSR for BL33 entry |
Vikram Kanigiri | 9637745 | 2014-04-24 11:02:16 +0100 | [diff] [blame] | 291 | ******************************************************************************/ |
Vikram Kanigiri | cf79bf5 | 2014-06-02 14:59:00 +0100 | [diff] [blame] | 292 | uint32_t fvp_get_spsr_for_bl33_entry(void) |
Vikram Kanigiri | 9637745 | 2014-04-24 11:02:16 +0100 | [diff] [blame] | 293 | { |
| 294 | unsigned long el_status; |
| 295 | unsigned int mode; |
Vikram Kanigiri | cf79bf5 | 2014-06-02 14:59:00 +0100 | [diff] [blame] | 296 | uint32_t spsr; |
Vikram Kanigiri | 9637745 | 2014-04-24 11:02:16 +0100 | [diff] [blame] | 297 | |
| 298 | /* Figure out what mode we enter the non-secure world in */ |
| 299 | el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; |
| 300 | el_status &= ID_AA64PFR0_ELX_MASK; |
| 301 | |
| 302 | if (el_status) |
| 303 | mode = MODE_EL2; |
| 304 | else |
| 305 | mode = MODE_EL1; |
| 306 | |
| 307 | /* |
| 308 | * TODO: Consider the possibility of specifying the SPSR in |
| 309 | * the FIP ToC and allowing the platform to have a say as |
| 310 | * well. |
| 311 | */ |
Vikram Kanigiri | cf79bf5 | 2014-06-02 14:59:00 +0100 | [diff] [blame] | 312 | spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); |
| 313 | return spsr; |
Vikram Kanigiri | 9637745 | 2014-04-24 11:02:16 +0100 | [diff] [blame] | 314 | } |