blob: 264d0c68830656fe6ef0674df9b8f56e6cc00956 [file] [log] [blame]
Dan Handley610e7e12018-03-01 18:44:00 +00001Arm CPU Specific Build Macros
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002=============================
3
Douglas Raillardd7c21b72017-06-28 15:23:03 +01004This document describes the various build options present in the CPU specific
5operations framework to enable errata workarounds and to enable optimizations
6for a specific CPU on a platform.
7
Dimitris Papastamos446f7f12017-11-30 14:53:53 +00008Security Vulnerability Workarounds
9----------------------------------
10
Dan Handley610e7e12018-03-01 18:44:00 +000011TF-A exports a series of build flags which control which security
12vulnerability workarounds should be applied at runtime.
Dimitris Papastamos446f7f12017-11-30 14:53:53 +000013
14- ``WORKAROUND_CVE_2017_5715``: Enables the security workaround for
Dimitris Papastamos6d1f4992018-03-28 12:06:40 +010015 `CVE-2017-5715`_. This flag can be set to 0 by the platform if none
16 of the PEs in the system need the workaround. Setting this flag to 0 provides
17 no performance benefit for non-affected platforms, it just helps to comply
18 with the recommendation in the spec regarding workaround discovery.
19 Defaults to 1.
Dimitris Papastamos446f7f12017-11-30 14:53:53 +000020
Dimitris Papastamose6625ec2018-04-05 14:38:26 +010021- ``WORKAROUND_CVE_2018_3639``: Enables the security workaround for
22 `CVE-2018-3639`_. Defaults to 1. The TF-A project recommends to keep
23 the default value of 1 even on platforms that are unaffected by
24 CVE-2018-3639, in order to comply with the recommendation in the spec
25 regarding workaround discovery.
26
Dimitris Papastamosba51d9e2018-05-16 11:36:14 +010027- ``DYNAMIC_WORKAROUND_CVE_2018_3639``: Enables dynamic mitigation for
28 `CVE-2018-3639`_. This build option should be set to 1 if the target
29 platform contains at least 1 CPU that requires dynamic mitigation.
30 Defaults to 0.
31
Paul Beesleyf8640672019-04-12 14:19:42 +010032.. _arm_cpu_macros_errata_workarounds:
33
Douglas Raillardd7c21b72017-06-28 15:23:03 +010034CPU Errata Workarounds
35----------------------
36
Dan Handley610e7e12018-03-01 18:44:00 +000037TF-A exports a series of build flags which control the errata workarounds that
38are applied to each CPU by the reset handler. The errata details can be found
39in the CPU specific errata documents published by Arm:
Douglas Raillardd7c21b72017-06-28 15:23:03 +010040
41- `Cortex-A53 MPCore Software Developers Errata Notice`_
42- `Cortex-A57 MPCore Software Developers Errata Notice`_
Eleanor Bonnicic3b4ca12017-08-02 18:33:41 +010043- `Cortex-A72 MPCore Software Developers Errata Notice`_
Douglas Raillardd7c21b72017-06-28 15:23:03 +010044
45The errata workarounds are implemented for a particular revision or a set of
46processor revisions. This is checked by the reset handler at runtime. Each
47errata workaround is identified by its ``ID`` as specified in the processor's
48errata notice document. The format of the define used to enable/disable the
49errata workaround is ``ERRATA_<Processor name>_<ID>``, where the ``Processor name``
50is for example ``A57`` for the ``Cortex_A57`` CPU.
51
Paul Beesleyf8640672019-04-12 14:19:42 +010052Refer to :ref:`firmware_design_cpu_errata_reporting` for information on how to
53write errata workaround functions.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010054
55All workarounds are disabled by default. The platform is responsible for
56enabling these workarounds according to its requirement by defining the
57errata workaround build flags in the platform specific makefile. In case
58these workarounds are enabled for the wrong CPU revision then the errata
59workaround is not applied. In the DEBUG build, this is indicated by
60printing a warning to the crash console.
61
62In the current implementation, a platform which has more than 1 variant
63with different revisions of a processor has no runtime mechanism available
64for it to specify which errata workarounds should be enabled or not.
65
John Tsichritzis4daa1de2018-07-23 09:11:59 +010066The value of the build flags is 0 by default, that is, disabled. A value of 1
67will enable it.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010068
Joel Hutton26d16762019-04-10 12:52:52 +010069For Cortex-A9, the following errata build flags are defined :
70
Louis Mayencourte6469d52019-04-18 12:11:25 +010071- ``ERRATA_A9_794073``: This applies errata 794073 workaround to Cortex-A9
Joel Hutton26d16762019-04-10 12:52:52 +010072 CPU. This needs to be enabled for all revisions of the CPU.
73
Ambroise Vincentd4a51eb2019-03-04 16:56:26 +000074For Cortex-A15, the following errata build flags are defined :
75
76- ``ERRATA_A15_816470``: This applies errata 816470 workaround to Cortex-A15
77 CPU. This needs to be enabled only for revision >= r3p0 of the CPU.
78
Ambroise Vincent68b38122019-03-05 09:54:21 +000079- ``ERRATA_A15_827671``: This applies errata 827671 workaround to Cortex-A15
80 CPU. This needs to be enabled only for revision >= r3p0 of the CPU.
81
Ambroise Vincent8cf9eef2019-02-28 16:23:53 +000082For Cortex-A17, the following errata build flags are defined :
83
84- ``ERRATA_A17_852421``: This applies errata 852421 workaround to Cortex-A17
85 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
86
Ambroise Vincentfa5c9512019-03-04 13:20:56 +000087- ``ERRATA_A17_852423``: This applies errata 852423 workaround to Cortex-A17
88 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
89
Louis Mayencourt8a061272019-04-05 16:25:25 +010090For Cortex-A35, the following errata build flags are defined :
91
92- ``ERRATA_A35_855472``: This applies errata 855472 workaround to Cortex-A35
93 CPUs. This needs to be enabled only for revision r0p0 of Cortex-A35.
94
John Tsichritzis4daa1de2018-07-23 09:11:59 +010095For Cortex-A53, the following errata build flags are defined :
Douglas Raillardd7c21b72017-06-28 15:23:03 +010096
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +000097- ``ERRATA_A53_819472``: This applies errata 819472 workaround to all
98 CPUs. This needs to be enabled only for revision <= r0p1 of Cortex-A53.
99
100- ``ERRATA_A53_824069``: This applies errata 824069 workaround to all
101 CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53.
102
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100103- ``ERRATA_A53_826319``: This applies errata 826319 workaround to Cortex-A53
104 CPU. This needs to be enabled only for revision <= r0p2 of the CPU.
105
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +0000106- ``ERRATA_A53_827319``: This applies errata 827319 workaround to all
107 CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53.
108
Douglas Raillardb52353a2017-07-17 14:14:52 +0100109- ``ERRATA_A53_835769``: This applies erratum 835769 workaround at compile and
110 link time to Cortex-A53 CPU. This needs to be enabled for some variants of
111 revision <= r0p4. This workaround can lead the linker to create ``*.stub``
112 sections.
113
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100114- ``ERRATA_A53_836870``: This applies errata 836870 workaround to Cortex-A53
115 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. From
116 r0p4 and onwards, this errata is enabled by default in hardware.
117
Douglas Raillardb52353a2017-07-17 14:14:52 +0100118- ``ERRATA_A53_843419``: This applies erratum 843419 workaround at link time
119 to Cortex-A53 CPU. This needs to be enabled for some variants of revision
120 <= r0p4. This workaround can lead the linker to emit ``*.stub`` sections
121 which are 4kB aligned.
122
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100123- ``ERRATA_A53_855873``: This applies errata 855873 workaround to Cortex-A53
124 CPUs. Though the erratum is present in every revision of the CPU,
125 this workaround is only applied to CPUs from r0p3 onwards, which feature
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100126 a chicken bit in CPUACTLR_EL1 to enable a hardware workaround.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100127 Earlier revisions of the CPU have other errata which require the same
128 workaround in software, so they should be covered anyway.
129
Ambroise Vincent7927fa02019-02-21 16:20:43 +0000130For Cortex-A55, the following errata build flags are defined :
131
132- ``ERRATA_A55_768277``: This applies errata 768277 workaround to Cortex-A55
133 CPU. This needs to be enabled only for revision r0p0 of the CPU.
134
Ambroise Vincent6f319602019-02-21 16:25:37 +0000135- ``ERRATA_A55_778703``: This applies errata 778703 workaround to Cortex-A55
136 CPU. This needs to be enabled only for revision r0p0 of the CPU.
137
Ambroise Vincent6a77f052019-02-21 16:27:34 +0000138- ``ERRATA_A55_798797``: This applies errata 798797 workaround to Cortex-A55
139 CPU. This needs to be enabled only for revision r0p0 of the CPU.
140
Ambroise Vincentdd961f72019-02-21 16:29:16 +0000141- ``ERRATA_A55_846532``: This applies errata 846532 workaround to Cortex-A55
142 CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
143
Ambroise Vincenta1d64462019-02-21 16:29:50 +0000144- ``ERRATA_A55_903758``: This applies errata 903758 workaround to Cortex-A55
145 CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
146
Ambroise Vincentb72fe7a2019-05-28 09:52:48 +0100147- ``ERRATA_A55_1221012``: This applies errata 1221012 workaround to Cortex-A55
148 CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
149
John Tsichritzis4daa1de2018-07-23 09:11:59 +0100150For Cortex-A57, the following errata build flags are defined :
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100151
152- ``ERRATA_A57_806969``: This applies errata 806969 workaround to Cortex-A57
153 CPU. This needs to be enabled only for revision r0p0 of the CPU.
154
155- ``ERRATA_A57_813419``: This applies errata 813419 workaround to Cortex-A57
156 CPU. This needs to be enabled only for revision r0p0 of the CPU.
157
158- ``ERRATA_A57_813420``: This applies errata 813420 workaround to Cortex-A57
159 CPU. This needs to be enabled only for revision r0p0 of the CPU.
160
Ambroise Vincent1b0db762019-02-21 16:35:07 +0000161- ``ERRATA_A57_814670``: This applies errata 814670 workaround to Cortex-A57
162 CPU. This needs to be enabled only for revision r0p0 of the CPU.
163
Ambroise Vincentaa2c0292019-02-21 16:35:49 +0000164- ``ERRATA_A57_817169``: This applies errata 817169 workaround to Cortex-A57
165 CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
166
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100167- ``ERRATA_A57_826974``: This applies errata 826974 workaround to Cortex-A57
168 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
169
170- ``ERRATA_A57_826977``: This applies errata 826977 workaround to Cortex-A57
171 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
172
173- ``ERRATA_A57_828024``: This applies errata 828024 workaround to Cortex-A57
174 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
175
176- ``ERRATA_A57_829520``: This applies errata 829520 workaround to Cortex-A57
177 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
178
179- ``ERRATA_A57_833471``: This applies errata 833471 workaround to Cortex-A57
180 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
181
Eleanor Bonnici0c9bd272017-08-02 16:35:04 +0100182- ``ERRATA_A57_859972``: This applies errata 859972 workaround to Cortex-A57
183 CPU. This needs to be enabled only for revision <= r1p3 of the CPU.
184
Eleanor Bonnicic3b4ca12017-08-02 18:33:41 +0100185
John Tsichritzis4daa1de2018-07-23 09:11:59 +0100186For Cortex-A72, the following errata build flags are defined :
Eleanor Bonnicic3b4ca12017-08-02 18:33:41 +0100187
188- ``ERRATA_A72_859971``: This applies errata 859971 workaround to Cortex-A72
189 CPU. This needs to be enabled only for revision <= r0p3 of the CPU.
190
Louis Mayencourt4405de62019-02-21 16:38:16 +0000191For Cortex-A73, the following errata build flags are defined :
192
Louis Mayencourtd69722c2019-02-27 14:24:16 +0000193- ``ERRATA_A73_852427``: This applies errata 852427 workaround to Cortex-A73
194 CPU. This needs to be enabled only for revision r0p0 of the CPU.
195
Louis Mayencourt4405de62019-02-21 16:38:16 +0000196- ``ERRATA_A73_855423``: This applies errata 855423 workaround to Cortex-A73
197 CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
198
Louis Mayencourt78a0aed2019-02-20 12:11:41 +0000199For Cortex-A75, the following errata build flags are defined :
200
201- ``ERRATA_A75_764081``: This applies errata 764081 workaround to Cortex-A75
202 CPU. This needs to be enabled only for revision r0p0 of the CPU.
203
Louis Mayencourt8d868702019-02-25 14:57:57 +0000204- ``ERRATA_A75_790748``: This applies errata 790748 workaround to Cortex-A75
205 CPU. This needs to be enabled only for revision r0p0 of the CPU.
206
Louis Mayencourt09924472019-02-21 17:35:07 +0000207For Cortex-A76, the following errata build flags are defined :
208
Louis Mayencourt59fa2182019-02-25 15:17:44 +0000209- ``ERRATA_A76_1073348``: This applies errata 1073348 workaround to Cortex-A76
210 CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
211
Louis Mayencourt09924472019-02-21 17:35:07 +0000212- ``ERRATA_A76_1130799``: This applies errata 1130799 workaround to Cortex-A76
213 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
214
Louis Mayencourtadda9d42019-02-25 11:37:38 +0000215- ``ERRATA_A76_1220197``: This applies errata 1220197 workaround to Cortex-A76
216 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
217
Soby Mathew1d3ba1c2019-05-01 09:43:18 +0100218- ``ERRATA_A76_1257314``: This applies errata 1257314 workaround to Cortex-A76
219 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
220
221- ``ERRATA_A76_1262606``: This applies errata 1262606 workaround to Cortex-A76
222 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
223
224- ``ERRATA_A76_1262888``: This applies errata 1262888 workaround to Cortex-A76
225 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
226
227- ``ERRATA_A76_1275112``: This applies errata 1275112 workaround to Cortex-A76
228 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
229
johpow019603f982020-05-29 14:17:38 -0500230- ``ERRATA_A76_1791580``: This applies errata 1791580 workaround to Cortex-A76
231 CPU. This needs to be enabled only for revision <= r4p0 of the CPU.
232
johpow015c9ed082020-06-02 15:02:28 -0500233- ``ERRATA_A76_1800710``: This applies errata 1800710 workaround to Cortex-A76
234 CPU. This needs to be enabled only for revision <= r4p0 of the CPU.
235
Jimmy Brisson3571fb92020-06-01 10:18:22 -0500236For Cortex-A78, the following errata build flags are defined :
Madhukar Pappireddy4efede72019-12-18 15:56:27 -0600237
Jimmy Brisson3571fb92020-06-01 10:18:22 -0500238- ``ERRATA_A78_1688305``: This applies errata 1688305 workaround to Cortex-A78
239 CPU. This needs to be enabled only for revision r0p0 - r1p0 of the CPU.
Madhukar Pappireddy4efede72019-12-18 15:56:27 -0600240
lauwal01bd555f42019-06-24 11:23:50 -0500241For Neoverse N1, the following errata build flags are defined :
242
243- ``ERRATA_N1_1073348``: This applies errata 1073348 workaround to Neoverse-N1
244 CPU. This needs to be enabled only for revision r0p0 and r1p0 of the CPU.
245
lauwal01363ee3c2019-06-24 11:28:34 -0500246- ``ERRATA_N1_1130799``: This applies errata 1130799 workaround to Neoverse-N1
247 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
248
lauwal01f2adb132019-06-24 11:32:40 -0500249- ``ERRATA_N1_1165347``: This applies errata 1165347 workaround to Neoverse-N1
250 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
251
lauwal01e1590442019-06-24 11:35:37 -0500252- ``ERRATA_N1_1207823``: This applies errata 1207823 workaround to Neoverse-N1
253 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
254
lauwal01197f14c2019-06-24 11:38:53 -0500255- ``ERRATA_N1_1220197``: This applies errata 1220197 workaround to Neoverse-N1
256 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
257
lauwal0107c2a232019-06-24 11:42:02 -0500258- ``ERRATA_N1_1257314``: This applies errata 1257314 workaround to Neoverse-N1
259 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
260
lauwal0142771af2019-06-24 11:44:58 -0500261- ``ERRATA_N1_1262606``: This applies errata 1262606 workaround to Neoverse-N1
262 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
263
lauwal0100396bf2019-06-24 11:47:30 -0500264- ``ERRATA_N1_1262888``: This applies errata 1262888 workaround to Neoverse-N1
265 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
266
lauwal01644b6ed2019-06-24 11:49:01 -0500267- ``ERRATA_N1_1275112``: This applies errata 1275112 workaround to Neoverse-N1
268 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
269
Andre Przywarab9347402019-05-20 14:57:06 +0100270- ``ERRATA_N1_1315703``: This applies errata 1315703 workaround to Neoverse-N1
271 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
272
laurenw-arm94accd32019-08-20 15:51:24 -0500273- ``ERRATA_N1_1542419``: This applies errata 1542419 workaround to Neoverse-N1
274 CPU. This needs to be enabled only for revisions r3p0 - r4p0 of the CPU.
275
John Tsichritzis4daa1de2018-07-23 09:11:59 +0100276DSU Errata Workarounds
277----------------------
278
279Similar to CPU errata, TF-A also implements workarounds for DSU (DynamIQ
280Shared Unit) errata. The DSU errata details can be found in the respective Arm
281documentation:
282
283- `Arm DSU Software Developers Errata Notice`_.
284
285Each erratum is identified by an ``ID``, as defined in the DSU errata notice
286document. Thus, the build flags which enable/disable the errata workarounds
287have the format ``ERRATA_DSU_<ID>``. The implementation and application logic
288of DSU errata workarounds are similar to `CPU errata workarounds`_.
289
290For DSU errata, the following build flags are defined:
291
Louis Mayencourt4498b152019-04-09 16:29:01 +0100292- ``ERRATA_DSU_798953``: This applies errata 798953 workaround for the
293 affected DSU configurations. This errata applies only for those DSUs that
294 revision is r0p0 (on r0p1 it is fixed). However, please note that this
295 workaround results in increased DSU power consumption on idle.
296
John Tsichritzis4daa1de2018-07-23 09:11:59 +0100297- ``ERRATA_DSU_936184``: This applies errata 936184 workaround for the
298 affected DSU configurations. This errata applies only for those DSUs that
299 contain the ACP interface **and** the DSU revision is older than r2p0 (on
300 r2p0 it is fixed). However, please note that this workaround results in
301 increased DSU power consumption on idle.
302
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100303CPU Specific optimizations
304--------------------------
305
306This section describes some of the optimizations allowed by the CPU micro
307architecture that can be enabled by the platform as desired.
308
309- ``SKIP_A57_L1_FLUSH_PWR_DWN``: This flag enables an optimization in the
310 Cortex-A57 cluster power down sequence by not flushing the Level 1 data
311 cache. The L1 data cache and the L2 unified cache are inclusive. A flush
312 of the L2 by set/way flushes any dirty lines from the L1 as well. This
313 is a known safe deviation from the Cortex-A57 TRM defined power down
314 sequence. Each Cortex-A57 based platform must make its own decision on
315 whether to use the optimization.
316
317- ``A53_DISABLE_NON_TEMPORAL_HINT``: This flag disables the cache non-temporal
318 hint. The LDNP/STNP instructions as implemented on Cortex-A53 do not behave
319 in a way most programmers expect, and will most probably result in a
Dan Handley610e7e12018-03-01 18:44:00 +0000320 significant speed degradation to any code that employs them. The Armv8-A
321 architecture (see Arm DDI 0487A.h, section D3.4.3) allows cores to ignore
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100322 the non-temporal hint and treat LDNP/STNP as LDP/STP instead. Enabling this
323 flag enforces this behaviour. This needs to be enabled only for revisions
324 <= r0p3 of the CPU and is enabled by default.
325
326- ``A57_DISABLE_NON_TEMPORAL_HINT``: This flag has the same behaviour as
327 ``A53_DISABLE_NON_TEMPORAL_HINT`` but for Cortex-A57. This needs to be
328 enabled only for revisions <= r1p2 of the CPU and is enabled by default,
329 as recommended in section "4.7 Non-Temporal Loads/Stores" of the
330 `Cortex-A57 Software Optimization Guide`_.
331
Varun Wadekar5ee3abc2018-06-12 16:49:12 -0700332- ''A57_ENABLE_NON_CACHEABLE_LOAD_FWD'': This flag enables non-cacheable
333 streaming enhancement feature for Cortex-A57 CPUs. Platforms can set
334 this bit only if their memory system meets the requirement that cache
335 line fill requests from the Cortex-A57 processor are atomic. Each
336 Cortex-A57 based platform must make its own decision on whether to use
337 the optimization. This flag is disabled by default.
338
Manish Pandey3880a362020-01-24 11:54:44 +0000339- ``NEOVERSE_N1_EXTERNAL_LLC``: This flag indicates that an external last
340 level cache(LLC) is present in the system, and that the DataSource field
341 on the master CHI interface indicates when data is returned from the LLC.
342 This is used to control how the LL_CACHE* PMU events count.
343
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100344--------------
345
Jimmy Brisson3571fb92020-06-01 10:18:22 -0500346*Copyright (c) 2014-2020, Arm Limited and Contributors. All rights reserved.*
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100347
John Tsichritzis3eeac412018-09-04 10:56:53 +0100348.. _CVE-2017-5715: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5715
349.. _CVE-2018-3639: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3639
Paul Beesley2437ddc2019-02-08 16:43:05 +0000350.. _Cortex-A53 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm048406/index.html
351.. _Cortex-A57 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm049219/index.html
Eleanor Bonnicic3b4ca12017-08-02 18:33:41 +0100352.. _Cortex-A72 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm012079/index.html
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100353.. _Cortex-A57 Software Optimization Guide: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100354.. _Arm DSU Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm138168/index.html