blob: 33b509083d07b8541bb7a70a000c3630394b4b59 [file] [log] [blame]
Dan Handley610e7e12018-03-01 18:44:00 +00001Arm CPU Specific Build Macros
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002=============================
3
Douglas Raillardd7c21b72017-06-28 15:23:03 +01004This document describes the various build options present in the CPU specific
5operations framework to enable errata workarounds and to enable optimizations
6for a specific CPU on a platform.
7
Dimitris Papastamos446f7f12017-11-30 14:53:53 +00008Security Vulnerability Workarounds
9----------------------------------
10
Dan Handley610e7e12018-03-01 18:44:00 +000011TF-A exports a series of build flags which control which security
12vulnerability workarounds should be applied at runtime.
Dimitris Papastamos446f7f12017-11-30 14:53:53 +000013
14- ``WORKAROUND_CVE_2017_5715``: Enables the security workaround for
Dimitris Papastamos6d1f4992018-03-28 12:06:40 +010015 `CVE-2017-5715`_. This flag can be set to 0 by the platform if none
16 of the PEs in the system need the workaround. Setting this flag to 0 provides
17 no performance benefit for non-affected platforms, it just helps to comply
18 with the recommendation in the spec regarding workaround discovery.
19 Defaults to 1.
Dimitris Papastamos446f7f12017-11-30 14:53:53 +000020
Dimitris Papastamose6625ec2018-04-05 14:38:26 +010021- ``WORKAROUND_CVE_2018_3639``: Enables the security workaround for
22 `CVE-2018-3639`_. Defaults to 1. The TF-A project recommends to keep
23 the default value of 1 even on platforms that are unaffected by
24 CVE-2018-3639, in order to comply with the recommendation in the spec
25 regarding workaround discovery.
26
Dimitris Papastamosba51d9e2018-05-16 11:36:14 +010027- ``DYNAMIC_WORKAROUND_CVE_2018_3639``: Enables dynamic mitigation for
28 `CVE-2018-3639`_. This build option should be set to 1 if the target
29 platform contains at least 1 CPU that requires dynamic mitigation.
30 Defaults to 0.
31
Paul Beesleyf8640672019-04-12 14:19:42 +010032.. _arm_cpu_macros_errata_workarounds:
33
Douglas Raillardd7c21b72017-06-28 15:23:03 +010034CPU Errata Workarounds
35----------------------
36
Dan Handley610e7e12018-03-01 18:44:00 +000037TF-A exports a series of build flags which control the errata workarounds that
38are applied to each CPU by the reset handler. The errata details can be found
39in the CPU specific errata documents published by Arm:
Douglas Raillardd7c21b72017-06-28 15:23:03 +010040
41- `Cortex-A53 MPCore Software Developers Errata Notice`_
42- `Cortex-A57 MPCore Software Developers Errata Notice`_
Eleanor Bonnicic3b4ca12017-08-02 18:33:41 +010043- `Cortex-A72 MPCore Software Developers Errata Notice`_
Douglas Raillardd7c21b72017-06-28 15:23:03 +010044
45The errata workarounds are implemented for a particular revision or a set of
46processor revisions. This is checked by the reset handler at runtime. Each
47errata workaround is identified by its ``ID`` as specified in the processor's
48errata notice document. The format of the define used to enable/disable the
49errata workaround is ``ERRATA_<Processor name>_<ID>``, where the ``Processor name``
50is for example ``A57`` for the ``Cortex_A57`` CPU.
51
Paul Beesleyf8640672019-04-12 14:19:42 +010052Refer to :ref:`firmware_design_cpu_errata_reporting` for information on how to
53write errata workaround functions.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010054
55All workarounds are disabled by default. The platform is responsible for
56enabling these workarounds according to its requirement by defining the
57errata workaround build flags in the platform specific makefile. In case
58these workarounds are enabled for the wrong CPU revision then the errata
59workaround is not applied. In the DEBUG build, this is indicated by
60printing a warning to the crash console.
61
62In the current implementation, a platform which has more than 1 variant
63with different revisions of a processor has no runtime mechanism available
64for it to specify which errata workarounds should be enabled or not.
65
John Tsichritzis4daa1de2018-07-23 09:11:59 +010066The value of the build flags is 0 by default, that is, disabled. A value of 1
67will enable it.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010068
Joel Hutton26d16762019-04-10 12:52:52 +010069For Cortex-A9, the following errata build flags are defined :
70
Louis Mayencourte6469d52019-04-18 12:11:25 +010071- ``ERRATA_A9_794073``: This applies errata 794073 workaround to Cortex-A9
Joel Hutton26d16762019-04-10 12:52:52 +010072 CPU. This needs to be enabled for all revisions of the CPU.
73
Ambroise Vincentd4a51eb2019-03-04 16:56:26 +000074For Cortex-A15, the following errata build flags are defined :
75
76- ``ERRATA_A15_816470``: This applies errata 816470 workaround to Cortex-A15
77 CPU. This needs to be enabled only for revision >= r3p0 of the CPU.
78
Ambroise Vincent68b38122019-03-05 09:54:21 +000079- ``ERRATA_A15_827671``: This applies errata 827671 workaround to Cortex-A15
80 CPU. This needs to be enabled only for revision >= r3p0 of the CPU.
81
Ambroise Vincent8cf9eef2019-02-28 16:23:53 +000082For Cortex-A17, the following errata build flags are defined :
83
84- ``ERRATA_A17_852421``: This applies errata 852421 workaround to Cortex-A17
85 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
86
Ambroise Vincentfa5c9512019-03-04 13:20:56 +000087- ``ERRATA_A17_852423``: This applies errata 852423 workaround to Cortex-A17
88 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
89
Louis Mayencourt8a061272019-04-05 16:25:25 +010090For Cortex-A35, the following errata build flags are defined :
91
92- ``ERRATA_A35_855472``: This applies errata 855472 workaround to Cortex-A35
93 CPUs. This needs to be enabled only for revision r0p0 of Cortex-A35.
94
John Tsichritzis4daa1de2018-07-23 09:11:59 +010095For Cortex-A53, the following errata build flags are defined :
Douglas Raillardd7c21b72017-06-28 15:23:03 +010096
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +000097- ``ERRATA_A53_819472``: This applies errata 819472 workaround to all
98 CPUs. This needs to be enabled only for revision <= r0p1 of Cortex-A53.
99
100- ``ERRATA_A53_824069``: This applies errata 824069 workaround to all
101 CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53.
102
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100103- ``ERRATA_A53_826319``: This applies errata 826319 workaround to Cortex-A53
104 CPU. This needs to be enabled only for revision <= r0p2 of the CPU.
105
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +0000106- ``ERRATA_A53_827319``: This applies errata 827319 workaround to all
107 CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53.
108
Douglas Raillardb52353a2017-07-17 14:14:52 +0100109- ``ERRATA_A53_835769``: This applies erratum 835769 workaround at compile and
110 link time to Cortex-A53 CPU. This needs to be enabled for some variants of
111 revision <= r0p4. This workaround can lead the linker to create ``*.stub``
112 sections.
113
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100114- ``ERRATA_A53_836870``: This applies errata 836870 workaround to Cortex-A53
115 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. From
116 r0p4 and onwards, this errata is enabled by default in hardware.
117
Douglas Raillardb52353a2017-07-17 14:14:52 +0100118- ``ERRATA_A53_843419``: This applies erratum 843419 workaround at link time
119 to Cortex-A53 CPU. This needs to be enabled for some variants of revision
120 <= r0p4. This workaround can lead the linker to emit ``*.stub`` sections
121 which are 4kB aligned.
122
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100123- ``ERRATA_A53_855873``: This applies errata 855873 workaround to Cortex-A53
124 CPUs. Though the erratum is present in every revision of the CPU,
125 this workaround is only applied to CPUs from r0p3 onwards, which feature
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100126 a chicken bit in CPUACTLR_EL1 to enable a hardware workaround.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100127 Earlier revisions of the CPU have other errata which require the same
128 workaround in software, so they should be covered anyway.
129
Manish V Badarkhea59fa012020-07-31 08:38:49 +0100130- ``ERRATA_A53_1530924``: This applies errata 1530924 workaround to all
131 revisions of Cortex-A53 CPU.
132
Ambroise Vincent7927fa02019-02-21 16:20:43 +0000133For Cortex-A55, the following errata build flags are defined :
134
135- ``ERRATA_A55_768277``: This applies errata 768277 workaround to Cortex-A55
136 CPU. This needs to be enabled only for revision r0p0 of the CPU.
137
Ambroise Vincent6f319602019-02-21 16:25:37 +0000138- ``ERRATA_A55_778703``: This applies errata 778703 workaround to Cortex-A55
139 CPU. This needs to be enabled only for revision r0p0 of the CPU.
140
Ambroise Vincent6a77f052019-02-21 16:27:34 +0000141- ``ERRATA_A55_798797``: This applies errata 798797 workaround to Cortex-A55
142 CPU. This needs to be enabled only for revision r0p0 of the CPU.
143
Ambroise Vincentdd961f72019-02-21 16:29:16 +0000144- ``ERRATA_A55_846532``: This applies errata 846532 workaround to Cortex-A55
145 CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
146
Ambroise Vincenta1d64462019-02-21 16:29:50 +0000147- ``ERRATA_A55_903758``: This applies errata 903758 workaround to Cortex-A55
148 CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
149
Ambroise Vincentb72fe7a2019-05-28 09:52:48 +0100150- ``ERRATA_A55_1221012``: This applies errata 1221012 workaround to Cortex-A55
151 CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
152
Manish V Badarkhea59fa012020-07-31 08:38:49 +0100153- ``ERRATA_A55_1530923``: This applies errata 1530923 workaround to all
154 revisions of Cortex-A55 CPU.
155
John Tsichritzis4daa1de2018-07-23 09:11:59 +0100156For Cortex-A57, the following errata build flags are defined :
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100157
158- ``ERRATA_A57_806969``: This applies errata 806969 workaround to Cortex-A57
159 CPU. This needs to be enabled only for revision r0p0 of the CPU.
160
161- ``ERRATA_A57_813419``: This applies errata 813419 workaround to Cortex-A57
162 CPU. This needs to be enabled only for revision r0p0 of the CPU.
163
164- ``ERRATA_A57_813420``: This applies errata 813420 workaround to Cortex-A57
165 CPU. This needs to be enabled only for revision r0p0 of the CPU.
166
Ambroise Vincent1b0db762019-02-21 16:35:07 +0000167- ``ERRATA_A57_814670``: This applies errata 814670 workaround to Cortex-A57
168 CPU. This needs to be enabled only for revision r0p0 of the CPU.
169
Ambroise Vincentaa2c0292019-02-21 16:35:49 +0000170- ``ERRATA_A57_817169``: This applies errata 817169 workaround to Cortex-A57
171 CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
172
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100173- ``ERRATA_A57_826974``: This applies errata 826974 workaround to Cortex-A57
174 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
175
176- ``ERRATA_A57_826977``: This applies errata 826977 workaround to Cortex-A57
177 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
178
179- ``ERRATA_A57_828024``: This applies errata 828024 workaround to Cortex-A57
180 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
181
182- ``ERRATA_A57_829520``: This applies errata 829520 workaround to Cortex-A57
183 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
184
185- ``ERRATA_A57_833471``: This applies errata 833471 workaround to Cortex-A57
186 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
187
Eleanor Bonnici0c9bd272017-08-02 16:35:04 +0100188- ``ERRATA_A57_859972``: This applies errata 859972 workaround to Cortex-A57
189 CPU. This needs to be enabled only for revision <= r1p3 of the CPU.
190
Manish V Badarkhea59fa012020-07-31 08:38:49 +0100191- ``ERRATA_A57_1319537``: This applies errata 1319537 workaround to all
192 revisions of Cortex-A57 CPU.
Eleanor Bonnicic3b4ca12017-08-02 18:33:41 +0100193
John Tsichritzis4daa1de2018-07-23 09:11:59 +0100194For Cortex-A72, the following errata build flags are defined :
Eleanor Bonnicic3b4ca12017-08-02 18:33:41 +0100195
196- ``ERRATA_A72_859971``: This applies errata 859971 workaround to Cortex-A72
197 CPU. This needs to be enabled only for revision <= r0p3 of the CPU.
198
Manish V Badarkhea59fa012020-07-31 08:38:49 +0100199- ``ERRATA_A72_1319367``: This applies errata 1319367 workaround to all
200 revisions of Cortex-A72 CPU.
201
Louis Mayencourt4405de62019-02-21 16:38:16 +0000202For Cortex-A73, the following errata build flags are defined :
203
Louis Mayencourtd69722c2019-02-27 14:24:16 +0000204- ``ERRATA_A73_852427``: This applies errata 852427 workaround to Cortex-A73
205 CPU. This needs to be enabled only for revision r0p0 of the CPU.
206
Louis Mayencourt4405de62019-02-21 16:38:16 +0000207- ``ERRATA_A73_855423``: This applies errata 855423 workaround to Cortex-A73
208 CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
209
Louis Mayencourt78a0aed2019-02-20 12:11:41 +0000210For Cortex-A75, the following errata build flags are defined :
211
212- ``ERRATA_A75_764081``: This applies errata 764081 workaround to Cortex-A75
213 CPU. This needs to be enabled only for revision r0p0 of the CPU.
214
Louis Mayencourt8d868702019-02-25 14:57:57 +0000215- ``ERRATA_A75_790748``: This applies errata 790748 workaround to Cortex-A75
216 CPU. This needs to be enabled only for revision r0p0 of the CPU.
217
Louis Mayencourt09924472019-02-21 17:35:07 +0000218For Cortex-A76, the following errata build flags are defined :
219
Louis Mayencourt59fa2182019-02-25 15:17:44 +0000220- ``ERRATA_A76_1073348``: This applies errata 1073348 workaround to Cortex-A76
221 CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
222
Louis Mayencourt09924472019-02-21 17:35:07 +0000223- ``ERRATA_A76_1130799``: This applies errata 1130799 workaround to Cortex-A76
224 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
225
Louis Mayencourtadda9d42019-02-25 11:37:38 +0000226- ``ERRATA_A76_1220197``: This applies errata 1220197 workaround to Cortex-A76
227 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
228
Soby Mathew1d3ba1c2019-05-01 09:43:18 +0100229- ``ERRATA_A76_1257314``: This applies errata 1257314 workaround to Cortex-A76
230 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
231
232- ``ERRATA_A76_1262606``: This applies errata 1262606 workaround to Cortex-A76
233 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
234
235- ``ERRATA_A76_1262888``: This applies errata 1262888 workaround to Cortex-A76
236 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
237
238- ``ERRATA_A76_1275112``: This applies errata 1275112 workaround to Cortex-A76
239 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
240
johpow019603f982020-05-29 14:17:38 -0500241- ``ERRATA_A76_1791580``: This applies errata 1791580 workaround to Cortex-A76
242 CPU. This needs to be enabled only for revision <= r4p0 of the CPU.
243
johpow015c9ed082020-06-02 15:02:28 -0500244- ``ERRATA_A76_1800710``: This applies errata 1800710 workaround to Cortex-A76
245 CPU. This needs to be enabled only for revision <= r4p0 of the CPU.
246
Manish V Badarkhea59fa012020-07-31 08:38:49 +0100247- ``ERRATA_A76_1165522``: This applies errata 1165522 workaround to all
248 revisions of Cortex-A76 CPU. This errata is fixed in r3p0 but due to
249 limitation of errata framework this errata is applied to all revisions
250 of Cortex-A76 CPU.
251
johpow0168aedc72020-06-03 15:23:31 -0500252For Cortex-A77, the following errata build flags are defined :
253
254- ``ERRATA_A77_1800714``: This applies errata 1800714 workaround to Cortex-A77
255 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
256
Jimmy Brisson3571fb92020-06-01 10:18:22 -0500257For Cortex-A78, the following errata build flags are defined :
Madhukar Pappireddy4efede72019-12-18 15:56:27 -0600258
Jimmy Brisson3571fb92020-06-01 10:18:22 -0500259- ``ERRATA_A78_1688305``: This applies errata 1688305 workaround to Cortex-A78
260 CPU. This needs to be enabled only for revision r0p0 - r1p0 of the CPU.
Madhukar Pappireddy4efede72019-12-18 15:56:27 -0600261
lauwal01bd555f42019-06-24 11:23:50 -0500262For Neoverse N1, the following errata build flags are defined :
263
264- ``ERRATA_N1_1073348``: This applies errata 1073348 workaround to Neoverse-N1
265 CPU. This needs to be enabled only for revision r0p0 and r1p0 of the CPU.
266
lauwal01363ee3c2019-06-24 11:28:34 -0500267- ``ERRATA_N1_1130799``: This applies errata 1130799 workaround to Neoverse-N1
268 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
269
lauwal01f2adb132019-06-24 11:32:40 -0500270- ``ERRATA_N1_1165347``: This applies errata 1165347 workaround to Neoverse-N1
271 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
272
lauwal01e1590442019-06-24 11:35:37 -0500273- ``ERRATA_N1_1207823``: This applies errata 1207823 workaround to Neoverse-N1
274 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
275
lauwal01197f14c2019-06-24 11:38:53 -0500276- ``ERRATA_N1_1220197``: This applies errata 1220197 workaround to Neoverse-N1
277 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
278
lauwal0107c2a232019-06-24 11:42:02 -0500279- ``ERRATA_N1_1257314``: This applies errata 1257314 workaround to Neoverse-N1
280 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
281
lauwal0142771af2019-06-24 11:44:58 -0500282- ``ERRATA_N1_1262606``: This applies errata 1262606 workaround to Neoverse-N1
283 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
284
lauwal0100396bf2019-06-24 11:47:30 -0500285- ``ERRATA_N1_1262888``: This applies errata 1262888 workaround to Neoverse-N1
286 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
287
lauwal01644b6ed2019-06-24 11:49:01 -0500288- ``ERRATA_N1_1275112``: This applies errata 1275112 workaround to Neoverse-N1
289 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
290
Andre Przywarab9347402019-05-20 14:57:06 +0100291- ``ERRATA_N1_1315703``: This applies errata 1315703 workaround to Neoverse-N1
292 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
293
laurenw-arm94accd32019-08-20 15:51:24 -0500294- ``ERRATA_N1_1542419``: This applies errata 1542419 workaround to Neoverse-N1
295 CPU. This needs to be enabled only for revisions r3p0 - r4p0 of the CPU.
296
John Tsichritzis4daa1de2018-07-23 09:11:59 +0100297DSU Errata Workarounds
298----------------------
299
300Similar to CPU errata, TF-A also implements workarounds for DSU (DynamIQ
301Shared Unit) errata. The DSU errata details can be found in the respective Arm
302documentation:
303
304- `Arm DSU Software Developers Errata Notice`_.
305
306Each erratum is identified by an ``ID``, as defined in the DSU errata notice
307document. Thus, the build flags which enable/disable the errata workarounds
308have the format ``ERRATA_DSU_<ID>``. The implementation and application logic
309of DSU errata workarounds are similar to `CPU errata workarounds`_.
310
311For DSU errata, the following build flags are defined:
312
Louis Mayencourt4498b152019-04-09 16:29:01 +0100313- ``ERRATA_DSU_798953``: This applies errata 798953 workaround for the
314 affected DSU configurations. This errata applies only for those DSUs that
315 revision is r0p0 (on r0p1 it is fixed). However, please note that this
316 workaround results in increased DSU power consumption on idle.
317
John Tsichritzis4daa1de2018-07-23 09:11:59 +0100318- ``ERRATA_DSU_936184``: This applies errata 936184 workaround for the
319 affected DSU configurations. This errata applies only for those DSUs that
320 contain the ACP interface **and** the DSU revision is older than r2p0 (on
321 r2p0 it is fixed). However, please note that this workaround results in
322 increased DSU power consumption on idle.
323
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100324CPU Specific optimizations
325--------------------------
326
327This section describes some of the optimizations allowed by the CPU micro
328architecture that can be enabled by the platform as desired.
329
330- ``SKIP_A57_L1_FLUSH_PWR_DWN``: This flag enables an optimization in the
331 Cortex-A57 cluster power down sequence by not flushing the Level 1 data
332 cache. The L1 data cache and the L2 unified cache are inclusive. A flush
333 of the L2 by set/way flushes any dirty lines from the L1 as well. This
334 is a known safe deviation from the Cortex-A57 TRM defined power down
335 sequence. Each Cortex-A57 based platform must make its own decision on
336 whether to use the optimization.
337
338- ``A53_DISABLE_NON_TEMPORAL_HINT``: This flag disables the cache non-temporal
339 hint. The LDNP/STNP instructions as implemented on Cortex-A53 do not behave
340 in a way most programmers expect, and will most probably result in a
Dan Handley610e7e12018-03-01 18:44:00 +0000341 significant speed degradation to any code that employs them. The Armv8-A
342 architecture (see Arm DDI 0487A.h, section D3.4.3) allows cores to ignore
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100343 the non-temporal hint and treat LDNP/STNP as LDP/STP instead. Enabling this
344 flag enforces this behaviour. This needs to be enabled only for revisions
345 <= r0p3 of the CPU and is enabled by default.
346
347- ``A57_DISABLE_NON_TEMPORAL_HINT``: This flag has the same behaviour as
348 ``A53_DISABLE_NON_TEMPORAL_HINT`` but for Cortex-A57. This needs to be
349 enabled only for revisions <= r1p2 of the CPU and is enabled by default,
350 as recommended in section "4.7 Non-Temporal Loads/Stores" of the
351 `Cortex-A57 Software Optimization Guide`_.
352
Varun Wadekar5ee3abc2018-06-12 16:49:12 -0700353- ''A57_ENABLE_NON_CACHEABLE_LOAD_FWD'': This flag enables non-cacheable
354 streaming enhancement feature for Cortex-A57 CPUs. Platforms can set
355 this bit only if their memory system meets the requirement that cache
356 line fill requests from the Cortex-A57 processor are atomic. Each
357 Cortex-A57 based platform must make its own decision on whether to use
358 the optimization. This flag is disabled by default.
359
Manish Pandey3880a362020-01-24 11:54:44 +0000360- ``NEOVERSE_N1_EXTERNAL_LLC``: This flag indicates that an external last
361 level cache(LLC) is present in the system, and that the DataSource field
362 on the master CHI interface indicates when data is returned from the LLC.
363 This is used to control how the LL_CACHE* PMU events count.
364
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100365--------------
366
Jimmy Brisson3571fb92020-06-01 10:18:22 -0500367*Copyright (c) 2014-2020, Arm Limited and Contributors. All rights reserved.*
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100368
John Tsichritzis3eeac412018-09-04 10:56:53 +0100369.. _CVE-2017-5715: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5715
370.. _CVE-2018-3639: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3639
Paul Beesley2437ddc2019-02-08 16:43:05 +0000371.. _Cortex-A53 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm048406/index.html
372.. _Cortex-A57 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm049219/index.html
Eleanor Bonnicic3b4ca12017-08-02 18:33:41 +0100373.. _Cortex-A72 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm012079/index.html
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100374.. _Cortex-A57 Software Optimization Guide: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100375.. _Arm DSU Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm138168/index.html