blob: 0cb1c16662a0301d911d6e31cbe4d14e513d1591 [file] [log] [blame]
developer29647af2022-11-15 18:09:16 +08001From bc9cac100bb95aa89b6ded079f1065fbb739c90c Mon Sep 17 00:00:00 2001
developer8cb3ac72022-07-04 10:55:14 +08002From: Sujuan Chen <sujuan.chen@mediatek.com>
developerf50c1802022-07-05 20:35:53 +08003Date: Tue, 5 Jul 2022 19:42:55 +0800
developer356ecec2022-11-14 10:25:04 +08004Subject: [PATCH 3003/3011] mt76 add wed rx support
developer8cb3ac72022-07-04 10:55:14 +08005
6Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
7---
developerbbca0f92022-07-26 17:26:12 +08008 dma.c | 250 ++++++++++++++++++++++++++++++++++++++--------
9 dma.h | 10 ++
10 mac80211.c | 8 +-
developere0cbe332022-09-10 17:36:02 +080011 mt76.h | 24 ++++-
developerbbca0f92022-07-26 17:26:12 +080012 mt7603/dma.c | 2 +-
13 mt7603/mt7603.h | 2 +-
14 mt7615/mac.c | 2 +-
15 mt7615/mt7615.h | 2 +-
16 mt76_connac_mcu.c | 9 ++
17 mt76x02.h | 2 +-
18 mt76x02_txrx.c | 2 +-
developerc226de82022-10-03 12:24:57 +080019 mt7915/dma.c | 17 +++-
developer20747c12022-09-16 14:09:40 +080020 mt7915/mac.c | 101 ++++++++++++++++++-
developere0cbe332022-09-10 17:36:02 +080021 mt7915/mcu.c | 3 +
developerc226de82022-10-03 12:24:57 +080022 mt7915/mmio.c | 30 ++++--
developere0cbe332022-09-10 17:36:02 +080023 mt7915/mt7915.h | 7 +-
developerc226de82022-10-03 12:24:57 +080024 mt7915/regs.h | 6 ++
developerbbca0f92022-07-26 17:26:12 +080025 mt7921/mac.c | 2 +-
developer20747c12022-09-16 14:09:40 +080026 mt7921/mt7921.h | 2 +-
developerbbca0f92022-07-26 17:26:12 +080027 tx.c | 34 +++++++
developerc226de82022-10-03 12:24:57 +080028 20 files changed, 448 insertions(+), 67 deletions(-)
developer8cb3ac72022-07-04 10:55:14 +080029
30diff --git a/dma.c b/dma.c
developer29647af2022-11-15 18:09:16 +080031index 82b4da2..a8739eb 100644
developer8cb3ac72022-07-04 10:55:14 +080032--- a/dma.c
33+++ b/dma.c
34@@ -98,6 +98,63 @@ mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t)
35 }
36 EXPORT_SYMBOL_GPL(mt76_put_txwi);
37
38+static struct mt76_txwi_cache *
39+mt76_alloc_rxwi(struct mt76_dev *dev)
40+{
41+ struct mt76_txwi_cache *r;
42+ int size;
43+
44+ size = L1_CACHE_ALIGN(sizeof(*r));
45+ r = kzalloc(size, GFP_ATOMIC);
46+ if (!r)
47+ return NULL;
48+
49+ r->buf = NULL;
50+
51+ return r;
52+}
53+
54+static struct mt76_txwi_cache *
55+__mt76_get_rxwi(struct mt76_dev *dev)
56+{
57+ struct mt76_txwi_cache *r = NULL;
58+
59+ spin_lock(&dev->wed_lock);
60+ if (!list_empty(&dev->rxwi_cache)) {
61+ r = list_first_entry(&dev->rxwi_cache, struct mt76_txwi_cache,
62+ list);
63+ if(r)
64+ list_del(&r->list);
65+ }
66+ spin_unlock(&dev->wed_lock);
67+
68+ return r;
69+}
70+
71+struct mt76_txwi_cache *
72+mt76_get_rxwi(struct mt76_dev *dev)
73+{
74+ struct mt76_txwi_cache *r = __mt76_get_rxwi(dev);
75+
76+ if (r)
77+ return r;
78+
79+ return mt76_alloc_rxwi(dev);
80+}
81+EXPORT_SYMBOL_GPL(mt76_get_rxwi);
82+
83+void
84+mt76_put_rxwi(struct mt76_dev *dev, struct mt76_txwi_cache *r)
85+{
86+ if (!r)
87+ return;
88+
89+ spin_lock(&dev->wed_lock);
90+ list_add(&r->list, &dev->rxwi_cache);
91+ spin_unlock(&dev->wed_lock);
92+}
93+EXPORT_SYMBOL_GPL(mt76_put_rxwi);
94+
95 static void
96 mt76_free_pending_txwi(struct mt76_dev *dev)
97 {
developera3f86ed2022-07-08 14:15:13 +080098@@ -112,6 +169,21 @@ mt76_free_pending_txwi(struct mt76_dev *dev)
99 local_bh_enable();
100 }
101
102+static void
103+mt76_free_pending_rxwi(struct mt76_dev *dev)
104+{
105+ struct mt76_txwi_cache *r;
106+
107+ local_bh_disable();
108+ while ((r = __mt76_get_rxwi(dev)) != NULL) {
109+ if (r->buf)
110+ skb_free_frag(r->buf);
111+
112+ kfree(r);
113+ }
114+ local_bh_enable();
115+}
116+
117 static void
118 mt76_dma_sync_idx(struct mt76_dev *dev, struct mt76_queue *q)
119 {
120@@ -141,12 +213,15 @@ mt76_dma_queue_reset(struct mt76_dev *dev, struct mt76_queue *q)
developer8cb3ac72022-07-04 10:55:14 +0800121 static int
122 mt76_dma_add_buf(struct mt76_dev *dev, struct mt76_queue *q,
123 struct mt76_queue_buf *buf, int nbufs, u32 info,
124- struct sk_buff *skb, void *txwi)
125+ struct sk_buff *skb, void *txwi, void *rxwi)
126 {
127+ struct mtk_wed_device *wed = &dev->mmio.wed;
128+
129 struct mt76_queue_entry *entry;
130 struct mt76_desc *desc;
131 u32 ctrl;
132 int i, idx = -1;
133+ int type;
134
135 if (txwi) {
136 q->entry[q->head].txwi = DMA_DUMMY_DATA;
developera3f86ed2022-07-08 14:15:13 +0800137@@ -162,28 +237,42 @@ mt76_dma_add_buf(struct mt76_dev *dev, struct mt76_queue *q,
developer8cb3ac72022-07-04 10:55:14 +0800138 desc = &q->desc[idx];
139 entry = &q->entry[idx];
140
141- if (buf[0].skip_unmap)
142- entry->skip_buf0 = true;
143- entry->skip_buf1 = i == nbufs - 1;
144-
145- entry->dma_addr[0] = buf[0].addr;
146- entry->dma_len[0] = buf[0].len;
147-
148- ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, buf[0].len);
149- if (i < nbufs - 1) {
150- entry->dma_addr[1] = buf[1].addr;
151- entry->dma_len[1] = buf[1].len;
152- buf1 = buf[1].addr;
153- ctrl |= FIELD_PREP(MT_DMA_CTL_SD_LEN1, buf[1].len);
154- if (buf[1].skip_unmap)
155- entry->skip_buf1 = true;
156+ type = FIELD_GET(MT_QFLAG_WED_TYPE, q->flags);
157+ if (mtk_wed_device_active(wed) && type == MT76_WED_Q_RX) {
158+ struct mt76_txwi_cache *r = rxwi;
159+ int rx_token;
160+
161+ if (!r)
162+ return -ENOMEM;
163+
164+ rx_token = mt76_rx_token_consume(dev, (void *)skb, r, buf[0].addr);
165+
166+ buf1 |= FIELD_PREP(MT_DMA_CTL_TOKEN, rx_token);
167+ ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, MTK_WED_RX_PKT_SIZE);
168+ ctrl |= MT_DMA_CTL_TO_HOST;
169+ } else {
170+ if (buf[0].skip_unmap)
171+ entry->skip_buf0 = true;
172+ entry->skip_buf1 = i == nbufs - 1;
173+
174+ entry->dma_addr[0] = buf[0].addr;
175+ entry->dma_len[0] = buf[0].len;
176+
177+ ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, buf[0].len);
178+ if (i < nbufs - 1) {
179+ entry->dma_addr[1] = buf[1].addr;
180+ entry->dma_len[1] = buf[1].len;
181+ buf1 = buf[1].addr;
182+ ctrl |= FIELD_PREP(MT_DMA_CTL_SD_LEN1, buf[1].len);
183+ if (buf[1].skip_unmap)
184+ entry->skip_buf1 = true;
185+ }
186+ if (i == nbufs - 1)
187+ ctrl |= MT_DMA_CTL_LAST_SEC0;
188+ else if (i == nbufs - 2)
189+ ctrl |= MT_DMA_CTL_LAST_SEC1;
190 }
191
192- if (i == nbufs - 1)
193- ctrl |= MT_DMA_CTL_LAST_SEC0;
194- else if (i == nbufs - 2)
195- ctrl |= MT_DMA_CTL_LAST_SEC1;
196-
197 WRITE_ONCE(desc->buf0, cpu_to_le32(buf0));
198 WRITE_ONCE(desc->buf1, cpu_to_le32(buf1));
199 WRITE_ONCE(desc->info, cpu_to_le32(info));
developerc32bdb22022-07-20 16:15:39 +0800200@@ -272,33 +361,65 @@ mt76_dma_tx_cleanup(struct mt76_dev *dev, struct mt76_queue *q, bool flush)
developer8cb3ac72022-07-04 10:55:14 +0800201
202 static void *
203 mt76_dma_get_buf(struct mt76_dev *dev, struct mt76_queue *q, int idx,
204- int *len, u32 *info, bool *more)
205+ int *len, u32 *info, bool *more, bool *drop)
206 {
207 struct mt76_queue_entry *e = &q->entry[idx];
208 struct mt76_desc *desc = &q->desc[idx];
209 dma_addr_t buf_addr;
developerc32bdb22022-07-20 16:15:39 +0800210- void *buf = e->buf;
211+ void *buf = e->buf, *copy = NULL;
developer8cb3ac72022-07-04 10:55:14 +0800212 int buf_len = SKB_WITH_OVERHEAD(q->buf_size);
213+ struct mtk_wed_device *wed = &dev->mmio.wed;
214+ int type;
215
216- buf_addr = e->dma_addr[0];
217 if (len) {
218 u32 ctl = le32_to_cpu(READ_ONCE(desc->ctrl));
219 *len = FIELD_GET(MT_DMA_CTL_SD_LEN0, ctl);
220 *more = !(ctl & MT_DMA_CTL_LAST_SEC0);
221 }
222
223- if (info)
224- *info = le32_to_cpu(desc->info);
225+ type = FIELD_GET(MT_QFLAG_WED_TYPE, q->flags);
226+ if (mtk_wed_device_active(wed) && type == MT76_WED_Q_RX) {
227+ u32 token;
228+ struct mt76_txwi_cache *r;
229+
230+ token = FIELD_GET(MT_DMA_CTL_TOKEN, desc->buf1);
231+
232+ r = mt76_rx_token_release(dev, token);
233+ if (!r)
234+ return NULL;
235+
236+ buf = page_frag_alloc(&q->rx_page, q->buf_size, GFP_ATOMIC);
237+ if (!buf)
238+ return NULL;
239+
developerc32bdb22022-07-20 16:15:39 +0800240+ copy = r->buf;
developer8cb3ac72022-07-04 10:55:14 +0800241+ buf_addr = r->dma_addr;
242+ buf_len = MTK_WED_RX_PKT_SIZE;
243+ r->dma_addr = 0;
developer8cb3ac72022-07-04 10:55:14 +0800244+
245+ mt76_put_rxwi(dev, r);
246+
247+ if (desc->ctrl & (MT_DMA_CTL_TO_HOST_A | MT_DMA_CTL_DROP))
248+ *drop = true;
249+ } else {
250+ buf_addr = e->dma_addr[0];
251+ e->buf = NULL;
252+ }
253
254 dma_unmap_single(dev->dma_dev, buf_addr, buf_len, DMA_FROM_DEVICE);
255- e->buf = NULL;
256+
developerc32bdb22022-07-20 16:15:39 +0800257+ if (copy)
258+ memcpy(buf, copy, MTK_WED_RX_PKT_SIZE);
259+
developer8cb3ac72022-07-04 10:55:14 +0800260+ if (info)
261+ *info = le32_to_cpu(desc->info);
262
263 return buf;
264 }
265
266 static void *
267 mt76_dma_dequeue(struct mt76_dev *dev, struct mt76_queue *q, bool flush,
268- int *len, u32 *info, bool *more)
269+ int *len, u32 *info, bool *more, bool *drop)
270 {
271 int idx = q->tail;
272
developerbbca0f92022-07-26 17:26:12 +0800273@@ -314,7 +435,7 @@ mt76_dma_dequeue(struct mt76_dev *dev, struct mt76_queue *q, bool flush,
developer8cb3ac72022-07-04 10:55:14 +0800274 q->tail = (q->tail + 1) % q->ndesc;
275 q->queued--;
276
277- return mt76_dma_get_buf(dev, q, idx, len, info, more);
278+ return mt76_dma_get_buf(dev, q, idx, len, info, more, drop);
279 }
280
281 static int
developerbbca0f92022-07-26 17:26:12 +0800282@@ -336,7 +457,7 @@ mt76_dma_tx_queue_skb_raw(struct mt76_dev *dev, struct mt76_queue *q,
developer8cb3ac72022-07-04 10:55:14 +0800283 buf.len = skb->len;
284
285 spin_lock_bh(&q->lock);
286- mt76_dma_add_buf(dev, q, &buf, 1, tx_info, skb, NULL);
287+ mt76_dma_add_buf(dev, q, &buf, 1, tx_info, skb, NULL, NULL);
288 mt76_dma_kick_queue(dev, q);
289 spin_unlock_bh(&q->lock);
290
developerbbca0f92022-07-26 17:26:12 +0800291@@ -413,7 +534,7 @@ mt76_dma_tx_queue_skb(struct mt76_dev *dev, struct mt76_queue *q,
developer8cb3ac72022-07-04 10:55:14 +0800292 goto unmap;
293
294 return mt76_dma_add_buf(dev, q, tx_info.buf, tx_info.nbuf,
295- tx_info.info, tx_info.skb, t);
296+ tx_info.info, tx_info.skb, t, NULL);
297
298 unmap:
299 for (n--; n > 0; n--)
developerbbca0f92022-07-26 17:26:12 +0800300@@ -448,6 +569,8 @@ mt76_dma_rx_fill(struct mt76_dev *dev, struct mt76_queue *q)
developer8cb3ac72022-07-04 10:55:14 +0800301 int frames = 0;
302 int len = SKB_WITH_OVERHEAD(q->buf_size);
303 int offset = q->buf_offset;
304+ struct mtk_wed_device *wed = &dev->mmio.wed;
developera3f86ed2022-07-08 14:15:13 +0800305+ struct page_frag_cache *rx_page;
developer8cb3ac72022-07-04 10:55:14 +0800306
307 if (!q->ndesc)
308 return 0;
developerbbca0f92022-07-26 17:26:12 +0800309@@ -456,10 +579,29 @@ mt76_dma_rx_fill(struct mt76_dev *dev, struct mt76_queue *q)
developer8cb3ac72022-07-04 10:55:14 +0800310
311 while (q->queued < q->ndesc - 1) {
312 struct mt76_queue_buf qbuf;
313+ int type = FIELD_GET(MT_QFLAG_WED_TYPE, q->flags);
314+ bool skip_alloc = false;
315+ struct mt76_txwi_cache *r = NULL;
316+
developera3f86ed2022-07-08 14:15:13 +0800317+ rx_page = &q->rx_page;
developer8cb3ac72022-07-04 10:55:14 +0800318+ if (mtk_wed_device_active(wed) && type == MT76_WED_Q_RX) {
developera3f86ed2022-07-08 14:15:13 +0800319+ rx_page = &wed->rx_page;
developer8cb3ac72022-07-04 10:55:14 +0800320+ r = mt76_get_rxwi(dev);
321+ if (!r)
322+ return -ENOMEM;
323+
324+ if (r->buf) {
325+ skip_alloc = true;
326+ len = MTK_WED_RX_PKT_SIZE;
327+ buf = r->buf;
328+ }
329+ }
330
331- buf = page_frag_alloc(&q->rx_page, q->buf_size, GFP_ATOMIC);
332- if (!buf)
333- break;
334+ if (!skip_alloc) {
developera3f86ed2022-07-08 14:15:13 +0800335+ buf = page_frag_alloc(rx_page, q->buf_size, GFP_ATOMIC);
developer8cb3ac72022-07-04 10:55:14 +0800336+ if (!buf)
337+ break;
338+ }
339
340 addr = dma_map_single(dev->dma_dev, buf, len, DMA_FROM_DEVICE);
341 if (unlikely(dma_mapping_error(dev->dma_dev, addr))) {
developerbbca0f92022-07-26 17:26:12 +0800342@@ -470,7 +612,7 @@ mt76_dma_rx_fill(struct mt76_dev *dev, struct mt76_queue *q)
developer8cb3ac72022-07-04 10:55:14 +0800343 qbuf.addr = addr + offset;
344 qbuf.len = len - offset;
345 qbuf.skip_unmap = false;
346- mt76_dma_add_buf(dev, q, &qbuf, 1, 0, buf, NULL);
347+ mt76_dma_add_buf(dev, q, &qbuf, 1, 0, buf, NULL, r);
348 frames++;
349 }
350
developerbbca0f92022-07-26 17:26:12 +0800351@@ -516,6 +658,11 @@ mt76_dma_wed_setup(struct mt76_dev *dev, struct mt76_queue *q)
developer8cb3ac72022-07-04 10:55:14 +0800352 if (!ret)
353 q->wed_regs = wed->txfree_ring.reg_base;
354 break;
355+ case MT76_WED_Q_RX:
356+ ret = mtk_wed_device_rx_ring_setup(wed, ring, q->regs);
357+ if (!ret)
358+ q->wed_regs = wed->rx_ring[ring].reg_base;
359+ break;
360 default:
361 ret = -EINVAL;
362 }
developerbbca0f92022-07-26 17:26:12 +0800363@@ -531,7 +678,8 @@ mt76_dma_alloc_queue(struct mt76_dev *dev, struct mt76_queue *q,
developer8cb3ac72022-07-04 10:55:14 +0800364 int idx, int n_desc, int bufsize,
365 u32 ring_base)
366 {
367- int ret, size;
368+ int ret, size, type;
369+ struct mtk_wed_device *wed = &dev->mmio.wed;
370
371 spin_lock_init(&q->lock);
372 spin_lock_init(&q->cleanup_lock);
developerbbca0f92022-07-26 17:26:12 +0800373@@ -541,6 +689,11 @@ mt76_dma_alloc_queue(struct mt76_dev *dev, struct mt76_queue *q,
developer8cb3ac72022-07-04 10:55:14 +0800374 q->buf_size = bufsize;
375 q->hw_idx = idx;
376
377+ type = FIELD_GET(MT_QFLAG_WED_TYPE, q->flags);
378+ if (mtk_wed_device_active(wed) && type == MT76_WED_Q_RX)
379+ q->buf_size = SKB_DATA_ALIGN(NET_SKB_PAD + MTK_WED_RX_PKT_SIZE) +
380+ SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
381+
382 size = q->ndesc * sizeof(struct mt76_desc);
383 q->desc = dmam_alloc_coherent(dev->dma_dev, size, &q->desc_dma, GFP_KERNEL);
384 if (!q->desc)
developerbbca0f92022-07-26 17:26:12 +0800385@@ -573,7 +726,7 @@ mt76_dma_rx_cleanup(struct mt76_dev *dev, struct mt76_queue *q)
developer8cb3ac72022-07-04 10:55:14 +0800386
387 spin_lock_bh(&q->lock);
388 do {
389- buf = mt76_dma_dequeue(dev, q, true, NULL, NULL, &more);
390+ buf = mt76_dma_dequeue(dev, q, true, NULL, NULL, &more, NULL);
391 if (!buf)
392 break;
393
developerbbca0f92022-07-26 17:26:12 +0800394@@ -614,7 +767,7 @@ mt76_dma_rx_reset(struct mt76_dev *dev, enum mt76_rxq_id qid)
developer8cb3ac72022-07-04 10:55:14 +0800395
396 static void
397 mt76_add_fragment(struct mt76_dev *dev, struct mt76_queue *q, void *data,
398- int len, bool more)
399+ int len, bool more, u32 info)
400 {
401 struct sk_buff *skb = q->rx_head;
402 struct skb_shared_info *shinfo = skb_shinfo(skb);
developerbbca0f92022-07-26 17:26:12 +0800403@@ -634,7 +787,7 @@ mt76_add_fragment(struct mt76_dev *dev, struct mt76_queue *q, void *data,
developer8cb3ac72022-07-04 10:55:14 +0800404
405 q->rx_head = NULL;
406 if (nr_frags < ARRAY_SIZE(shinfo->frags))
407- dev->drv->rx_skb(dev, q - dev->q_rx, skb);
408+ dev->drv->rx_skb(dev, q - dev->q_rx, skb, info);
409 else
410 dev_kfree_skb(skb);
411 }
developerbbca0f92022-07-26 17:26:12 +0800412@@ -655,6 +808,7 @@ mt76_dma_rx_process(struct mt76_dev *dev, struct mt76_queue *q, int budget)
developer8cb3ac72022-07-04 10:55:14 +0800413 }
414
415 while (done < budget) {
416+ bool drop = false;
417 u32 info;
418
419 if (check_ddone) {
developerbbca0f92022-07-26 17:26:12 +0800420@@ -665,10 +819,13 @@ mt76_dma_rx_process(struct mt76_dev *dev, struct mt76_queue *q, int budget)
developer8cb3ac72022-07-04 10:55:14 +0800421 break;
422 }
423
424- data = mt76_dma_dequeue(dev, q, false, &len, &info, &more);
425+ data = mt76_dma_dequeue(dev, q, false, &len, &info, &more, &drop);
426 if (!data)
427 break;
428
429+ if (drop)
430+ goto free_frag;
431+
432 if (q->rx_head)
433 data_len = q->buf_size;
434 else
developerbbca0f92022-07-26 17:26:12 +0800435@@ -681,7 +838,7 @@ mt76_dma_rx_process(struct mt76_dev *dev, struct mt76_queue *q, int budget)
developer8cb3ac72022-07-04 10:55:14 +0800436 }
437
438 if (q->rx_head) {
439- mt76_add_fragment(dev, q, data, len, more);
440+ mt76_add_fragment(dev, q, data, len, more, info);
441 continue;
442 }
443
developer81ca9d62022-10-14 11:23:22 +0800444@@ -705,7 +862,7 @@ mt76_dma_rx_process(struct mt76_dev *dev, struct mt76_queue *q, int budget)
developer8cb3ac72022-07-04 10:55:14 +0800445 continue;
446 }
447
448- dev->drv->rx_skb(dev, q - dev->q_rx, skb);
449+ dev->drv->rx_skb(dev, q - dev->q_rx, skb, info);
450 continue;
451
452 free_frag:
developer81ca9d62022-10-14 11:23:22 +0800453@@ -782,7 +939,7 @@ EXPORT_SYMBOL_GPL(mt76_dma_attach);
developera3f86ed2022-07-08 14:15:13 +0800454
455 void mt76_dma_cleanup(struct mt76_dev *dev)
456 {
457- int i;
developera3f86ed2022-07-08 14:15:13 +0800458+ int i, type;
developerd59e4772022-07-14 13:48:49 +0800459
developera3f86ed2022-07-08 14:15:13 +0800460 mt76_worker_disable(&dev->tx_worker);
461 netif_napi_del(&dev->tx_napi);
developer81ca9d62022-10-14 11:23:22 +0800462@@ -803,12 +960,17 @@ void mt76_dma_cleanup(struct mt76_dev *dev)
developera3f86ed2022-07-08 14:15:13 +0800463
464 mt76_for_each_q_rx(dev, i) {
465 netif_napi_del(&dev->napi[i]);
466- mt76_dma_rx_cleanup(dev, &dev->q_rx[i]);
467+ type = FIELD_GET(MT_QFLAG_WED_TYPE, dev->q_rx[i].flags);
468+ if (type != MT76_WED_Q_RX)
469+ mt76_dma_rx_cleanup(dev, &dev->q_rx[i]);
470 }
471
472 mt76_free_pending_txwi(dev);
473+ mt76_free_pending_rxwi(dev);
474
475 if (mtk_wed_device_active(&dev->mmio.wed))
476 mtk_wed_device_detach(&dev->mmio.wed);
477+
478+ mt76_free_pending_rxwi(dev);
479 }
480 EXPORT_SYMBOL_GPL(mt76_dma_cleanup);
developer8cb3ac72022-07-04 10:55:14 +0800481diff --git a/dma.h b/dma.h
developer29647af2022-11-15 18:09:16 +0800482index fdf786f..90370d1 100644
developer8cb3ac72022-07-04 10:55:14 +0800483--- a/dma.h
484+++ b/dma.h
485@@ -16,6 +16,16 @@
486 #define MT_DMA_CTL_LAST_SEC0 BIT(30)
487 #define MT_DMA_CTL_DMA_DONE BIT(31)
488
489+#define MT_DMA_CTL_TO_HOST BIT(8)
490+#define MT_DMA_CTL_TO_HOST_A BIT(12)
491+#define MT_DMA_CTL_DROP BIT(14)
492+
493+#define MT_DMA_CTL_TOKEN GENMASK(31, 16)
494+
495+#define MT_DMA_PPE_CPU_REASON GENMASK(15, 11)
496+#define MT_DMA_PPE_ENTRY GENMASK(30, 16)
497+#define MT_DMA_INFO_PPE_VLD BIT(31)
498+
499 #define MT_DMA_HDR_LEN 4
500 #define MT_RX_INFO_LEN 4
501 #define MT_FCE_INFO_LEN 4
502diff --git a/mac80211.c b/mac80211.c
developer29647af2022-11-15 18:09:16 +0800503index c84c9ef..32961b6 100644
developer8cb3ac72022-07-04 10:55:14 +0800504--- a/mac80211.c
505+++ b/mac80211.c
developerc226de82022-10-03 12:24:57 +0800506@@ -603,11 +603,14 @@ mt76_alloc_device(struct device *pdev, unsigned int size,
developer8cb3ac72022-07-04 10:55:14 +0800507 BIT(NL80211_IFTYPE_ADHOC);
508
509 spin_lock_init(&dev->token_lock);
510+ spin_lock_init(&dev->rx_token_lock);
511 idr_init(&dev->token);
512+ idr_init(&dev->rx_token);
513
514 INIT_LIST_HEAD(&dev->wcid_list);
515
516 INIT_LIST_HEAD(&dev->txwi_cache);
517+ INIT_LIST_HEAD(&dev->rxwi_cache);
518 dev->token_size = dev->drv->token_size;
519
520 for (i = 0; i < ARRAY_SIZE(dev->q_rx); i++)
developer356ecec2022-11-14 10:25:04 +0800521@@ -1304,7 +1307,10 @@ void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q,
developer8cb3ac72022-07-04 10:55:14 +0800522
523 while ((skb = __skb_dequeue(&dev->rx_skb[q])) != NULL) {
524 mt76_check_sta(dev, skb);
525- mt76_rx_aggr_reorder(skb, &frames);
526+ if (mtk_wed_device_active(&dev->mmio.wed))
527+ __skb_queue_tail(&frames, skb);
528+ else
529+ mt76_rx_aggr_reorder(skb, &frames);
530 }
531
532 mt76_rx_complete(dev, &frames, napi);
533diff --git a/mt76.h b/mt76.h
developer29647af2022-11-15 18:09:16 +0800534index b86c835..627bcbf 100644
developer8cb3ac72022-07-04 10:55:14 +0800535--- a/mt76.h
536+++ b/mt76.h
537@@ -20,6 +20,8 @@
538
539 #define MT_MCU_RING_SIZE 32
540 #define MT_RX_BUF_SIZE 2048
541+#define MTK_WED_RX_PKT_SIZE 1700
542+
543 #define MT_SKB_HEAD_LEN 256
544
545 #define MT_MAX_NON_AQL_PKT 16
546@@ -35,6 +37,7 @@
547 FIELD_PREP(MT_QFLAG_WED_TYPE, _type) | \
548 FIELD_PREP(MT_QFLAG_WED_RING, _n))
549 #define MT_WED_Q_TX(_n) __MT_WED_Q(MT76_WED_Q_TX, _n)
550+#define MT_WED_Q_RX(_n) __MT_WED_Q(MT76_WED_Q_RX, _n)
551 #define MT_WED_Q_TXFREE __MT_WED_Q(MT76_WED_Q_TXFREE, 0)
552
553 struct mt76_dev;
554@@ -56,6 +59,7 @@ enum mt76_bus_type {
555 enum mt76_wed_type {
556 MT76_WED_Q_TX,
557 MT76_WED_Q_TXFREE,
558+ MT76_WED_Q_RX,
559 };
560
561 struct mt76_bus_ops {
developer20747c12022-09-16 14:09:40 +0800562@@ -339,7 +343,10 @@ struct mt76_txwi_cache {
developer8cb3ac72022-07-04 10:55:14 +0800563 struct list_head list;
564 dma_addr_t dma_addr;
565
566- struct sk_buff *skb;
567+ union {
568+ void *buf;
569+ struct sk_buff *skb;
570+ };
571 };
572
573 struct mt76_rx_tid {
developerc226de82022-10-03 12:24:57 +0800574@@ -439,7 +446,7 @@ struct mt76_driver_ops {
developer8cb3ac72022-07-04 10:55:14 +0800575 bool (*rx_check)(struct mt76_dev *dev, void *data, int len);
576
577 void (*rx_skb)(struct mt76_dev *dev, enum mt76_rxq_id q,
578- struct sk_buff *skb);
579+ struct sk_buff *skb, u32 info);
580
581 void (*rx_poll_complete)(struct mt76_dev *dev, enum mt76_rxq_id q);
582
developer356ecec2022-11-14 10:25:04 +0800583@@ -782,6 +789,7 @@ struct mt76_dev {
developer8cb3ac72022-07-04 10:55:14 +0800584 struct ieee80211_hw *hw;
585
586 spinlock_t lock;
587+ spinlock_t wed_lock;
588 spinlock_t cc_lock;
589
590 u32 cur_cc_bss_rx;
developer356ecec2022-11-14 10:25:04 +0800591@@ -807,6 +815,7 @@ struct mt76_dev {
developer8cb3ac72022-07-04 10:55:14 +0800592 struct sk_buff_head rx_skb[__MT_RXQ_MAX];
593
594 struct list_head txwi_cache;
595+ struct list_head rxwi_cache;
596 struct mt76_queue *q_mcu[__MT_MCUQ_MAX];
597 struct mt76_queue q_rx[__MT_RXQ_MAX];
598 const struct mt76_queue_ops *queue_ops;
developer356ecec2022-11-14 10:25:04 +0800599@@ -820,6 +829,9 @@ struct mt76_dev {
developer8cb3ac72022-07-04 10:55:14 +0800600 u16 wed_token_count;
601 u16 token_count;
602 u16 token_size;
603+ u16 rx_token_size;
604+ spinlock_t rx_token_lock;
605+ struct idr rx_token;
606
607 wait_queue_head_t tx_wait;
608 /* spinclock used to protect wcid pktid linked list */
developer356ecec2022-11-14 10:25:04 +0800609@@ -1361,6 +1373,8 @@ mt76_tx_status_get_hw(struct mt76_dev *dev, struct sk_buff *skb)
developer8cb3ac72022-07-04 10:55:14 +0800610 }
611
612 void mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t);
613+void mt76_put_rxwi(struct mt76_dev *dev, struct mt76_txwi_cache *t);
614+struct mt76_txwi_cache *mt76_get_rxwi(struct mt76_dev *dev);
615 void mt76_rx_complete(struct mt76_dev *dev, struct sk_buff_head *frames,
616 struct napi_struct *napi);
617 void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q,
developer356ecec2022-11-14 10:25:04 +0800618@@ -1505,6 +1519,12 @@ struct mt76_txwi_cache *
developer8cb3ac72022-07-04 10:55:14 +0800619 mt76_token_release(struct mt76_dev *dev, int token, bool *wake);
620 int mt76_token_consume(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi);
621 void __mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked);
622+int mt76_rx_token_consume(struct mt76_dev *dev, void *ptr,
623+ struct mt76_txwi_cache *r, dma_addr_t phys);
624+void skb_trace(const struct sk_buff *skb, bool full_pkt);
625+
626+struct mt76_txwi_cache *
627+mt76_rx_token_release(struct mt76_dev *dev, int token);
628
629 static inline void mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked)
630 {
631diff --git a/mt7603/dma.c b/mt7603/dma.c
developer29647af2022-11-15 18:09:16 +0800632index 590cff9..2ff71c5 100644
developer8cb3ac72022-07-04 10:55:14 +0800633--- a/mt7603/dma.c
634+++ b/mt7603/dma.c
635@@ -69,7 +69,7 @@ free:
636 }
637
638 void mt7603_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
639- struct sk_buff *skb)
640+ struct sk_buff *skb, u32 info)
641 {
642 struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76);
643 __le32 *rxd = (__le32 *)skb->data;
644diff --git a/mt7603/mt7603.h b/mt7603/mt7603.h
developer29647af2022-11-15 18:09:16 +0800645index 0fd46d9..f2ce22a 100644
developer8cb3ac72022-07-04 10:55:14 +0800646--- a/mt7603/mt7603.h
647+++ b/mt7603/mt7603.h
648@@ -244,7 +244,7 @@ int mt7603_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
649 void mt7603_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue_entry *e);
650
651 void mt7603_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
652- struct sk_buff *skb);
653+ struct sk_buff *skb, u32 info);
654 void mt7603_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q);
655 void mt7603_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps);
656 int mt7603_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif,
657diff --git a/mt7615/mac.c b/mt7615/mac.c
developer29647af2022-11-15 18:09:16 +0800658index 305bf18..4aed123 100644
developer8cb3ac72022-07-04 10:55:14 +0800659--- a/mt7615/mac.c
660+++ b/mt7615/mac.c
developer356ecec2022-11-14 10:25:04 +0800661@@ -1666,7 +1666,7 @@ bool mt7615_rx_check(struct mt76_dev *mdev, void *data, int len)
developer8cb3ac72022-07-04 10:55:14 +0800662 EXPORT_SYMBOL_GPL(mt7615_rx_check);
663
664 void mt7615_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
665- struct sk_buff *skb)
666+ struct sk_buff *skb, u32 info)
667 {
668 struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
669 __le32 *rxd = (__le32 *)skb->data;
670diff --git a/mt7615/mt7615.h b/mt7615/mt7615.h
developer29647af2022-11-15 18:09:16 +0800671index 1080d20..91b3037 100644
developer8cb3ac72022-07-04 10:55:14 +0800672--- a/mt7615/mt7615.h
673+++ b/mt7615/mt7615.h
developer356ecec2022-11-14 10:25:04 +0800674@@ -514,7 +514,7 @@ void mt7615_tx_worker(struct mt76_worker *w);
developer8cb3ac72022-07-04 10:55:14 +0800675 void mt7615_tx_token_put(struct mt7615_dev *dev);
676 bool mt7615_rx_check(struct mt76_dev *mdev, void *data, int len);
677 void mt7615_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
678- struct sk_buff *skb);
679+ struct sk_buff *skb, u32 info);
680 void mt7615_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps);
681 int mt7615_mac_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif,
682 struct ieee80211_sta *sta);
683diff --git a/mt76_connac_mcu.c b/mt76_connac_mcu.c
developer29647af2022-11-15 18:09:16 +0800684index afdd42f..1b01ef2 100644
developer8cb3ac72022-07-04 10:55:14 +0800685--- a/mt76_connac_mcu.c
686+++ b/mt76_connac_mcu.c
developer20747c12022-09-16 14:09:40 +0800687@@ -1192,6 +1192,7 @@ int mt76_connac_mcu_sta_ba(struct mt76_dev *dev, struct mt76_vif *mvif,
developer8cb3ac72022-07-04 10:55:14 +0800688 int cmd, bool enable, bool tx)
689 {
690 struct mt76_wcid *wcid = (struct mt76_wcid *)params->sta->drv_priv;
691+ struct mtk_wed_device *wed = &dev->mmio.wed;
692 struct wtbl_req_hdr *wtbl_hdr;
693 struct tlv *sta_wtbl;
694 struct sk_buff *skb;
developer20747c12022-09-16 14:09:40 +0800695@@ -1212,6 +1213,8 @@ int mt76_connac_mcu_sta_ba(struct mt76_dev *dev, struct mt76_vif *mvif,
developer8cb3ac72022-07-04 10:55:14 +0800696 mt76_connac_mcu_wtbl_ba_tlv(dev, skb, params, enable, tx, sta_wtbl,
697 wtbl_hdr);
698
developerf50c1802022-07-05 20:35:53 +0800699+ if (mtk_wed_device_active(wed) && wed->ver > MTK_WED_V1)
developer6adfa0e2022-07-06 16:25:53 +0800700+ mtk_wed_device_update_msg(wed, WED_WO_STA_REC, skb->data, skb->len);
developer8cb3ac72022-07-04 10:55:14 +0800701 ret = mt76_mcu_skb_send_msg(dev, skb, cmd, true);
702 if (ret)
703 return ret;
developer20747c12022-09-16 14:09:40 +0800704@@ -1222,6 +1225,8 @@ int mt76_connac_mcu_sta_ba(struct mt76_dev *dev, struct mt76_vif *mvif,
developer8cb3ac72022-07-04 10:55:14 +0800705
706 mt76_connac_mcu_sta_ba_tlv(skb, params, enable, tx);
707
developerf50c1802022-07-05 20:35:53 +0800708+ if (mtk_wed_device_active(wed) && wed->ver > MTK_WED_V1)
709+ mtk_wed_device_update_msg(wed, WED_WO_STA_REC, skb->data, skb->len);
developer8cb3ac72022-07-04 10:55:14 +0800710 return mt76_mcu_skb_send_msg(dev, skb, cmd, true);
711 }
712 EXPORT_SYMBOL_GPL(mt76_connac_mcu_sta_ba);
developer356ecec2022-11-14 10:25:04 +0800713@@ -2651,6 +2656,7 @@ int mt76_connac_mcu_add_key(struct mt76_dev *dev, struct ieee80211_vif *vif,
developer8cb3ac72022-07-04 10:55:14 +0800714 struct mt76_wcid *wcid, enum set_key_cmd cmd)
715 {
716 struct mt76_vif *mvif = (struct mt76_vif *)vif->drv_priv;
717+ struct mtk_wed_device *wed = &dev->mmio.wed;
718 struct sk_buff *skb;
719 int ret;
720
developer356ecec2022-11-14 10:25:04 +0800721@@ -2662,6 +2668,9 @@ int mt76_connac_mcu_add_key(struct mt76_dev *dev, struct ieee80211_vif *vif,
developer8cb3ac72022-07-04 10:55:14 +0800722 if (ret)
723 return ret;
724
developerf50c1802022-07-05 20:35:53 +0800725+ if (mtk_wed_device_active(wed) && wed->ver > MTK_WED_V1)
developer8cb3ac72022-07-04 10:55:14 +0800726+ mtk_wed_device_update_msg(wed, WED_WO_STA_REC, skb->data, skb->len);
727+
728 return mt76_mcu_skb_send_msg(dev, skb, mcu_cmd, true);
729 }
730 EXPORT_SYMBOL_GPL(mt76_connac_mcu_add_key);
731diff --git a/mt76x02.h b/mt76x02.h
developer29647af2022-11-15 18:09:16 +0800732index 849c264..49112ab 100644
developer8cb3ac72022-07-04 10:55:14 +0800733--- a/mt76x02.h
734+++ b/mt76x02.h
developerc226de82022-10-03 12:24:57 +0800735@@ -187,7 +187,7 @@ int mt76x02_set_rts_threshold(struct ieee80211_hw *hw, u32 val);
developer8cb3ac72022-07-04 10:55:14 +0800736 void mt76x02_remove_hdr_pad(struct sk_buff *skb, int len);
737 bool mt76x02_tx_status_data(struct mt76_dev *mdev, u8 *update);
738 void mt76x02_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
739- struct sk_buff *skb);
740+ struct sk_buff *skb, u32 info);
741 void mt76x02_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q);
742 irqreturn_t mt76x02_irq_handler(int irq, void *dev_instance);
743 void mt76x02_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control,
744diff --git a/mt76x02_txrx.c b/mt76x02_txrx.c
developer29647af2022-11-15 18:09:16 +0800745index 3a31307..5d6c8f7 100644
developer8cb3ac72022-07-04 10:55:14 +0800746--- a/mt76x02_txrx.c
747+++ b/mt76x02_txrx.c
748@@ -33,7 +33,7 @@ void mt76x02_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control,
749 EXPORT_SYMBOL_GPL(mt76x02_tx);
750
751 void mt76x02_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
752- struct sk_buff *skb)
753+ struct sk_buff *skb, u32 info)
754 {
755 struct mt76x02_dev *dev = container_of(mdev, struct mt76x02_dev, mt76);
756 void *rxwi = skb->data;
757diff --git a/mt7915/dma.c b/mt7915/dma.c
developer29647af2022-11-15 18:09:16 +0800758index 9a57ad8..6f6550f 100644
developer8cb3ac72022-07-04 10:55:14 +0800759--- a/mt7915/dma.c
760+++ b/mt7915/dma.c
developer356ecec2022-11-14 10:25:04 +0800761@@ -365,7 +365,8 @@ static int mt7915_dma_enable(struct mt7915_dev *dev)
developer8d18bff2022-09-26 17:39:49 +0800762 wed_irq_mask |= MT_INT_TX_DONE_BAND0 | MT_INT_TX_DONE_BAND1;
763 if (!is_mt7986(&dev->mt76))
764 mt76_wr(dev, MT_INT_WED_MASK_CSR, wed_irq_mask);
765- mt76_wr(dev, MT_INT_MASK_CSR, wed_irq_mask);
766+ else
767+ mt76_wr(dev, MT_INT_MASK_CSR, wed_irq_mask);
768 mtk_wed_device_start(&dev->mt76.mmio.wed, wed_irq_mask);
769 }
developerc226de82022-10-03 12:24:57 +0800770
developer356ecec2022-11-14 10:25:04 +0800771@@ -377,6 +378,7 @@ static int mt7915_dma_enable(struct mt7915_dev *dev)
developerc1b2cd12022-07-28 18:35:24 +0800772 int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2)
773 {
774 struct mt76_dev *mdev = &dev->mt76;
775+ struct mtk_wed_device *wed = &mdev->mmio.wed;
776 u32 wa_rx_base, wa_rx_idx;
777 u32 hif1_ofs = 0;
778 int ret;
developer356ecec2022-11-14 10:25:04 +0800779@@ -401,6 +403,9 @@ int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2)
developerc226de82022-10-03 12:24:57 +0800780 FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_TX1, 19) |
781 FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_RX1,
782 wed_control_rx1));
783+ if(is_mt7915(mdev))
developerc1b2cd12022-07-28 18:35:24 +0800784+ mt76_rmw(dev, MT_WFDMA0_EXT0_CFG, MT_WFDMA0_EXT0_RXWB_KEEP,
developerc226de82022-10-03 12:24:57 +0800785+ MT_WFDMA0_EXT0_RXWB_KEEP);
786 }
787 } else {
788 mt76_clear(dev, MT_WFDMA_HOST_CONFIG, MT_WFDMA_HOST_CONFIG_WED);
developer356ecec2022-11-14 10:25:04 +0800789@@ -473,6 +478,11 @@ int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2)
developer8cb3ac72022-07-04 10:55:14 +0800790
791 /* rx data queue for band0 */
792 if (!dev->phy.band_idx) {
developerc1b2cd12022-07-28 18:35:24 +0800793+ if (mtk_wed_device_active(wed) && wed->ver > MTK_WED_V1) {
developer8cb3ac72022-07-04 10:55:14 +0800794+ dev->mt76.q_rx[MT_RXQ_MAIN].flags = MT_WED_Q_RX(MT7915_RXQ_BAND0);
developerc1b2cd12022-07-28 18:35:24 +0800795+ dev->mt76.rx_token_size += MT7915_RX_RING_SIZE;
796+ }
developer8cb3ac72022-07-04 10:55:14 +0800797+
798 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN],
799 MT_RXQ_ID(MT_RXQ_MAIN),
800 MT7915_RX_RING_SIZE,
developer356ecec2022-11-14 10:25:04 +0800801@@ -503,6 +513,11 @@ int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2)
developer1d9fede2022-08-29 15:24:07 +0800802 }
developer8cb3ac72022-07-04 10:55:14 +0800803
804 if (dev->dbdc_support || dev->phy.band_idx) {
developerc1b2cd12022-07-28 18:35:24 +0800805+ if (mtk_wed_device_active(wed) && wed->ver > MTK_WED_V1) {
developer1d9fede2022-08-29 15:24:07 +0800806+ dev->mt76.q_rx[MT_RXQ_BAND1].flags = MT_WED_Q_RX(MT7915_RXQ_BAND1);
developerc1b2cd12022-07-28 18:35:24 +0800807+ dev->mt76.rx_token_size += MT7915_RX_RING_SIZE;
808+ }
developer8cb3ac72022-07-04 10:55:14 +0800809+
developer1d9fede2022-08-29 15:24:07 +0800810 /* rx data queue for band1 */
811 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_BAND1],
812 MT_RXQ_ID(MT_RXQ_BAND1),
developer8cb3ac72022-07-04 10:55:14 +0800813diff --git a/mt7915/mac.c b/mt7915/mac.c
developer29647af2022-11-15 18:09:16 +0800814index 20e5b70..eac4946 100644
developer8cb3ac72022-07-04 10:55:14 +0800815--- a/mt7915/mac.c
816+++ b/mt7915/mac.c
developer356ecec2022-11-14 10:25:04 +0800817@@ -247,7 +247,7 @@ void mt7915_mac_enable_rtscts(struct mt7915_dev *dev,
developer8cb3ac72022-07-04 10:55:14 +0800818 }
819
820 static int
821-mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
822+mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb, enum mt76_rxq_id q, u32 info)
823 {
824 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
825 struct mt76_phy *mphy = &dev->mt76.phy;
developer356ecec2022-11-14 10:25:04 +0800826@@ -526,6 +526,27 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
developer8cb3ac72022-07-04 10:55:14 +0800827 #endif
828 } else {
829 status->flag |= RX_FLAG_8023;
developera3f86ed2022-07-08 14:15:13 +0800830+ if (msta && msta->vif) {
developer8cb3ac72022-07-04 10:55:14 +0800831+ struct mtk_wed_device *wed;
832+ int type;
833+
834+ wed = &dev->mt76.mmio.wed;
835+ type = FIELD_GET(MT_QFLAG_WED_TYPE, dev->mt76.q_rx[q].flags);
836+ if ((mtk_wed_device_active(wed) && type == MT76_WED_Q_RX) &&
developera3f86ed2022-07-08 14:15:13 +0800837+ (info & MT_DMA_INFO_PPE_VLD)) {
developer8cb3ac72022-07-04 10:55:14 +0800838+ struct ieee80211_vif *vif;
839+ u32 hash, reason;
840+
841+ vif = container_of((void *)msta->vif, struct ieee80211_vif,
developera3f86ed2022-07-08 14:15:13 +0800842+ drv_priv);
developer8cb3ac72022-07-04 10:55:14 +0800843+
844+ skb->dev = ieee80211_vif_to_netdev(vif);
845+ reason = FIELD_GET(MT_DMA_PPE_CPU_REASON, info);
846+ hash = FIELD_GET(MT_DMA_PPE_ENTRY, info);
847+
848+ mtk_wed_device_ppe_check(wed, skb, reason, hash);
849+ }
850+ }
851 }
852
853 if (rxv && mode >= MT_PHY_TYPE_HE_SU && !(status->flag & RX_FLAG_8023))
developer356ecec2022-11-14 10:25:04 +0800854@@ -863,6 +884,80 @@ u32 mt7915_wed_init_buf(void *ptr, dma_addr_t phys, int token_id)
developer8cb3ac72022-07-04 10:55:14 +0800855 return MT_TXD_TXP_BUF_SIZE;
856 }
857
858+u32
859+mt7915_wed_init_rx_buf(struct mtk_wed_device *wed, int pkt_num)
860+{
861+ struct mtk_rxbm_desc *desc = wed->rx_buf_ring.desc;
862+ struct mt7915_dev *dev;
863+ dma_addr_t buf_phys;
864+ void *buf;
865+ int i, token, buf_size;
866+
867+ buf_size = SKB_DATA_ALIGN(NET_SKB_PAD + wed->wlan.rx_pkt_size) +
868+ SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
869+
870+ dev = container_of(wed, struct mt7915_dev, mt76.mmio.wed);
871+ for (i = 0; i < pkt_num; i++) {
872+ struct mt76_txwi_cache *r = mt76_get_rxwi(&dev->mt76);
873+
874+ buf = page_frag_alloc(&wed->rx_page, buf_size, GFP_ATOMIC);
875+ if (!buf)
876+ return -ENOMEM;
877+
878+ buf_phys = dma_map_single(dev->mt76.dma_dev, buf, wed->wlan.rx_pkt_size,
879+ DMA_TO_DEVICE);
880+
881+ if (unlikely(dma_mapping_error(dev->mt76.dev, buf_phys))) {
882+ skb_free_frag(buf);
883+ break;
884+ }
885+
886+ desc->buf0 = buf_phys;
887+
888+ token = mt76_rx_token_consume(&dev->mt76, buf, r, buf_phys);
889+
890+ desc->token |= FIELD_PREP(MT_DMA_CTL_TOKEN, token);
891+ desc++;
892+ }
893+
894+ return 0;
895+}
896+
897+void mt7915_wed_release_rx_buf(struct mtk_wed_device *wed)
898+{
899+ struct mt76_txwi_cache *rxwi;
900+ struct mt7915_dev *dev;
developera3f86ed2022-07-08 14:15:13 +0800901+ struct page *page;
developer8cb3ac72022-07-04 10:55:14 +0800902+ int token;
903+
904+ dev = container_of(wed, struct mt7915_dev, mt76.mmio.wed);
905+
906+ for(token = 0; token < dev->mt76.rx_token_size; token++) {
907+ rxwi = mt76_rx_token_release(&dev->mt76, token);
908+ if(!rxwi)
909+ continue;
910+
developera3f86ed2022-07-08 14:15:13 +0800911+ if(!rxwi->buf)
912+ continue;
913+
developer8cb3ac72022-07-04 10:55:14 +0800914+ dma_unmap_single(dev->mt76.dma_dev, rxwi->dma_addr,
915+ wed->wlan.rx_pkt_size, DMA_FROM_DEVICE);
916+ skb_free_frag(rxwi->buf);
917+ rxwi->buf = NULL;
918+
919+ mt76_put_rxwi(&dev->mt76, rxwi);
920+ }
developera3f86ed2022-07-08 14:15:13 +0800921+
922+ if (wed->rx_page.va)
923+ return;
924+
925+ page = virt_to_page(wed->rx_page.va);
926+ __page_frag_cache_drain(page, wed->rx_page.pagecnt_bias);
927+ memset(&wed->rx_page, 0, sizeof(wed->rx_page));
928+
developer8cb3ac72022-07-04 10:55:14 +0800929+ return;
930+}
931+
932 static void
933 mt7915_tx_check_aggr(struct ieee80211_sta *sta, __le32 *txwi)
934 {
developer356ecec2022-11-14 10:25:04 +0800935@@ -1147,7 +1242,7 @@ bool mt7915_rx_check(struct mt76_dev *mdev, void *data, int len)
developer8cb3ac72022-07-04 10:55:14 +0800936 }
937
938 void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
939- struct sk_buff *skb)
940+ struct sk_buff *skb, u32 info)
941 {
942 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
943 __le32 *rxd = (__le32 *)skb->data;
developer356ecec2022-11-14 10:25:04 +0800944@@ -1181,7 +1276,7 @@ void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
developer8cb3ac72022-07-04 10:55:14 +0800945 dev_kfree_skb(skb);
946 break;
947 case PKT_TYPE_NORMAL:
948- if (!mt7915_mac_fill_rx(dev, skb)) {
949+ if (!mt7915_mac_fill_rx(dev, skb, q, info)) {
950 mt76_rx(&dev->mt76, q, skb);
951 return;
952 }
953diff --git a/mt7915/mcu.c b/mt7915/mcu.c
developer29647af2022-11-15 18:09:16 +0800954index eb9343c..c11e575 100644
developer8cb3ac72022-07-04 10:55:14 +0800955--- a/mt7915/mcu.c
956+++ b/mt7915/mcu.c
developer356ecec2022-11-14 10:25:04 +0800957@@ -1653,6 +1653,7 @@ int mt7915_mcu_add_sta(struct mt7915_dev *dev, struct ieee80211_vif *vif,
developer8cb3ac72022-07-04 10:55:14 +0800958 struct ieee80211_sta *sta, bool enable)
959 {
960 struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv;
961+ struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
962 struct mt7915_sta *msta;
963 struct sk_buff *skb;
964 int ret;
developer356ecec2022-11-14 10:25:04 +0800965@@ -1705,6 +1706,8 @@ int mt7915_mcu_add_sta(struct mt7915_dev *dev, struct ieee80211_vif *vif,
developer8cb3ac72022-07-04 10:55:14 +0800966 return ret;
967 }
968 out:
developerf50c1802022-07-05 20:35:53 +0800969+ if (mtk_wed_device_active(wed) && wed->ver > MTK_WED_V1)
970+ mtk_wed_device_update_msg(wed, WED_WO_STA_REC, skb->data, skb->len);
developer8cb3ac72022-07-04 10:55:14 +0800971 return mt76_mcu_skb_send_msg(&dev->mt76, skb,
972 MCU_EXT_CMD(STA_REC_UPDATE), true);
973 }
974diff --git a/mt7915/mmio.c b/mt7915/mmio.c
developer29647af2022-11-15 18:09:16 +0800975index e45cd2d..1e22ec9 100644
developer8cb3ac72022-07-04 10:55:14 +0800976--- a/mt7915/mmio.c
977+++ b/mt7915/mmio.c
developer356ecec2022-11-14 10:25:04 +0800978@@ -44,6 +44,7 @@ static const u32 mt7915_reg[] = {
developer8cb3ac72022-07-04 10:55:14 +0800979 [SWDEF_BASE_ADDR] = 0x41f200,
developerc226de82022-10-03 12:24:57 +0800980 [TXQ_WED_RING_BASE] = 0xd7300,
981 [RXQ_WED_RING_BASE] = 0xd7410,
developer8cb3ac72022-07-04 10:55:14 +0800982+ [WED_RX_DATA_RING] = 0xd4500,
983 };
984
developer356ecec2022-11-14 10:25:04 +0800985 static const u32 mt7916_reg[] = {
986@@ -77,6 +78,7 @@ static const u32 mt7916_reg[] = {
developer8cb3ac72022-07-04 10:55:14 +0800987 [SWDEF_BASE_ADDR] = 0x411400,
developerc226de82022-10-03 12:24:57 +0800988 [TXQ_WED_RING_BASE] = 0xd7300,
989 [RXQ_WED_RING_BASE] = 0xd7410,
developer8cb3ac72022-07-04 10:55:14 +0800990+ [WED_RX_DATA_RING] = 0xd4540,
991 };
992
developer356ecec2022-11-14 10:25:04 +0800993 static const u32 mt7986_reg[] = {
994@@ -110,6 +112,7 @@ static const u32 mt7986_reg[] = {
developer8cb3ac72022-07-04 10:55:14 +0800995 [SWDEF_BASE_ADDR] = 0x411400,
developerc226de82022-10-03 12:24:57 +0800996 [TXQ_WED_RING_BASE] = 0x24420,
997 [RXQ_WED_RING_BASE] = 0x24520,
developer8cb3ac72022-07-04 10:55:14 +0800998+ [WED_RX_DATA_RING] = 0x24540,
999 };
1000
developer356ecec2022-11-14 10:25:04 +08001001 static const u32 mt7915_offs[] = {
1002@@ -605,7 +608,7 @@ int mt7915_mmio_wed_init(struct mt7915_dev *dev, void *pdev_ptr,
developerc226de82022-10-03 12:24:57 +08001003 struct pci_dev *pci_dev = pdev_ptr;
1004
1005 wed->wlan.pci_dev = pci_dev;
1006- wed->wlan.bus_type = MTK_WED_BUS_PCIE;
1007+ wed->wlan.bus_type = MTK_BUS_TYPE_PCIE;
1008 wed->wlan.base = (void __iomem *)ioremap(
1009 pci_resource_start(pci_dev, 0),
1010 pci_resource_len(pci_dev, 0));
developer356ecec2022-11-14 10:25:04 +08001011@@ -619,6 +622,10 @@ int mt7915_mmio_wed_init(struct mt7915_dev *dev, void *pdev_ptr,
developerc226de82022-10-03 12:24:57 +08001012 MT_TXQ_WED_RING_BASE;
1013 wed->wlan.wpdma_txfree = pci_resource_start(pci_dev, 0) +
1014 MT_RXQ_WED_RING_BASE;
1015+ wed->wlan.wpdma_rx_glo = pci_resource_start(pci_dev, 0) +
1016+ MT_WPDMA_GLO_CFG;
1017+ wed->wlan.wpdma_rx = pci_resource_start(pci_dev, 0) +
1018+ MT_RXQ_WED_DATA_RING_BASE;
1019 wed->wlan.phy_base = pci_resource_start(pci_dev, 0);
developerf50c1802022-07-05 20:35:53 +08001020 } else {
developerc226de82022-10-03 12:24:57 +08001021 struct platform_device *plat_dev = pdev_ptr;
developer356ecec2022-11-14 10:25:04 +08001022@@ -628,27 +635,38 @@ int mt7915_mmio_wed_init(struct mt7915_dev *dev, void *pdev_ptr,
developerc226de82022-10-03 12:24:57 +08001023 if (!res)
1024 return -ENOMEM;
1025
1026- wed->wlan.platform_dev = plat_dev;
1027- wed->wlan.bus_type = MTK_WED_BUS_AXI;
1028+ //wed->wlan.platform_dev = plat_dev;
1029+ wed->wlan.bus_type = MTK_BUS_TYPE_AXI;
1030 wed->wlan.base = (void __iomem *)ioremap(res->start,
1031 resource_size(res));
1032 wed->wlan.wpdma_int = res->start + MT_INT_SOURCE_CSR;
1033 wed->wlan.wpdma_mask = res->start + MT_INT_MASK_CSR;
1034 wed->wlan.wpdma_tx = res->start + MT_TXQ_WED_RING_BASE;
1035 wed->wlan.wpdma_txfree = res->start + MT_RXQ_WED_RING_BASE;
1036+ wed->wlan.wpdma_rx_glo = res->start + MT_WPDMA_GLO_CFG;
1037+ wed->wlan.wpdma_rx = res->start + MT_RXQ_WED_DATA_RING_BASE;
1038 wed->wlan.phy_base = res->start;
developer8cb3ac72022-07-04 10:55:14 +08001039 }
developerc226de82022-10-03 12:24:57 +08001040- wed->wlan.nbuf = 4096;
developer8cb3ac72022-07-04 10:55:14 +08001041+ wed->wlan.rx_pkt = MT7915_WED_RX_TOKEN_SIZE;
developerc226de82022-10-03 12:24:57 +08001042+ wed->wlan.nbuf = 7168;
1043 wed->wlan.tx_tbit[0] = is_mt7915(&dev->mt76) ? 4 : 30;
1044 wed->wlan.tx_tbit[1] = is_mt7915(&dev->mt76) ? 5 : 31;
1045- wed->wlan.txfree_tbit = is_mt7915(&dev->mt76) ? 1 : 2;
1046+ wed->wlan.txfree_tbit = (is_mt7986(&dev->mt76) ? 2 : 1);
1047+ wed->wlan.rx_tbit[0] = (is_mt7915(&dev->mt76) ? 16 : (is_mt7986(&dev->mt76) ? 22 : 18));
1048+ wed->wlan.rx_tbit[1] = (is_mt7915(&dev->mt76) ? 17 : (is_mt7986(&dev->mt76) ? 23 : 19));
developer8cb3ac72022-07-04 10:55:14 +08001049 wed->wlan.token_start = MT7915_TOKEN_SIZE - wed->wlan.nbuf;
1050 wed->wlan.init_buf = mt7915_wed_init_buf;
developerc226de82022-10-03 12:24:57 +08001051 wed->wlan.offload_enable = mt7915_mmio_wed_offload_enable;
1052 wed->wlan.offload_disable = mt7915_mmio_wed_offload_disable;
1053- if (!is_mt7915(mdev))
1054+ if (!is_mt7915(&dev->mt76))
developer203096a2022-09-13 21:07:19 +08001055 wed->wlan.wcid_512 = true;
developer8cb3ac72022-07-04 10:55:14 +08001056
1057+ wed->wlan.rx_nbuf = 65536;
1058+ wed->wlan.rx_pkt_size = MTK_WED_RX_PKT_SIZE;
1059+ wed->wlan.init_rx_buf = mt7915_wed_init_rx_buf;
1060+ wed->wlan.release_rx_buf = mt7915_wed_release_rx_buf;
1061+
developerc1b2cd12022-07-28 18:35:24 +08001062+ dev->mt76.rx_token_size = wed->wlan.rx_pkt;
developerc226de82022-10-03 12:24:57 +08001063 if (mtk_wed_device_attach(wed))
developer8cb3ac72022-07-04 10:55:14 +08001064 return 0;
1065
1066diff --git a/mt7915/mt7915.h b/mt7915/mt7915.h
developer29647af2022-11-15 18:09:16 +08001067index 06b98b7..6952825 100644
developer8cb3ac72022-07-04 10:55:14 +08001068--- a/mt7915/mt7915.h
1069+++ b/mt7915/mt7915.h
developere0cbe332022-09-10 17:36:02 +08001070@@ -81,6 +81,7 @@
developer8cb3ac72022-07-04 10:55:14 +08001071 #define MT7915_MAX_STA_TWT_AGRT 8
1072 #define MT7915_MIN_TWT_DUR 64
developer1d9fede2022-08-29 15:24:07 +08001073 #define MT7915_MAX_QUEUE (MT_RXQ_BAND2 + __MT_MCUQ_MAX + 2)
developer8cb3ac72022-07-04 10:55:14 +08001074+#define MT7915_WED_RX_TOKEN_SIZE 12288
1075
1076 struct mt7915_vif;
1077 struct mt7915_sta;
developer29647af2022-11-15 18:09:16 +08001078@@ -560,7 +561,9 @@ void mt7915_wfsys_reset(struct mt7915_dev *dev);
developer8cb3ac72022-07-04 10:55:14 +08001079 irqreturn_t mt7915_irq_handler(int irq, void *dev_instance);
1080 u64 __mt7915_get_tsf(struct ieee80211_hw *hw, struct mt7915_vif *mvif);
1081 u32 mt7915_wed_init_buf(void *ptr, dma_addr_t phys, int token_id);
1082-
1083+u32 mt7915_wed_init_rx_buf(struct mtk_wed_device *wed,
1084+ int pkt_num);
1085+void mt7915_wed_release_rx_buf(struct mtk_wed_device *wed);
1086 int mt7915_register_device(struct mt7915_dev *dev);
1087 void mt7915_unregister_device(struct mt7915_dev *dev);
developer81ca9d62022-10-14 11:23:22 +08001088 void mt7915_eeprom_rebonding(struct mt7915_dev *dev);
developer29647af2022-11-15 18:09:16 +08001089@@ -720,7 +723,7 @@ int mt7915_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
developer8cb3ac72022-07-04 10:55:14 +08001090 struct mt76_tx_info *tx_info);
1091 void mt7915_tx_token_put(struct mt7915_dev *dev);
1092 void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1093- struct sk_buff *skb);
1094+ struct sk_buff *skb, u32 info);
1095 bool mt7915_rx_check(struct mt76_dev *mdev, void *data, int len);
developere0cbe332022-09-10 17:36:02 +08001096 bool mt7915_wed_wds_check(struct mt76_dev *mdev, struct ieee80211_sta *sta);
developer8cb3ac72022-07-04 10:55:14 +08001097 void mt7915_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps);
developer8cb3ac72022-07-04 10:55:14 +08001098diff --git a/mt7915/regs.h b/mt7915/regs.h
developer29647af2022-11-15 18:09:16 +08001099index 9b6266c..faaac08 100644
developer8cb3ac72022-07-04 10:55:14 +08001100--- a/mt7915/regs.h
1101+++ b/mt7915/regs.h
developer356ecec2022-11-14 10:25:04 +08001102@@ -43,6 +43,7 @@ enum reg_rev {
developer8cb3ac72022-07-04 10:55:14 +08001103 SWDEF_BASE_ADDR,
developerc226de82022-10-03 12:24:57 +08001104 TXQ_WED_RING_BASE,
1105 RXQ_WED_RING_BASE,
developer8cb3ac72022-07-04 10:55:14 +08001106+ WED_RX_DATA_RING,
1107 __MT_REG_MAX,
1108 };
developer356ecec2022-11-14 10:25:04 +08001109
1110@@ -603,9 +604,13 @@ enum offs_rev {
developer8cb3ac72022-07-04 10:55:14 +08001111 #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2 BIT(21)
1112
1113 #define MT_WFDMA0_RST_DTX_PTR MT_WFDMA0(0x20c)
1114+#define MT_WFDMA0_EXT0_CFG MT_WFDMA0(0x2b0)
1115+#define MT_WFDMA0_EXT0_RXWB_KEEP BIT(10)
1116+
1117 #define MT_WFDMA0_PRI_DLY_INT_CFG0 MT_WFDMA0(0x2f0)
1118 #define MT_WFDMA0_PRI_DLY_INT_CFG1 MT_WFDMA0(0x2f4)
1119 #define MT_WFDMA0_PRI_DLY_INT_CFG2 MT_WFDMA0(0x2f8)
1120+#define MT_WPDMA_GLO_CFG MT_WFDMA0(0x208)
1121
developer356ecec2022-11-14 10:25:04 +08001122 /* WFDMA1 */
1123 #define MT_WFDMA1_BASE 0xd5000
1124@@ -701,6 +706,7 @@ enum offs_rev {
developer8cb3ac72022-07-04 10:55:14 +08001125
developerc226de82022-10-03 12:24:57 +08001126 #define MT_TXQ_WED_RING_BASE __REG(TXQ_WED_RING_BASE)
1127 #define MT_RXQ_WED_RING_BASE __REG(RXQ_WED_RING_BASE)
developer8cb3ac72022-07-04 10:55:14 +08001128+#define MT_RXQ_WED_DATA_RING_BASE __REG(WED_RX_DATA_RING)
1129
developer8cb3ac72022-07-04 10:55:14 +08001130 #define MT_INT_SOURCE_CSR __REG(INT_SOURCE_CSR)
1131 #define MT_INT_MASK_CSR __REG(INT_MASK_CSR)
1132diff --git a/mt7921/mac.c b/mt7921/mac.c
developer29647af2022-11-15 18:09:16 +08001133index 7b15193..ea6dd95 100644
developer8cb3ac72022-07-04 10:55:14 +08001134--- a/mt7921/mac.c
1135+++ b/mt7921/mac.c
developer81ca9d62022-10-14 11:23:22 +08001136@@ -692,7 +692,7 @@ bool mt7921_rx_check(struct mt76_dev *mdev, void *data, int len)
developer20747c12022-09-16 14:09:40 +08001137 EXPORT_SYMBOL_GPL(mt7921_rx_check);
developer8cb3ac72022-07-04 10:55:14 +08001138
1139 void mt7921_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1140- struct sk_buff *skb)
1141+ struct sk_buff *skb, u32 info)
1142 {
1143 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
1144 __le32 *rxd = (__le32 *)skb->data;
1145diff --git a/mt7921/mt7921.h b/mt7921/mt7921.h
developer29647af2022-11-15 18:09:16 +08001146index d9d78f6..0c9924a 100644
developer8cb3ac72022-07-04 10:55:14 +08001147--- a/mt7921/mt7921.h
1148+++ b/mt7921/mt7921.h
developer356ecec2022-11-14 10:25:04 +08001149@@ -422,7 +422,7 @@ void mt7921_tx_worker(struct mt76_worker *w);
developer8cb3ac72022-07-04 10:55:14 +08001150 void mt7921_tx_token_put(struct mt7921_dev *dev);
developer20747c12022-09-16 14:09:40 +08001151 bool mt7921_rx_check(struct mt76_dev *mdev, void *data, int len);
developer8cb3ac72022-07-04 10:55:14 +08001152 void mt7921_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1153- struct sk_buff *skb);
1154+ struct sk_buff *skb, u32 info);
1155 void mt7921_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps);
1156 void mt7921_stats_work(struct work_struct *work);
1157 void mt7921_set_stream_he_caps(struct mt7921_phy *phy);
developer8cb3ac72022-07-04 10:55:14 +08001158diff --git a/tx.c b/tx.c
developer29647af2022-11-15 18:09:16 +08001159index 8b33186..b812d06 100644
developer8cb3ac72022-07-04 10:55:14 +08001160--- a/tx.c
1161+++ b/tx.c
developer1d9fede2022-08-29 15:24:07 +08001162@@ -778,3 +778,37 @@ mt76_token_release(struct mt76_dev *dev, int token, bool *wake)
developer8cb3ac72022-07-04 10:55:14 +08001163 return txwi;
1164 }
1165 EXPORT_SYMBOL_GPL(mt76_token_release);
1166+
1167+int mt76_rx_token_consume(struct mt76_dev *dev, void *ptr,
1168+ struct mt76_txwi_cache *r, dma_addr_t phys)
1169+{
1170+ int token;
1171+
1172+ spin_lock_bh(&dev->rx_token_lock);
1173+
1174+ token = idr_alloc(&dev->rx_token, r, 0, dev->rx_token_size, GFP_ATOMIC);
1175+
1176+ spin_unlock_bh(&dev->rx_token_lock);
1177+
1178+ r->buf = ptr;
1179+ r->dma_addr = phys;
1180+
1181+ return token;
1182+}
1183+EXPORT_SYMBOL_GPL(mt76_rx_token_consume);
1184+
1185+struct mt76_txwi_cache *
1186+mt76_rx_token_release(struct mt76_dev *dev, int token)
1187+{
1188+
1189+ struct mt76_txwi_cache *rxwi;
1190+
1191+ spin_lock_bh(&dev->rx_token_lock);
1192+
1193+ rxwi = idr_remove(&dev->rx_token, token);
1194+
1195+ spin_unlock_bh(&dev->rx_token_lock);
1196+
1197+ return rxwi;
1198+}
1199+EXPORT_SYMBOL_GPL(mt76_rx_token_release);
1200--
developer887da632022-10-28 09:35:38 +080012012.18.0
developer8cb3ac72022-07-04 10:55:14 +08001202