blob: 49992bcb1f33b126d01c7de84ebb3a289de94d99 [file] [log] [blame]
developerbbca0f92022-07-26 17:26:12 +08001From 50c04081556744438d6017c11ddfa3b7239efd26 Mon Sep 17 00:00:00 2001
developer8cb3ac72022-07-04 10:55:14 +08002From: Sujuan Chen <sujuan.chen@mediatek.com>
developerf50c1802022-07-05 20:35:53 +08003Date: Tue, 5 Jul 2022 19:42:55 +0800
developerd59e4772022-07-14 13:48:49 +08004Subject: [PATCH 3002/3003] mt76 add wed rx support
developer8cb3ac72022-07-04 10:55:14 +08005
6Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
7---
developerbbca0f92022-07-26 17:26:12 +08008 dma.c | 250 ++++++++++++++++++++++++++++++++++++++--------
9 dma.h | 10 ++
10 mac80211.c | 8 +-
11 mt76.h | 25 ++++-
12 mt7603/dma.c | 2 +-
13 mt7603/mt7603.h | 2 +-
14 mt7615/mac.c | 2 +-
15 mt7615/mt7615.h | 2 +-
16 mt76_connac_mcu.c | 9 ++
17 mt76x02.h | 2 +-
18 mt76x02_txrx.c | 2 +-
developerc1b2cd12022-07-28 18:35:24 +080019 mt7915/dma.c | 25 +++--
developerbbca0f92022-07-26 17:26:12 +080020 mt7915/init.c | 9 ++
21 mt7915/mac.c | 103 ++++++++++++++++++-
22 mt7915/main.c | 25 ++++-
23 mt7915/mcu.c | 14 ++-
24 mt7915/mcu.h | 1 +
25 mt7915/mmio.c | 26 ++++-
26 mt7915/mt7915.h | 10 +-
27 mt7915/regs.h | 14 ++-
28 mt7921/mac.c | 2 +-
29 mt7921/mt7921.h | 4 +-
30 mt7921/pci_mac.c | 4 +-
31 tx.c | 34 +++++++
developerc1b2cd12022-07-28 18:35:24 +080032 24 files changed, 504 insertions(+), 81 deletions(-)
developer8cb3ac72022-07-04 10:55:14 +080033
34diff --git a/dma.c b/dma.c
developerc1b2cd12022-07-28 18:35:24 +080035index 03ee9109..4d4d4046 100644
developer8cb3ac72022-07-04 10:55:14 +080036--- a/dma.c
37+++ b/dma.c
38@@ -98,6 +98,63 @@ mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t)
39 }
40 EXPORT_SYMBOL_GPL(mt76_put_txwi);
41
42+static struct mt76_txwi_cache *
43+mt76_alloc_rxwi(struct mt76_dev *dev)
44+{
45+ struct mt76_txwi_cache *r;
46+ int size;
47+
48+ size = L1_CACHE_ALIGN(sizeof(*r));
49+ r = kzalloc(size, GFP_ATOMIC);
50+ if (!r)
51+ return NULL;
52+
53+ r->buf = NULL;
54+
55+ return r;
56+}
57+
58+static struct mt76_txwi_cache *
59+__mt76_get_rxwi(struct mt76_dev *dev)
60+{
61+ struct mt76_txwi_cache *r = NULL;
62+
63+ spin_lock(&dev->wed_lock);
64+ if (!list_empty(&dev->rxwi_cache)) {
65+ r = list_first_entry(&dev->rxwi_cache, struct mt76_txwi_cache,
66+ list);
67+ if(r)
68+ list_del(&r->list);
69+ }
70+ spin_unlock(&dev->wed_lock);
71+
72+ return r;
73+}
74+
75+struct mt76_txwi_cache *
76+mt76_get_rxwi(struct mt76_dev *dev)
77+{
78+ struct mt76_txwi_cache *r = __mt76_get_rxwi(dev);
79+
80+ if (r)
81+ return r;
82+
83+ return mt76_alloc_rxwi(dev);
84+}
85+EXPORT_SYMBOL_GPL(mt76_get_rxwi);
86+
87+void
88+mt76_put_rxwi(struct mt76_dev *dev, struct mt76_txwi_cache *r)
89+{
90+ if (!r)
91+ return;
92+
93+ spin_lock(&dev->wed_lock);
94+ list_add(&r->list, &dev->rxwi_cache);
95+ spin_unlock(&dev->wed_lock);
96+}
97+EXPORT_SYMBOL_GPL(mt76_put_rxwi);
98+
99 static void
100 mt76_free_pending_txwi(struct mt76_dev *dev)
101 {
developera3f86ed2022-07-08 14:15:13 +0800102@@ -112,6 +169,21 @@ mt76_free_pending_txwi(struct mt76_dev *dev)
103 local_bh_enable();
104 }
105
106+static void
107+mt76_free_pending_rxwi(struct mt76_dev *dev)
108+{
109+ struct mt76_txwi_cache *r;
110+
111+ local_bh_disable();
112+ while ((r = __mt76_get_rxwi(dev)) != NULL) {
113+ if (r->buf)
114+ skb_free_frag(r->buf);
115+
116+ kfree(r);
117+ }
118+ local_bh_enable();
119+}
120+
121 static void
122 mt76_dma_sync_idx(struct mt76_dev *dev, struct mt76_queue *q)
123 {
124@@ -141,12 +213,15 @@ mt76_dma_queue_reset(struct mt76_dev *dev, struct mt76_queue *q)
developer8cb3ac72022-07-04 10:55:14 +0800125 static int
126 mt76_dma_add_buf(struct mt76_dev *dev, struct mt76_queue *q,
127 struct mt76_queue_buf *buf, int nbufs, u32 info,
128- struct sk_buff *skb, void *txwi)
129+ struct sk_buff *skb, void *txwi, void *rxwi)
130 {
131+ struct mtk_wed_device *wed = &dev->mmio.wed;
132+
133 struct mt76_queue_entry *entry;
134 struct mt76_desc *desc;
135 u32 ctrl;
136 int i, idx = -1;
137+ int type;
138
139 if (txwi) {
140 q->entry[q->head].txwi = DMA_DUMMY_DATA;
developera3f86ed2022-07-08 14:15:13 +0800141@@ -162,28 +237,42 @@ mt76_dma_add_buf(struct mt76_dev *dev, struct mt76_queue *q,
developer8cb3ac72022-07-04 10:55:14 +0800142 desc = &q->desc[idx];
143 entry = &q->entry[idx];
144
145- if (buf[0].skip_unmap)
146- entry->skip_buf0 = true;
147- entry->skip_buf1 = i == nbufs - 1;
148-
149- entry->dma_addr[0] = buf[0].addr;
150- entry->dma_len[0] = buf[0].len;
151-
152- ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, buf[0].len);
153- if (i < nbufs - 1) {
154- entry->dma_addr[1] = buf[1].addr;
155- entry->dma_len[1] = buf[1].len;
156- buf1 = buf[1].addr;
157- ctrl |= FIELD_PREP(MT_DMA_CTL_SD_LEN1, buf[1].len);
158- if (buf[1].skip_unmap)
159- entry->skip_buf1 = true;
160+ type = FIELD_GET(MT_QFLAG_WED_TYPE, q->flags);
161+ if (mtk_wed_device_active(wed) && type == MT76_WED_Q_RX) {
162+ struct mt76_txwi_cache *r = rxwi;
163+ int rx_token;
164+
165+ if (!r)
166+ return -ENOMEM;
167+
168+ rx_token = mt76_rx_token_consume(dev, (void *)skb, r, buf[0].addr);
169+
170+ buf1 |= FIELD_PREP(MT_DMA_CTL_TOKEN, rx_token);
171+ ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, MTK_WED_RX_PKT_SIZE);
172+ ctrl |= MT_DMA_CTL_TO_HOST;
173+ } else {
174+ if (buf[0].skip_unmap)
175+ entry->skip_buf0 = true;
176+ entry->skip_buf1 = i == nbufs - 1;
177+
178+ entry->dma_addr[0] = buf[0].addr;
179+ entry->dma_len[0] = buf[0].len;
180+
181+ ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, buf[0].len);
182+ if (i < nbufs - 1) {
183+ entry->dma_addr[1] = buf[1].addr;
184+ entry->dma_len[1] = buf[1].len;
185+ buf1 = buf[1].addr;
186+ ctrl |= FIELD_PREP(MT_DMA_CTL_SD_LEN1, buf[1].len);
187+ if (buf[1].skip_unmap)
188+ entry->skip_buf1 = true;
189+ }
190+ if (i == nbufs - 1)
191+ ctrl |= MT_DMA_CTL_LAST_SEC0;
192+ else if (i == nbufs - 2)
193+ ctrl |= MT_DMA_CTL_LAST_SEC1;
194 }
195
196- if (i == nbufs - 1)
197- ctrl |= MT_DMA_CTL_LAST_SEC0;
198- else if (i == nbufs - 2)
199- ctrl |= MT_DMA_CTL_LAST_SEC1;
200-
201 WRITE_ONCE(desc->buf0, cpu_to_le32(buf0));
202 WRITE_ONCE(desc->buf1, cpu_to_le32(buf1));
203 WRITE_ONCE(desc->info, cpu_to_le32(info));
developerc32bdb22022-07-20 16:15:39 +0800204@@ -272,33 +361,65 @@ mt76_dma_tx_cleanup(struct mt76_dev *dev, struct mt76_queue *q, bool flush)
developer8cb3ac72022-07-04 10:55:14 +0800205
206 static void *
207 mt76_dma_get_buf(struct mt76_dev *dev, struct mt76_queue *q, int idx,
208- int *len, u32 *info, bool *more)
209+ int *len, u32 *info, bool *more, bool *drop)
210 {
211 struct mt76_queue_entry *e = &q->entry[idx];
212 struct mt76_desc *desc = &q->desc[idx];
213 dma_addr_t buf_addr;
developerc32bdb22022-07-20 16:15:39 +0800214- void *buf = e->buf;
215+ void *buf = e->buf, *copy = NULL;
developer8cb3ac72022-07-04 10:55:14 +0800216 int buf_len = SKB_WITH_OVERHEAD(q->buf_size);
217+ struct mtk_wed_device *wed = &dev->mmio.wed;
218+ int type;
219
220- buf_addr = e->dma_addr[0];
221 if (len) {
222 u32 ctl = le32_to_cpu(READ_ONCE(desc->ctrl));
223 *len = FIELD_GET(MT_DMA_CTL_SD_LEN0, ctl);
224 *more = !(ctl & MT_DMA_CTL_LAST_SEC0);
225 }
226
227- if (info)
228- *info = le32_to_cpu(desc->info);
229+ type = FIELD_GET(MT_QFLAG_WED_TYPE, q->flags);
230+ if (mtk_wed_device_active(wed) && type == MT76_WED_Q_RX) {
231+ u32 token;
232+ struct mt76_txwi_cache *r;
233+
234+ token = FIELD_GET(MT_DMA_CTL_TOKEN, desc->buf1);
235+
236+ r = mt76_rx_token_release(dev, token);
237+ if (!r)
238+ return NULL;
239+
240+ buf = page_frag_alloc(&q->rx_page, q->buf_size, GFP_ATOMIC);
241+ if (!buf)
242+ return NULL;
243+
developerc32bdb22022-07-20 16:15:39 +0800244+ copy = r->buf;
developer8cb3ac72022-07-04 10:55:14 +0800245+ buf_addr = r->dma_addr;
246+ buf_len = MTK_WED_RX_PKT_SIZE;
247+ r->dma_addr = 0;
developer8cb3ac72022-07-04 10:55:14 +0800248+
249+ mt76_put_rxwi(dev, r);
250+
251+ if (desc->ctrl & (MT_DMA_CTL_TO_HOST_A | MT_DMA_CTL_DROP))
252+ *drop = true;
253+ } else {
254+ buf_addr = e->dma_addr[0];
255+ e->buf = NULL;
256+ }
257
258 dma_unmap_single(dev->dma_dev, buf_addr, buf_len, DMA_FROM_DEVICE);
259- e->buf = NULL;
260+
developerc32bdb22022-07-20 16:15:39 +0800261+ if (copy)
262+ memcpy(buf, copy, MTK_WED_RX_PKT_SIZE);
263+
developer8cb3ac72022-07-04 10:55:14 +0800264+ if (info)
265+ *info = le32_to_cpu(desc->info);
266
267 return buf;
268 }
269
270 static void *
271 mt76_dma_dequeue(struct mt76_dev *dev, struct mt76_queue *q, bool flush,
272- int *len, u32 *info, bool *more)
273+ int *len, u32 *info, bool *more, bool *drop)
274 {
275 int idx = q->tail;
276
developerbbca0f92022-07-26 17:26:12 +0800277@@ -314,7 +435,7 @@ mt76_dma_dequeue(struct mt76_dev *dev, struct mt76_queue *q, bool flush,
developer8cb3ac72022-07-04 10:55:14 +0800278 q->tail = (q->tail + 1) % q->ndesc;
279 q->queued--;
280
281- return mt76_dma_get_buf(dev, q, idx, len, info, more);
282+ return mt76_dma_get_buf(dev, q, idx, len, info, more, drop);
283 }
284
285 static int
developerbbca0f92022-07-26 17:26:12 +0800286@@ -336,7 +457,7 @@ mt76_dma_tx_queue_skb_raw(struct mt76_dev *dev, struct mt76_queue *q,
developer8cb3ac72022-07-04 10:55:14 +0800287 buf.len = skb->len;
288
289 spin_lock_bh(&q->lock);
290- mt76_dma_add_buf(dev, q, &buf, 1, tx_info, skb, NULL);
291+ mt76_dma_add_buf(dev, q, &buf, 1, tx_info, skb, NULL, NULL);
292 mt76_dma_kick_queue(dev, q);
293 spin_unlock_bh(&q->lock);
294
developerbbca0f92022-07-26 17:26:12 +0800295@@ -413,7 +534,7 @@ mt76_dma_tx_queue_skb(struct mt76_dev *dev, struct mt76_queue *q,
developer8cb3ac72022-07-04 10:55:14 +0800296 goto unmap;
297
298 return mt76_dma_add_buf(dev, q, tx_info.buf, tx_info.nbuf,
299- tx_info.info, tx_info.skb, t);
300+ tx_info.info, tx_info.skb, t, NULL);
301
302 unmap:
303 for (n--; n > 0; n--)
developerbbca0f92022-07-26 17:26:12 +0800304@@ -448,6 +569,8 @@ mt76_dma_rx_fill(struct mt76_dev *dev, struct mt76_queue *q)
developer8cb3ac72022-07-04 10:55:14 +0800305 int frames = 0;
306 int len = SKB_WITH_OVERHEAD(q->buf_size);
307 int offset = q->buf_offset;
308+ struct mtk_wed_device *wed = &dev->mmio.wed;
developera3f86ed2022-07-08 14:15:13 +0800309+ struct page_frag_cache *rx_page;
developer8cb3ac72022-07-04 10:55:14 +0800310
311 if (!q->ndesc)
312 return 0;
developerbbca0f92022-07-26 17:26:12 +0800313@@ -456,10 +579,29 @@ mt76_dma_rx_fill(struct mt76_dev *dev, struct mt76_queue *q)
developer8cb3ac72022-07-04 10:55:14 +0800314
315 while (q->queued < q->ndesc - 1) {
316 struct mt76_queue_buf qbuf;
317+ int type = FIELD_GET(MT_QFLAG_WED_TYPE, q->flags);
318+ bool skip_alloc = false;
319+ struct mt76_txwi_cache *r = NULL;
320+
developera3f86ed2022-07-08 14:15:13 +0800321+ rx_page = &q->rx_page;
developer8cb3ac72022-07-04 10:55:14 +0800322+ if (mtk_wed_device_active(wed) && type == MT76_WED_Q_RX) {
developera3f86ed2022-07-08 14:15:13 +0800323+ rx_page = &wed->rx_page;
developer8cb3ac72022-07-04 10:55:14 +0800324+ r = mt76_get_rxwi(dev);
325+ if (!r)
326+ return -ENOMEM;
327+
328+ if (r->buf) {
329+ skip_alloc = true;
330+ len = MTK_WED_RX_PKT_SIZE;
331+ buf = r->buf;
332+ }
333+ }
334
335- buf = page_frag_alloc(&q->rx_page, q->buf_size, GFP_ATOMIC);
336- if (!buf)
337- break;
338+ if (!skip_alloc) {
developera3f86ed2022-07-08 14:15:13 +0800339+ buf = page_frag_alloc(rx_page, q->buf_size, GFP_ATOMIC);
developer8cb3ac72022-07-04 10:55:14 +0800340+ if (!buf)
341+ break;
342+ }
343
344 addr = dma_map_single(dev->dma_dev, buf, len, DMA_FROM_DEVICE);
345 if (unlikely(dma_mapping_error(dev->dma_dev, addr))) {
developerbbca0f92022-07-26 17:26:12 +0800346@@ -470,7 +612,7 @@ mt76_dma_rx_fill(struct mt76_dev *dev, struct mt76_queue *q)
developer8cb3ac72022-07-04 10:55:14 +0800347 qbuf.addr = addr + offset;
348 qbuf.len = len - offset;
349 qbuf.skip_unmap = false;
350- mt76_dma_add_buf(dev, q, &qbuf, 1, 0, buf, NULL);
351+ mt76_dma_add_buf(dev, q, &qbuf, 1, 0, buf, NULL, r);
352 frames++;
353 }
354
developerbbca0f92022-07-26 17:26:12 +0800355@@ -516,6 +658,11 @@ mt76_dma_wed_setup(struct mt76_dev *dev, struct mt76_queue *q)
developer8cb3ac72022-07-04 10:55:14 +0800356 if (!ret)
357 q->wed_regs = wed->txfree_ring.reg_base;
358 break;
359+ case MT76_WED_Q_RX:
360+ ret = mtk_wed_device_rx_ring_setup(wed, ring, q->regs);
361+ if (!ret)
362+ q->wed_regs = wed->rx_ring[ring].reg_base;
363+ break;
364 default:
365 ret = -EINVAL;
366 }
developerbbca0f92022-07-26 17:26:12 +0800367@@ -531,7 +678,8 @@ mt76_dma_alloc_queue(struct mt76_dev *dev, struct mt76_queue *q,
developer8cb3ac72022-07-04 10:55:14 +0800368 int idx, int n_desc, int bufsize,
369 u32 ring_base)
370 {
371- int ret, size;
372+ int ret, size, type;
373+ struct mtk_wed_device *wed = &dev->mmio.wed;
374
375 spin_lock_init(&q->lock);
376 spin_lock_init(&q->cleanup_lock);
developerbbca0f92022-07-26 17:26:12 +0800377@@ -541,6 +689,11 @@ mt76_dma_alloc_queue(struct mt76_dev *dev, struct mt76_queue *q,
developer8cb3ac72022-07-04 10:55:14 +0800378 q->buf_size = bufsize;
379 q->hw_idx = idx;
380
381+ type = FIELD_GET(MT_QFLAG_WED_TYPE, q->flags);
382+ if (mtk_wed_device_active(wed) && type == MT76_WED_Q_RX)
383+ q->buf_size = SKB_DATA_ALIGN(NET_SKB_PAD + MTK_WED_RX_PKT_SIZE) +
384+ SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
385+
386 size = q->ndesc * sizeof(struct mt76_desc);
387 q->desc = dmam_alloc_coherent(dev->dma_dev, size, &q->desc_dma, GFP_KERNEL);
388 if (!q->desc)
developerbbca0f92022-07-26 17:26:12 +0800389@@ -573,7 +726,7 @@ mt76_dma_rx_cleanup(struct mt76_dev *dev, struct mt76_queue *q)
developer8cb3ac72022-07-04 10:55:14 +0800390
391 spin_lock_bh(&q->lock);
392 do {
393- buf = mt76_dma_dequeue(dev, q, true, NULL, NULL, &more);
394+ buf = mt76_dma_dequeue(dev, q, true, NULL, NULL, &more, NULL);
395 if (!buf)
396 break;
397
developerbbca0f92022-07-26 17:26:12 +0800398@@ -614,7 +767,7 @@ mt76_dma_rx_reset(struct mt76_dev *dev, enum mt76_rxq_id qid)
developer8cb3ac72022-07-04 10:55:14 +0800399
400 static void
401 mt76_add_fragment(struct mt76_dev *dev, struct mt76_queue *q, void *data,
402- int len, bool more)
403+ int len, bool more, u32 info)
404 {
405 struct sk_buff *skb = q->rx_head;
406 struct skb_shared_info *shinfo = skb_shinfo(skb);
developerbbca0f92022-07-26 17:26:12 +0800407@@ -634,7 +787,7 @@ mt76_add_fragment(struct mt76_dev *dev, struct mt76_queue *q, void *data,
developer8cb3ac72022-07-04 10:55:14 +0800408
409 q->rx_head = NULL;
410 if (nr_frags < ARRAY_SIZE(shinfo->frags))
411- dev->drv->rx_skb(dev, q - dev->q_rx, skb);
412+ dev->drv->rx_skb(dev, q - dev->q_rx, skb, info);
413 else
414 dev_kfree_skb(skb);
415 }
developerbbca0f92022-07-26 17:26:12 +0800416@@ -655,6 +808,7 @@ mt76_dma_rx_process(struct mt76_dev *dev, struct mt76_queue *q, int budget)
developer8cb3ac72022-07-04 10:55:14 +0800417 }
418
419 while (done < budget) {
420+ bool drop = false;
421 u32 info;
422
423 if (check_ddone) {
developerbbca0f92022-07-26 17:26:12 +0800424@@ -665,10 +819,13 @@ mt76_dma_rx_process(struct mt76_dev *dev, struct mt76_queue *q, int budget)
developer8cb3ac72022-07-04 10:55:14 +0800425 break;
426 }
427
428- data = mt76_dma_dequeue(dev, q, false, &len, &info, &more);
429+ data = mt76_dma_dequeue(dev, q, false, &len, &info, &more, &drop);
430 if (!data)
431 break;
432
433+ if (drop)
434+ goto free_frag;
435+
436 if (q->rx_head)
437 data_len = q->buf_size;
438 else
developerbbca0f92022-07-26 17:26:12 +0800439@@ -681,7 +838,7 @@ mt76_dma_rx_process(struct mt76_dev *dev, struct mt76_queue *q, int budget)
developer8cb3ac72022-07-04 10:55:14 +0800440 }
441
442 if (q->rx_head) {
443- mt76_add_fragment(dev, q, data, len, more);
444+ mt76_add_fragment(dev, q, data, len, more, info);
445 continue;
446 }
447
developerbbca0f92022-07-26 17:26:12 +0800448@@ -708,7 +865,7 @@ mt76_dma_rx_process(struct mt76_dev *dev, struct mt76_queue *q, int budget)
developer8cb3ac72022-07-04 10:55:14 +0800449 continue;
450 }
451
452- dev->drv->rx_skb(dev, q - dev->q_rx, skb);
453+ dev->drv->rx_skb(dev, q - dev->q_rx, skb, info);
454 continue;
455
456 free_frag:
developerbbca0f92022-07-26 17:26:12 +0800457@@ -785,7 +942,7 @@ EXPORT_SYMBOL_GPL(mt76_dma_attach);
developera3f86ed2022-07-08 14:15:13 +0800458
459 void mt76_dma_cleanup(struct mt76_dev *dev)
460 {
461- int i;
developera3f86ed2022-07-08 14:15:13 +0800462+ int i, type;
developerd59e4772022-07-14 13:48:49 +0800463
developera3f86ed2022-07-08 14:15:13 +0800464 mt76_worker_disable(&dev->tx_worker);
465 netif_napi_del(&dev->tx_napi);
developerbbca0f92022-07-26 17:26:12 +0800466@@ -801,12 +958,17 @@ void mt76_dma_cleanup(struct mt76_dev *dev)
developera3f86ed2022-07-08 14:15:13 +0800467
468 mt76_for_each_q_rx(dev, i) {
469 netif_napi_del(&dev->napi[i]);
470- mt76_dma_rx_cleanup(dev, &dev->q_rx[i]);
471+ type = FIELD_GET(MT_QFLAG_WED_TYPE, dev->q_rx[i].flags);
472+ if (type != MT76_WED_Q_RX)
473+ mt76_dma_rx_cleanup(dev, &dev->q_rx[i]);
474 }
475
476 mt76_free_pending_txwi(dev);
477+ mt76_free_pending_rxwi(dev);
478
479 if (mtk_wed_device_active(&dev->mmio.wed))
480 mtk_wed_device_detach(&dev->mmio.wed);
481+
482+ mt76_free_pending_rxwi(dev);
483 }
484 EXPORT_SYMBOL_GPL(mt76_dma_cleanup);
developer8cb3ac72022-07-04 10:55:14 +0800485diff --git a/dma.h b/dma.h
developerc1b2cd12022-07-28 18:35:24 +0800486index fdf786f9..90370d12 100644
developer8cb3ac72022-07-04 10:55:14 +0800487--- a/dma.h
488+++ b/dma.h
489@@ -16,6 +16,16 @@
490 #define MT_DMA_CTL_LAST_SEC0 BIT(30)
491 #define MT_DMA_CTL_DMA_DONE BIT(31)
492
493+#define MT_DMA_CTL_TO_HOST BIT(8)
494+#define MT_DMA_CTL_TO_HOST_A BIT(12)
495+#define MT_DMA_CTL_DROP BIT(14)
496+
497+#define MT_DMA_CTL_TOKEN GENMASK(31, 16)
498+
499+#define MT_DMA_PPE_CPU_REASON GENMASK(15, 11)
500+#define MT_DMA_PPE_ENTRY GENMASK(30, 16)
501+#define MT_DMA_INFO_PPE_VLD BIT(31)
502+
503 #define MT_DMA_HDR_LEN 4
504 #define MT_RX_INFO_LEN 4
505 #define MT_FCE_INFO_LEN 4
506diff --git a/mac80211.c b/mac80211.c
developerc1b2cd12022-07-28 18:35:24 +0800507index af2c09ad..fa5ce6ec 100644
developer8cb3ac72022-07-04 10:55:14 +0800508--- a/mac80211.c
509+++ b/mac80211.c
510@@ -594,11 +594,14 @@ mt76_alloc_device(struct device *pdev, unsigned int size,
511 BIT(NL80211_IFTYPE_ADHOC);
512
513 spin_lock_init(&dev->token_lock);
514+ spin_lock_init(&dev->rx_token_lock);
515 idr_init(&dev->token);
516+ idr_init(&dev->rx_token);
517
518 INIT_LIST_HEAD(&dev->wcid_list);
519
520 INIT_LIST_HEAD(&dev->txwi_cache);
521+ INIT_LIST_HEAD(&dev->rxwi_cache);
522 dev->token_size = dev->drv->token_size;
523
524 for (i = 0; i < ARRAY_SIZE(dev->q_rx); i++)
525@@ -1296,7 +1299,10 @@ void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q,
526
527 while ((skb = __skb_dequeue(&dev->rx_skb[q])) != NULL) {
528 mt76_check_sta(dev, skb);
529- mt76_rx_aggr_reorder(skb, &frames);
530+ if (mtk_wed_device_active(&dev->mmio.wed))
531+ __skb_queue_tail(&frames, skb);
532+ else
533+ mt76_rx_aggr_reorder(skb, &frames);
534 }
535
536 mt76_rx_complete(dev, &frames, napi);
537diff --git a/mt76.h b/mt76.h
developerc1b2cd12022-07-28 18:35:24 +0800538index 49314895..0043c7c8 100644
developer8cb3ac72022-07-04 10:55:14 +0800539--- a/mt76.h
540+++ b/mt76.h
541@@ -20,6 +20,8 @@
542
543 #define MT_MCU_RING_SIZE 32
544 #define MT_RX_BUF_SIZE 2048
545+#define MTK_WED_RX_PKT_SIZE 1700
546+
547 #define MT_SKB_HEAD_LEN 256
548
549 #define MT_MAX_NON_AQL_PKT 16
550@@ -35,6 +37,7 @@
551 FIELD_PREP(MT_QFLAG_WED_TYPE, _type) | \
552 FIELD_PREP(MT_QFLAG_WED_RING, _n))
553 #define MT_WED_Q_TX(_n) __MT_WED_Q(MT76_WED_Q_TX, _n)
554+#define MT_WED_Q_RX(_n) __MT_WED_Q(MT76_WED_Q_RX, _n)
555 #define MT_WED_Q_TXFREE __MT_WED_Q(MT76_WED_Q_TXFREE, 0)
556
557 struct mt76_dev;
558@@ -56,6 +59,7 @@ enum mt76_bus_type {
559 enum mt76_wed_type {
560 MT76_WED_Q_TX,
561 MT76_WED_Q_TXFREE,
562+ MT76_WED_Q_RX,
563 };
564
565 struct mt76_bus_ops {
566@@ -305,7 +309,10 @@ struct mt76_txwi_cache {
567 struct list_head list;
568 dma_addr_t dma_addr;
569
570- struct sk_buff *skb;
571+ union {
572+ void *buf;
573+ struct sk_buff *skb;
574+ };
575 };
576
577 struct mt76_rx_tid {
578@@ -403,7 +410,7 @@ struct mt76_driver_ops {
579 bool (*rx_check)(struct mt76_dev *dev, void *data, int len);
580
581 void (*rx_skb)(struct mt76_dev *dev, enum mt76_rxq_id q,
582- struct sk_buff *skb);
583+ struct sk_buff *skb, u32 info);
584
585 void (*rx_poll_complete)(struct mt76_dev *dev, enum mt76_rxq_id q);
586
587@@ -747,6 +754,7 @@ struct mt76_dev {
588 struct ieee80211_hw *hw;
589
590 spinlock_t lock;
591+ spinlock_t wed_lock;
592 spinlock_t cc_lock;
593
594 u32 cur_cc_bss_rx;
595@@ -772,6 +780,7 @@ struct mt76_dev {
596 struct sk_buff_head rx_skb[__MT_RXQ_MAX];
597
598 struct list_head txwi_cache;
599+ struct list_head rxwi_cache;
600 struct mt76_queue *q_mcu[__MT_MCUQ_MAX];
601 struct mt76_queue q_rx[__MT_RXQ_MAX];
602 const struct mt76_queue_ops *queue_ops;
developerbbca0f92022-07-26 17:26:12 +0800603@@ -785,12 +794,16 @@ struct mt76_dev {
developer8cb3ac72022-07-04 10:55:14 +0800604 u16 wed_token_count;
605 u16 token_count;
606 u16 token_size;
607+ u16 rx_token_size;
608+ spinlock_t rx_token_lock;
609+ struct idr rx_token;
610
611 wait_queue_head_t tx_wait;
612 /* spinclock used to protect wcid pktid linked list */
developerbbca0f92022-07-26 17:26:12 +0800613 spinlock_t status_lock;
614
615 u32 wcid_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)];
616+ u32 wcid_wds_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)];
617 u32 wcid_phy_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)];
618
619 u64 vif_mask;
620@@ -1352,6 +1365,8 @@ mt76_tx_status_get_hw(struct mt76_dev *dev, struct sk_buff *skb)
developer8cb3ac72022-07-04 10:55:14 +0800621 }
622
623 void mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t);
624+void mt76_put_rxwi(struct mt76_dev *dev, struct mt76_txwi_cache *t);
625+struct mt76_txwi_cache *mt76_get_rxwi(struct mt76_dev *dev);
626 void mt76_rx_complete(struct mt76_dev *dev, struct sk_buff_head *frames,
627 struct napi_struct *napi);
628 void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q,
developerbbca0f92022-07-26 17:26:12 +0800629@@ -1496,6 +1511,12 @@ struct mt76_txwi_cache *
developer8cb3ac72022-07-04 10:55:14 +0800630 mt76_token_release(struct mt76_dev *dev, int token, bool *wake);
631 int mt76_token_consume(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi);
632 void __mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked);
633+int mt76_rx_token_consume(struct mt76_dev *dev, void *ptr,
634+ struct mt76_txwi_cache *r, dma_addr_t phys);
635+void skb_trace(const struct sk_buff *skb, bool full_pkt);
636+
637+struct mt76_txwi_cache *
638+mt76_rx_token_release(struct mt76_dev *dev, int token);
639
640 static inline void mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked)
641 {
642diff --git a/mt7603/dma.c b/mt7603/dma.c
developerc1b2cd12022-07-28 18:35:24 +0800643index 590cff9d..2ff71c53 100644
developer8cb3ac72022-07-04 10:55:14 +0800644--- a/mt7603/dma.c
645+++ b/mt7603/dma.c
646@@ -69,7 +69,7 @@ free:
647 }
648
649 void mt7603_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
650- struct sk_buff *skb)
651+ struct sk_buff *skb, u32 info)
652 {
653 struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76);
654 __le32 *rxd = (__le32 *)skb->data;
655diff --git a/mt7603/mt7603.h b/mt7603/mt7603.h
developerc1b2cd12022-07-28 18:35:24 +0800656index 0fd46d90..f2ce22ae 100644
developer8cb3ac72022-07-04 10:55:14 +0800657--- a/mt7603/mt7603.h
658+++ b/mt7603/mt7603.h
659@@ -244,7 +244,7 @@ int mt7603_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
660 void mt7603_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue_entry *e);
661
662 void mt7603_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
663- struct sk_buff *skb);
664+ struct sk_buff *skb, u32 info);
665 void mt7603_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q);
666 void mt7603_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps);
667 int mt7603_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif,
668diff --git a/mt7615/mac.c b/mt7615/mac.c
developerc1b2cd12022-07-28 18:35:24 +0800669index 37286276..14cdd9a2 100644
developer8cb3ac72022-07-04 10:55:14 +0800670--- a/mt7615/mac.c
671+++ b/mt7615/mac.c
developerf50c1802022-07-05 20:35:53 +0800672@@ -1648,7 +1648,7 @@ bool mt7615_rx_check(struct mt76_dev *mdev, void *data, int len)
developer8cb3ac72022-07-04 10:55:14 +0800673 EXPORT_SYMBOL_GPL(mt7615_rx_check);
674
675 void mt7615_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
676- struct sk_buff *skb)
677+ struct sk_buff *skb, u32 info)
678 {
679 struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
680 __le32 *rxd = (__le32 *)skb->data;
681diff --git a/mt7615/mt7615.h b/mt7615/mt7615.h
developerc1b2cd12022-07-28 18:35:24 +0800682index 25880d1a..983469c7 100644
developer8cb3ac72022-07-04 10:55:14 +0800683--- a/mt7615/mt7615.h
684+++ b/mt7615/mt7615.h
developerf50c1802022-07-05 20:35:53 +0800685@@ -511,7 +511,7 @@ void mt7615_tx_worker(struct mt76_worker *w);
developer8cb3ac72022-07-04 10:55:14 +0800686 void mt7615_tx_token_put(struct mt7615_dev *dev);
687 bool mt7615_rx_check(struct mt76_dev *mdev, void *data, int len);
688 void mt7615_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
689- struct sk_buff *skb);
690+ struct sk_buff *skb, u32 info);
691 void mt7615_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps);
692 int mt7615_mac_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif,
693 struct ieee80211_sta *sta);
694diff --git a/mt76_connac_mcu.c b/mt76_connac_mcu.c
developerc1b2cd12022-07-28 18:35:24 +0800695index cd350689..24548469 100644
developer8cb3ac72022-07-04 10:55:14 +0800696--- a/mt76_connac_mcu.c
697+++ b/mt76_connac_mcu.c
698@@ -1190,6 +1190,7 @@ int mt76_connac_mcu_sta_ba(struct mt76_dev *dev, struct mt76_vif *mvif,
699 int cmd, bool enable, bool tx)
700 {
701 struct mt76_wcid *wcid = (struct mt76_wcid *)params->sta->drv_priv;
702+ struct mtk_wed_device *wed = &dev->mmio.wed;
703 struct wtbl_req_hdr *wtbl_hdr;
704 struct tlv *sta_wtbl;
705 struct sk_buff *skb;
developerf50c1802022-07-05 20:35:53 +0800706@@ -1210,6 +1211,8 @@ int mt76_connac_mcu_sta_ba(struct mt76_dev *dev, struct mt76_vif *mvif,
developer8cb3ac72022-07-04 10:55:14 +0800707 mt76_connac_mcu_wtbl_ba_tlv(dev, skb, params, enable, tx, sta_wtbl,
708 wtbl_hdr);
709
developerf50c1802022-07-05 20:35:53 +0800710+ if (mtk_wed_device_active(wed) && wed->ver > MTK_WED_V1)
developer6adfa0e2022-07-06 16:25:53 +0800711+ mtk_wed_device_update_msg(wed, WED_WO_STA_REC, skb->data, skb->len);
developer8cb3ac72022-07-04 10:55:14 +0800712 ret = mt76_mcu_skb_send_msg(dev, skb, cmd, true);
713 if (ret)
714 return ret;
developerf50c1802022-07-05 20:35:53 +0800715@@ -1220,6 +1223,8 @@ int mt76_connac_mcu_sta_ba(struct mt76_dev *dev, struct mt76_vif *mvif,
developer8cb3ac72022-07-04 10:55:14 +0800716
717 mt76_connac_mcu_sta_ba_tlv(skb, params, enable, tx);
718
developerf50c1802022-07-05 20:35:53 +0800719+ if (mtk_wed_device_active(wed) && wed->ver > MTK_WED_V1)
720+ mtk_wed_device_update_msg(wed, WED_WO_STA_REC, skb->data, skb->len);
developer8cb3ac72022-07-04 10:55:14 +0800721 return mt76_mcu_skb_send_msg(dev, skb, cmd, true);
722 }
723 EXPORT_SYMBOL_GPL(mt76_connac_mcu_sta_ba);
developerf50c1802022-07-05 20:35:53 +0800724@@ -2634,6 +2639,7 @@ int mt76_connac_mcu_add_key(struct mt76_dev *dev, struct ieee80211_vif *vif,
developer8cb3ac72022-07-04 10:55:14 +0800725 struct mt76_wcid *wcid, enum set_key_cmd cmd)
726 {
727 struct mt76_vif *mvif = (struct mt76_vif *)vif->drv_priv;
728+ struct mtk_wed_device *wed = &dev->mmio.wed;
729 struct sk_buff *skb;
730 int ret;
731
developerf50c1802022-07-05 20:35:53 +0800732@@ -2645,6 +2651,9 @@ int mt76_connac_mcu_add_key(struct mt76_dev *dev, struct ieee80211_vif *vif,
developer8cb3ac72022-07-04 10:55:14 +0800733 if (ret)
734 return ret;
735
developerf50c1802022-07-05 20:35:53 +0800736+ if (mtk_wed_device_active(wed) && wed->ver > MTK_WED_V1)
developer8cb3ac72022-07-04 10:55:14 +0800737+ mtk_wed_device_update_msg(wed, WED_WO_STA_REC, skb->data, skb->len);
738+
739 return mt76_mcu_skb_send_msg(dev, skb, mcu_cmd, true);
740 }
741 EXPORT_SYMBOL_GPL(mt76_connac_mcu_add_key);
742diff --git a/mt76x02.h b/mt76x02.h
developerc1b2cd12022-07-28 18:35:24 +0800743index f76fd22e..0b872af1 100644
developer8cb3ac72022-07-04 10:55:14 +0800744--- a/mt76x02.h
745+++ b/mt76x02.h
746@@ -173,7 +173,7 @@ int mt76x02_set_rts_threshold(struct ieee80211_hw *hw, u32 val);
747 void mt76x02_remove_hdr_pad(struct sk_buff *skb, int len);
748 bool mt76x02_tx_status_data(struct mt76_dev *mdev, u8 *update);
749 void mt76x02_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
750- struct sk_buff *skb);
751+ struct sk_buff *skb, u32 info);
752 void mt76x02_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q);
753 irqreturn_t mt76x02_irq_handler(int irq, void *dev_instance);
754 void mt76x02_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control,
755diff --git a/mt76x02_txrx.c b/mt76x02_txrx.c
developerc1b2cd12022-07-28 18:35:24 +0800756index 96fdf423..bf24d3e0 100644
developer8cb3ac72022-07-04 10:55:14 +0800757--- a/mt76x02_txrx.c
758+++ b/mt76x02_txrx.c
759@@ -33,7 +33,7 @@ void mt76x02_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control,
760 EXPORT_SYMBOL_GPL(mt76x02_tx);
761
762 void mt76x02_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
763- struct sk_buff *skb)
764+ struct sk_buff *skb, u32 info)
765 {
766 struct mt76x02_dev *dev = container_of(mdev, struct mt76x02_dev, mt76);
767 void *rxwi = skb->data;
768diff --git a/mt7915/dma.c b/mt7915/dma.c
developerc1b2cd12022-07-28 18:35:24 +0800769index 71223221..7d8d60bb 100644
developer8cb3ac72022-07-04 10:55:14 +0800770--- a/mt7915/dma.c
771+++ b/mt7915/dma.c
developerc1b2cd12022-07-28 18:35:24 +0800772@@ -356,6 +356,7 @@ static int mt7915_dma_enable(struct mt7915_dev *dev)
773 int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2)
774 {
775 struct mt76_dev *mdev = &dev->mt76;
776+ struct mtk_wed_device *wed = &mdev->mmio.wed;
777 u32 wa_rx_base, wa_rx_idx;
778 u32 hif1_ofs = 0;
779 int ret;
780@@ -372,10 +373,12 @@ int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2)
781 if (mtk_wed_device_active(&dev->mt76.mmio.wed) && !is_mt7986(mdev)) {
782 mt76_set(dev, MT_WFDMA_HOST_CONFIG, MT_WFDMA_HOST_CONFIG_WED);
783 if(is_mt7915(mdev)) {
784- mt76_wr(dev, MT_WFDMA_WED_RING_CONTROL,
785- FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_TX0, 18) |
786- FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_TX1, 19) |
787- FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_RX1, 1));
788+ mt76_wr(dev, MT_WFDMA_WED_RING_CONTROL,
789+ FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_TX0, 18) |
790+ FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_TX1, 19) |
791+ FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_RX1, 1));
792+ mt76_rmw(dev, MT_WFDMA0_EXT0_CFG, MT_WFDMA0_EXT0_RXWB_KEEP,
793+ MT_WFDMA0_EXT0_RXWB_KEEP);
developer8cb3ac72022-07-04 10:55:14 +0800794 } else {
795 mt76_wr(dev, MT_WFDMA_WED_RING_CONTROL,
796 FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_TX0, 18) |
developerc1b2cd12022-07-28 18:35:24 +0800797@@ -435,7 +438,7 @@ int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2)
798 return ret;
799
800 /* event from WA */
801- if (mtk_wed_device_active(&dev->mt76.mmio.wed) && is_mt7915(mdev)) {
802+ if (mtk_wed_device_active(wed) && is_mt7915(mdev)) {
803 wa_rx_base = MT_WED_RX_RING_BASE;
804 wa_rx_idx = MT7915_RXQ_MCU_WA;
805 dev->mt76.q_rx[MT_RXQ_MCU_WA].flags = MT_WED_Q_TXFREE;
806@@ -451,6 +454,11 @@ int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2)
developer8cb3ac72022-07-04 10:55:14 +0800807
808 /* rx data queue for band0 */
809 if (!dev->phy.band_idx) {
developerc1b2cd12022-07-28 18:35:24 +0800810+ if (mtk_wed_device_active(wed) && wed->ver > MTK_WED_V1) {
developer8cb3ac72022-07-04 10:55:14 +0800811+ dev->mt76.q_rx[MT_RXQ_MAIN].flags = MT_WED_Q_RX(MT7915_RXQ_BAND0);
developerc1b2cd12022-07-28 18:35:24 +0800812+ dev->mt76.rx_token_size += MT7915_RX_RING_SIZE;
813+ }
developer8cb3ac72022-07-04 10:55:14 +0800814+
815 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN],
816 MT_RXQ_ID(MT_RXQ_MAIN),
817 MT7915_RX_RING_SIZE,
developerc1b2cd12022-07-28 18:35:24 +0800818@@ -465,7 +473,7 @@ int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2)
819 wa_rx_base = MT_RXQ_RING_BASE(MT_RXQ_MAIN_WA);
820 wa_rx_idx = MT_RXQ_ID(MT_RXQ_MAIN_WA);
821
822- if (mtk_wed_device_active(&dev->mt76.mmio.wed)) {
823+ if (mtk_wed_device_active(wed)) {
824 dev->mt76.q_rx[MT_RXQ_MAIN_WA].flags = MT_WED_Q_TXFREE;
825 if (is_mt7916(mdev)) {
826 wa_rx_base = MT_WED_RX_RING_BASE;
827@@ -482,6 +490,11 @@ int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2)
developer8cb3ac72022-07-04 10:55:14 +0800828
829 if (dev->dbdc_support || dev->phy.band_idx) {
830 /* rx data queue for band1 */
developerc1b2cd12022-07-28 18:35:24 +0800831+ if (mtk_wed_device_active(wed) && wed->ver > MTK_WED_V1) {
developer8cb3ac72022-07-04 10:55:14 +0800832+ dev->mt76.q_rx[MT_RXQ_EXT].flags = MT_WED_Q_RX(MT7915_RXQ_BAND1);
developerc1b2cd12022-07-28 18:35:24 +0800833+ dev->mt76.rx_token_size += MT7915_RX_RING_SIZE;
834+ }
developer8cb3ac72022-07-04 10:55:14 +0800835+
836 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_EXT],
837 MT_RXQ_ID(MT_RXQ_EXT),
838 MT7915_RX_RING_SIZE,
developerbbca0f92022-07-26 17:26:12 +0800839diff --git a/mt7915/init.c b/mt7915/init.c
developerc1b2cd12022-07-28 18:35:24 +0800840index b549fa04..eb321b77 100644
developerbbca0f92022-07-26 17:26:12 +0800841--- a/mt7915/init.c
842+++ b/mt7915/init.c
843@@ -695,6 +695,15 @@ mt7915_init_hardware(struct mt7915_dev *dev, struct mt7915_phy *phy2)
844 return ret;
845 }
846
847+ /* wds workaround for mt7986 */
848+ if (mtk_wed_device_active(&dev->mt76.mmio.wed) && is_mt7986(&dev->mt76)) {
849+ for(idx = MT7915_WTBL_WDS_START; idx < MT7915_WTBL_WDS_END; idx++)
850+ mt76_wcid_mask_set(dev->mt76.wcid_mask, idx);
851+
852+ for (idx = 0; idx < DIV_ROUND_UP(MT7915_WTBL_STA, 32); idx++)
853+ dev->mt76.wcid_wds_mask[idx] = ~dev->mt76.wcid_mask[idx];
854+ }
855+
856 /* Beacon and mgmt frames should occupy wcid 0 */
857 idx = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7915_WTBL_STA);
858 if (idx)
developer8cb3ac72022-07-04 10:55:14 +0800859diff --git a/mt7915/mac.c b/mt7915/mac.c
developerc1b2cd12022-07-28 18:35:24 +0800860index db21d83e..1f8e1230 100644
developer8cb3ac72022-07-04 10:55:14 +0800861--- a/mt7915/mac.c
862+++ b/mt7915/mac.c
863@@ -217,7 +217,7 @@ static void mt7915_mac_sta_poll(struct mt7915_dev *dev)
864 }
865
866 static int
867-mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
868+mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb, enum mt76_rxq_id q, u32 info)
869 {
870 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
871 struct mt76_phy *mphy = &dev->mt76.phy;
developera3f86ed2022-07-08 14:15:13 +0800872@@ -234,7 +234,7 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
873 bool unicast, insert_ccmp_hdr = false;
874 u8 remove_pad, amsdu_info;
875 u8 mode = 0, qos_ctl = 0;
876- struct mt7915_sta *msta;
877+ struct mt7915_sta *msta = NULL;
878 bool hdr_trans;
879 u16 hdr_gap;
880 u16 seq_ctrl = 0;
developer8cb3ac72022-07-04 10:55:14 +0800881@@ -494,6 +494,27 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
882 #endif
883 } else {
884 status->flag |= RX_FLAG_8023;
developera3f86ed2022-07-08 14:15:13 +0800885+ if (msta && msta->vif) {
developer8cb3ac72022-07-04 10:55:14 +0800886+ struct mtk_wed_device *wed;
887+ int type;
888+
889+ wed = &dev->mt76.mmio.wed;
890+ type = FIELD_GET(MT_QFLAG_WED_TYPE, dev->mt76.q_rx[q].flags);
891+ if ((mtk_wed_device_active(wed) && type == MT76_WED_Q_RX) &&
developera3f86ed2022-07-08 14:15:13 +0800892+ (info & MT_DMA_INFO_PPE_VLD)) {
developer8cb3ac72022-07-04 10:55:14 +0800893+ struct ieee80211_vif *vif;
894+ u32 hash, reason;
895+
896+ vif = container_of((void *)msta->vif, struct ieee80211_vif,
developera3f86ed2022-07-08 14:15:13 +0800897+ drv_priv);
developer8cb3ac72022-07-04 10:55:14 +0800898+
899+ skb->dev = ieee80211_vif_to_netdev(vif);
900+ reason = FIELD_GET(MT_DMA_PPE_CPU_REASON, info);
901+ hash = FIELD_GET(MT_DMA_PPE_ENTRY, info);
902+
903+ mtk_wed_device_ppe_check(wed, skb, reason, hash);
904+ }
905+ }
906 }
907
908 if (rxv && mode >= MT_PHY_TYPE_HE_SU && !(status->flag & RX_FLAG_8023))
developera3f86ed2022-07-08 14:15:13 +0800909@@ -840,6 +861,80 @@ u32 mt7915_wed_init_buf(void *ptr, dma_addr_t phys, int token_id)
developer8cb3ac72022-07-04 10:55:14 +0800910 return MT_TXD_TXP_BUF_SIZE;
911 }
912
913+u32
914+mt7915_wed_init_rx_buf(struct mtk_wed_device *wed, int pkt_num)
915+{
916+ struct mtk_rxbm_desc *desc = wed->rx_buf_ring.desc;
917+ struct mt7915_dev *dev;
918+ dma_addr_t buf_phys;
919+ void *buf;
920+ int i, token, buf_size;
921+
922+ buf_size = SKB_DATA_ALIGN(NET_SKB_PAD + wed->wlan.rx_pkt_size) +
923+ SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
924+
925+ dev = container_of(wed, struct mt7915_dev, mt76.mmio.wed);
926+ for (i = 0; i < pkt_num; i++) {
927+ struct mt76_txwi_cache *r = mt76_get_rxwi(&dev->mt76);
928+
929+ buf = page_frag_alloc(&wed->rx_page, buf_size, GFP_ATOMIC);
930+ if (!buf)
931+ return -ENOMEM;
932+
933+ buf_phys = dma_map_single(dev->mt76.dma_dev, buf, wed->wlan.rx_pkt_size,
934+ DMA_TO_DEVICE);
935+
936+ if (unlikely(dma_mapping_error(dev->mt76.dev, buf_phys))) {
937+ skb_free_frag(buf);
938+ break;
939+ }
940+
941+ desc->buf0 = buf_phys;
942+
943+ token = mt76_rx_token_consume(&dev->mt76, buf, r, buf_phys);
944+
945+ desc->token |= FIELD_PREP(MT_DMA_CTL_TOKEN, token);
946+ desc++;
947+ }
948+
949+ return 0;
950+}
951+
952+void mt7915_wed_release_rx_buf(struct mtk_wed_device *wed)
953+{
954+ struct mt76_txwi_cache *rxwi;
955+ struct mt7915_dev *dev;
developera3f86ed2022-07-08 14:15:13 +0800956+ struct page *page;
developer8cb3ac72022-07-04 10:55:14 +0800957+ int token;
958+
959+ dev = container_of(wed, struct mt7915_dev, mt76.mmio.wed);
960+
961+ for(token = 0; token < dev->mt76.rx_token_size; token++) {
962+ rxwi = mt76_rx_token_release(&dev->mt76, token);
963+ if(!rxwi)
964+ continue;
965+
developera3f86ed2022-07-08 14:15:13 +0800966+ if(!rxwi->buf)
967+ continue;
968+
developer8cb3ac72022-07-04 10:55:14 +0800969+ dma_unmap_single(dev->mt76.dma_dev, rxwi->dma_addr,
970+ wed->wlan.rx_pkt_size, DMA_FROM_DEVICE);
971+ skb_free_frag(rxwi->buf);
972+ rxwi->buf = NULL;
973+
974+ mt76_put_rxwi(&dev->mt76, rxwi);
975+ }
developera3f86ed2022-07-08 14:15:13 +0800976+
977+ if (wed->rx_page.va)
978+ return;
979+
980+ page = virt_to_page(wed->rx_page.va);
981+ __page_frag_cache_drain(page, wed->rx_page.pagecnt_bias);
982+ memset(&wed->rx_page, 0, sizeof(wed->rx_page));
983+
developer8cb3ac72022-07-04 10:55:14 +0800984+ return;
985+}
986+
987 static void
988 mt7915_tx_check_aggr(struct ieee80211_sta *sta, __le32 *txwi)
989 {
developera3f86ed2022-07-08 14:15:13 +0800990@@ -1120,7 +1215,7 @@ bool mt7915_rx_check(struct mt76_dev *mdev, void *data, int len)
developer8cb3ac72022-07-04 10:55:14 +0800991 }
992
993 void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
994- struct sk_buff *skb)
995+ struct sk_buff *skb, u32 info)
996 {
997 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
998 __le32 *rxd = (__le32 *)skb->data;
developera3f86ed2022-07-08 14:15:13 +0800999@@ -1154,7 +1249,7 @@ void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
developer8cb3ac72022-07-04 10:55:14 +08001000 dev_kfree_skb(skb);
1001 break;
1002 case PKT_TYPE_NORMAL:
1003- if (!mt7915_mac_fill_rx(dev, skb)) {
1004+ if (!mt7915_mac_fill_rx(dev, skb, q, info)) {
1005 mt76_rx(&dev->mt76, q, skb);
1006 return;
1007 }
developerbbca0f92022-07-26 17:26:12 +08001008diff --git a/mt7915/main.c b/mt7915/main.c
developerc1b2cd12022-07-28 18:35:24 +08001009index 2e721cd0..9c808ff4 100644
developerbbca0f92022-07-26 17:26:12 +08001010--- a/mt7915/main.c
1011+++ b/mt7915/main.c
1012@@ -670,8 +670,15 @@ int mt7915_mac_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif,
1013 #endif
1014 int ret, idx;
1015 u32 addr;
1016+ bool wed_wds = false;
1017
1018- idx = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7915_WTBL_STA);
1019+ if (mtk_wed_device_active(&mdev->mmio.wed))
1020+ wed_wds = !!test_bit(MT_WCID_FLAG_4ADDR, &msta->wcid.flags);
1021+
1022+ if (wed_wds)
1023+ idx = mt76_wcid_alloc(mdev->wcid_wds_mask, MT7915_WTBL_STA);
1024+ else
1025+ idx = mt76_wcid_alloc(mdev->wcid_mask, MT7915_WTBL_STA);
1026 if (idx < 0)
1027 return -ENOSPC;
1028
1029@@ -1107,6 +1114,13 @@ static void mt7915_sta_set_4addr(struct ieee80211_hw *hw,
1030 else
1031 clear_bit(MT_WCID_FLAG_4ADDR, &msta->wcid.flags);
1032
1033+ if (mtk_wed_device_active(&dev->mt76.mmio.wed) &&
1034+ (msta->wcid.idx < MT7915_WTBL_WDS_START ||
1035+ msta->wcid.idx > MT7915_WTBL_WDS_END)) {
1036+ mt7915_sta_remove(hw, vif, sta);
1037+ mt7915_sta_add(hw, vif, sta);
1038+ }
1039+
1040 mt76_connac_mcu_wtbl_update_hdr_trans(&dev->mt76, vif, sta);
1041 }
1042
1043@@ -1449,9 +1463,12 @@ mt7915_net_fill_forward_path(struct ieee80211_hw *hw,
1044 /* fw will find the wcid by dest addr */
1045 if(is_mt7915(&dev->mt76))
1046 path->mtk_wdma.wcid = 0xff;
1047- else
1048- path->mtk_wdma.wcid = 0x3ff;
1049-
1050+ else {
1051+ if (test_bit(MT_WCID_FLAG_4ADDR, &msta->wcid.flags))
1052+ path->mtk_wdma.wcid = msta->wcid.idx;
1053+ else
1054+ path->mtk_wdma.wcid = 0x3ff;
1055+ }
1056 path->mtk_wdma.queue = phy != &dev->phy;
1057
1058 ctx->dev = NULL;
developer8cb3ac72022-07-04 10:55:14 +08001059diff --git a/mt7915/mcu.c b/mt7915/mcu.c
developerc1b2cd12022-07-28 18:35:24 +08001060index 9e9a2ea0..dd712283 100644
developer8cb3ac72022-07-04 10:55:14 +08001061--- a/mt7915/mcu.c
1062+++ b/mt7915/mcu.c
developerbbca0f92022-07-26 17:26:12 +08001063@@ -1719,6 +1719,7 @@ int mt7915_mcu_add_sta(struct mt7915_dev *dev, struct ieee80211_vif *vif,
developer8cb3ac72022-07-04 10:55:14 +08001064 struct ieee80211_sta *sta, bool enable)
1065 {
1066 struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv;
1067+ struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
1068 struct mt7915_sta *msta;
1069 struct sk_buff *skb;
1070 int ret;
developerbbca0f92022-07-26 17:26:12 +08001071@@ -1771,6 +1772,8 @@ int mt7915_mcu_add_sta(struct mt7915_dev *dev, struct ieee80211_vif *vif,
developer8cb3ac72022-07-04 10:55:14 +08001072 return ret;
1073 }
1074 out:
developerf50c1802022-07-05 20:35:53 +08001075+ if (mtk_wed_device_active(wed) && wed->ver > MTK_WED_V1)
1076+ mtk_wed_device_update_msg(wed, WED_WO_STA_REC, skb->data, skb->len);
developer8cb3ac72022-07-04 10:55:14 +08001077 return mt76_mcu_skb_send_msg(&dev->mt76, skb,
1078 MCU_EXT_CMD(STA_REC_UPDATE), true);
1079 }
developerbbca0f92022-07-26 17:26:12 +08001080@@ -2348,6 +2351,7 @@ mt7915_mcu_init_rx_airtime(struct mt7915_dev *dev)
1081 int mt7915_run_firmware(struct mt7915_dev *dev)
1082 {
1083 int ret;
1084+ struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
1085
1086 /* force firmware operation mode into normal state,
1087 * which should be set before firmware download stage.
1088@@ -2377,8 +2381,14 @@ int mt7915_run_firmware(struct mt7915_dev *dev)
1089 if (ret)
1090 return ret;
1091
1092- if (mtk_wed_device_active(&dev->mt76.mmio.wed) && is_mt7915(&dev->mt76))
1093- mt7915_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(CAPABILITY), 0, 0, 0);
1094+ if (mtk_wed_device_active(wed)) {
developerc1b2cd12022-07-28 18:35:24 +08001095+ if (is_mt7915(&dev->mt76))
developerbbca0f92022-07-26 17:26:12 +08001096+ mt7915_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(CAPABILITY),
1097+ 0, 0, 0);
1098+ mt7915_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET),
1099+ MCU_WA_PARAM_WED_VERSION,
1100+ wed->rev_id, 0);
1101+ }
1102
1103 ret = mt7915_mcu_set_mwds(dev, 1);
1104 if (ret)
1105diff --git a/mt7915/mcu.h b/mt7915/mcu.h
developerc1b2cd12022-07-28 18:35:24 +08001106index b8a433e5..ce50e606 100644
developerbbca0f92022-07-26 17:26:12 +08001107--- a/mt7915/mcu.h
1108+++ b/mt7915/mcu.h
1109@@ -268,6 +268,7 @@ enum {
1110 MCU_WA_PARAM_RED_SHOW_STA = 0xf,
1111 MCU_WA_PARAM_RED_TARGET_DELAY = 0x10,
1112 #endif
1113+ MCU_WA_PARAM_WED_VERSION = 0x32,
1114 };
1115
1116 enum mcu_mmps_mode {
developer8cb3ac72022-07-04 10:55:14 +08001117diff --git a/mt7915/mmio.c b/mt7915/mmio.c
developerc1b2cd12022-07-28 18:35:24 +08001118index b4a3120d..9316e056 100644
developer8cb3ac72022-07-04 10:55:14 +08001119--- a/mt7915/mmio.c
1120+++ b/mt7915/mmio.c
1121@@ -28,6 +28,9 @@ static const u32 mt7915_reg[] = {
1122 [FW_EXCEPTION_ADDR] = 0x219848,
1123 [SWDEF_BASE_ADDR] = 0x41f200,
1124 [EXCEPTION_BASE_ADDR] = 0x219848,
1125+ [WED_TX_RING] = 0xd7300,
1126+ [WED_RX_RING] = 0xd7410,
1127+ [WED_RX_DATA_RING] = 0xd4500,
1128 };
1129
1130 static const u32 mt7916_reg[] = {
1131@@ -45,6 +48,9 @@ static const u32 mt7916_reg[] = {
1132 [FW_EXCEPTION_ADDR] = 0x022050bc,
1133 [SWDEF_BASE_ADDR] = 0x411400,
1134 [EXCEPTION_BASE_ADDR] = 0x022050BC,
1135+ [WED_TX_RING] = 0xd7300,
1136+ [WED_RX_RING] = 0xd7410,
1137+ [WED_RX_DATA_RING] = 0xd4540,
1138 };
1139
1140 static const u32 mt7986_reg[] = {
1141@@ -62,6 +68,9 @@ static const u32 mt7986_reg[] = {
1142 [FW_EXCEPTION_ADDR] = 0x02204ffc,
1143 [SWDEF_BASE_ADDR] = 0x411400,
1144 [EXCEPTION_BASE_ADDR] = 0x02204FFC,
1145+ [WED_TX_RING] = 0x24420,
1146+ [WED_RX_RING] = 0x24520,
1147+ [WED_RX_DATA_RING] = 0x24540,
1148 };
1149
1150 static const u32 mt7915_offs[] = {
developerf50c1802022-07-05 20:35:53 +08001151@@ -710,6 +719,7 @@ mt7915_pci_wed_init(struct mt7915_dev *dev, struct device *pdev, int *irq)
1152 wed->wlan.bus_type = MTK_BUS_TYPE_PCIE;
1153 wed->wlan.wpdma_int = base + MT_INT_WED_SOURCE_CSR;
1154 wed->wlan.wpdma_mask = base + MT_INT_WED_MASK_CSR;
1155+ wed->wlan.wpdma_phys = base + MT_WFDMA_EXT_CSR_BASE;
1156 } else {
1157 struct platform_device *plat_dev;
1158 struct resource *res;
1159@@ -722,12 +732,19 @@ mt7915_pci_wed_init(struct mt7915_dev *dev, struct device *pdev, int *irq)
developer8cb3ac72022-07-04 10:55:14 +08001160 wed->wlan.wpdma_int = base + MT_INT_SOURCE_CSR;
1161 wed->wlan.wpdma_mask = base + MT_INT_MASK_CSR;
1162 }
1163+ wed->wlan.rx_pkt = MT7915_WED_RX_TOKEN_SIZE;
1164+ wed->wlan.phy_base = base;
1165 wed->wlan.wpdma_tx = base + MT_TXQ_WED_RING_BASE;
1166 wed->wlan.wpdma_txfree = base + MT_RXQ_WED_RING_BASE;
1167+ wed->wlan.wpdma_rx_glo = base + MT_WPDMA_GLO_CFG;
1168+ wed->wlan.wpdma_rx = base + MT_RXQ_WED_DATA_RING_BASE;
1169
1170 wed->wlan.tx_tbit[0] = MT_WED_TX_DONE_BAND0;
1171 wed->wlan.tx_tbit[1] = MT_WED_TX_DONE_BAND1;
1172 wed->wlan.txfree_tbit = MT_WED_TX_FREE_DONE;
1173+ wed->wlan.rx_tbit[0] = MT_WED_RX_DONE_BAND0;
1174+ wed->wlan.rx_tbit[1] = MT_WED_RX_DONE_BAND1;
1175+
1176 wed->wlan.nbuf = 7168;
1177 wed->wlan.token_start = MT7915_TOKEN_SIZE - wed->wlan.nbuf;
1178 wed->wlan.init_buf = mt7915_wed_init_buf;
developerf50c1802022-07-05 20:35:53 +08001179@@ -735,12 +752,15 @@ mt7915_pci_wed_init(struct mt7915_dev *dev, struct device *pdev, int *irq)
developer8cb3ac72022-07-04 10:55:14 +08001180 wed->wlan.offload_enable = mt7915_wed_offload_enable;
1181 wed->wlan.offload_disable = mt7915_wed_offload_disable;
1182
1183+ wed->wlan.rx_nbuf = 65536;
1184+ wed->wlan.rx_pkt_size = MTK_WED_RX_PKT_SIZE;
1185+ wed->wlan.init_rx_buf = mt7915_wed_init_rx_buf;
1186+ wed->wlan.release_rx_buf = mt7915_wed_release_rx_buf;
1187+
developerc1b2cd12022-07-28 18:35:24 +08001188+ dev->mt76.rx_token_size = wed->wlan.rx_pkt;
developer8cb3ac72022-07-04 10:55:14 +08001189 if (mtk_wed_device_attach(wed) != 0)
1190 return 0;
1191
developerf50c1802022-07-05 20:35:53 +08001192- if (wed->ver == MTK_WED_V1)
1193- wed->wlan.wpdma_phys = base + MT_WFDMA_EXT_CSR_BASE;
1194-
1195 *irq = wed->irq;
1196 dev->mt76.dma_dev = wed->dev;
1197 mdev->token_size = wed->wlan.token_start;
developer8cb3ac72022-07-04 10:55:14 +08001198diff --git a/mt7915/mt7915.h b/mt7915/mt7915.h
developerc1b2cd12022-07-28 18:35:24 +08001199index 39127922..97eac730 100644
developer8cb3ac72022-07-04 10:55:14 +08001200--- a/mt7915/mt7915.h
1201+++ b/mt7915/mt7915.h
developerbbca0f92022-07-26 17:26:12 +08001202@@ -18,6 +18,9 @@
1203 #define MT7915_WTBL_STA (MT7915_WTBL_RESERVED - \
1204 MT7915_MAX_INTERFACES)
1205
1206+#define MT7915_WTBL_WDS_START 256
1207+#define MT7915_WTBL_WDS_END 274
1208+
1209 #define MT7915_WATCHDOG_TIME (HZ / 10)
1210 #define MT7915_RESET_TIMEOUT (30 * HZ)
1211
1212@@ -78,6 +81,7 @@
developer8cb3ac72022-07-04 10:55:14 +08001213 #define MT7915_MAX_STA_TWT_AGRT 8
1214 #define MT7915_MIN_TWT_DUR 64
1215 #define MT7915_MAX_QUEUE (__MT_RXQ_MAX + __MT_MCUQ_MAX + 2)
1216+#define MT7915_WED_RX_TOKEN_SIZE 12288
1217
1218 struct mt7915_vif;
1219 struct mt7915_sta;
developerbbca0f92022-07-26 17:26:12 +08001220@@ -541,7 +545,9 @@ void mt7915_wfsys_reset(struct mt7915_dev *dev);
developer8cb3ac72022-07-04 10:55:14 +08001221 irqreturn_t mt7915_irq_handler(int irq, void *dev_instance);
1222 u64 __mt7915_get_tsf(struct ieee80211_hw *hw, struct mt7915_vif *mvif);
1223 u32 mt7915_wed_init_buf(void *ptr, dma_addr_t phys, int token_id);
1224-
1225+u32 mt7915_wed_init_rx_buf(struct mtk_wed_device *wed,
1226+ int pkt_num);
1227+void mt7915_wed_release_rx_buf(struct mtk_wed_device *wed);
1228 int mt7915_register_device(struct mt7915_dev *dev);
1229 void mt7915_unregister_device(struct mt7915_dev *dev);
1230 int mt7915_eeprom_init(struct mt7915_dev *dev);
developerbbca0f92022-07-26 17:26:12 +08001231@@ -693,7 +699,7 @@ int mt7915_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
developer8cb3ac72022-07-04 10:55:14 +08001232 struct mt76_tx_info *tx_info);
1233 void mt7915_tx_token_put(struct mt7915_dev *dev);
1234 void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1235- struct sk_buff *skb);
1236+ struct sk_buff *skb, u32 info);
1237 bool mt7915_rx_check(struct mt76_dev *mdev, void *data, int len);
1238 void mt7915_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps);
1239 void mt7915_stats_work(struct work_struct *work);
1240diff --git a/mt7915/regs.h b/mt7915/regs.h
developerc1b2cd12022-07-28 18:35:24 +08001241index ffda5f6b..08bf84ce 100644
developer8cb3ac72022-07-04 10:55:14 +08001242--- a/mt7915/regs.h
1243+++ b/mt7915/regs.h
1244@@ -33,6 +33,9 @@ enum reg_rev {
1245 FW_EXCEPTION_ADDR,
1246 SWDEF_BASE_ADDR,
1247 EXCEPTION_BASE_ADDR,
1248+ WED_TX_RING,
1249+ WED_RX_RING,
1250+ WED_RX_DATA_RING,
1251 __MT_REG_MAX,
1252 };
1253
1254@@ -570,9 +573,13 @@ enum offs_rev {
1255 #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2 BIT(21)
1256
1257 #define MT_WFDMA0_RST_DTX_PTR MT_WFDMA0(0x20c)
1258+#define MT_WFDMA0_EXT0_CFG MT_WFDMA0(0x2b0)
1259+#define MT_WFDMA0_EXT0_RXWB_KEEP BIT(10)
1260+
1261 #define MT_WFDMA0_PRI_DLY_INT_CFG0 MT_WFDMA0(0x2f0)
1262 #define MT_WFDMA0_PRI_DLY_INT_CFG1 MT_WFDMA0(0x2f4)
1263 #define MT_WFDMA0_PRI_DLY_INT_CFG2 MT_WFDMA0(0x2f8)
1264+#define MT_WPDMA_GLO_CFG MT_WFDMA0(0x208)
1265
1266 #define MT_WFDMA0_MCU_HOST_INT_ENA MT_WFDMA0(0x1f4)
1267 #define MT_WFDMA0_MT_WA_WDT_INT BIT(31)
1268@@ -670,12 +677,15 @@ enum offs_rev {
1269 #define MT_TXQ_EXT_CTRL(q) (MT_Q_BASE(__TXQ(q)) + 0x600 + \
1270 MT_TXQ_ID(q)* 0x4)
1271
1272-#define MT_TXQ_WED_RING_BASE (!is_mt7986(mdev)? 0xd7300 : 0x24420)
1273-#define MT_RXQ_WED_RING_BASE (!is_mt7986(mdev)? 0xd7410 : 0x24520)
1274+#define MT_TXQ_WED_RING_BASE __REG(WED_TX_RING)
1275+#define MT_RXQ_WED_RING_BASE __REG(WED_RX_RING)
1276+#define MT_RXQ_WED_DATA_RING_BASE __REG(WED_RX_DATA_RING)
1277
1278 #define MT_WED_TX_DONE_BAND0 (is_mt7915(mdev)? 4 : 30)
1279 #define MT_WED_TX_DONE_BAND1 (is_mt7915(mdev)? 5 : 31)
1280 #define MT_WED_TX_FREE_DONE (is_mt7915(mdev)? 1 : 2)
1281+#define MT_WED_RX_DONE_BAND0 (is_mt7915(mdev)? 16 : 22)
1282+#define MT_WED_RX_DONE_BAND1 (is_mt7915(mdev)? 17 : 23)
1283
1284 #define MT_INT_SOURCE_CSR __REG(INT_SOURCE_CSR)
1285 #define MT_INT_MASK_CSR __REG(INT_MASK_CSR)
1286diff --git a/mt7921/mac.c b/mt7921/mac.c
developerc1b2cd12022-07-28 18:35:24 +08001287index 4fcadf86..4897940b 100644
developer8cb3ac72022-07-04 10:55:14 +08001288--- a/mt7921/mac.c
1289+++ b/mt7921/mac.c
1290@@ -555,7 +555,7 @@ out:
1291 EXPORT_SYMBOL_GPL(mt7921_mac_add_txs);
1292
1293 void mt7921_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1294- struct sk_buff *skb)
1295+ struct sk_buff *skb, u32 info)
1296 {
1297 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
1298 __le32 *rxd = (__le32 *)skb->data;
1299diff --git a/mt7921/mt7921.h b/mt7921/mt7921.h
developerc1b2cd12022-07-28 18:35:24 +08001300index efeb82cb..4b2e974b 100644
developer8cb3ac72022-07-04 10:55:14 +08001301--- a/mt7921/mt7921.h
1302+++ b/mt7921/mt7921.h
1303@@ -388,7 +388,7 @@ int mt7921e_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
1304 void mt7921_tx_worker(struct mt76_worker *w);
1305 void mt7921_tx_token_put(struct mt7921_dev *dev);
1306 void mt7921_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1307- struct sk_buff *skb);
1308+ struct sk_buff *skb, u32 info);
1309 void mt7921_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps);
1310 void mt7921_stats_work(struct work_struct *work);
1311 void mt7921_set_stream_he_caps(struct mt7921_phy *phy);
1312@@ -424,7 +424,7 @@ int mt7921_mcu_parse_response(struct mt76_dev *mdev, int cmd,
1313
1314 bool mt7921e_rx_check(struct mt76_dev *mdev, void *data, int len);
1315 void mt7921e_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1316- struct sk_buff *skb);
1317+ struct sk_buff *skb, u32 info);
1318 int mt7921e_driver_own(struct mt7921_dev *dev);
1319 int mt7921e_mac_reset(struct mt7921_dev *dev);
1320 int mt7921e_mcu_init(struct mt7921_dev *dev);
1321diff --git a/mt7921/pci_mac.c b/mt7921/pci_mac.c
developerc1b2cd12022-07-28 18:35:24 +08001322index e1800674..ca982eb5 100644
developer8cb3ac72022-07-04 10:55:14 +08001323--- a/mt7921/pci_mac.c
1324+++ b/mt7921/pci_mac.c
1325@@ -182,7 +182,7 @@ bool mt7921e_rx_check(struct mt76_dev *mdev, void *data, int len)
1326 }
1327
1328 void mt7921e_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1329- struct sk_buff *skb)
1330+ struct sk_buff *skb, u32 info)
1331 {
1332 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
1333 __le32 *rxd = (__le32 *)skb->data;
1334@@ -196,7 +196,7 @@ void mt7921e_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1335 napi_consume_skb(skb, 1);
1336 break;
1337 default:
1338- mt7921_queue_rx_skb(mdev, q, skb);
1339+ mt7921_queue_rx_skb(mdev, q, skb, info);
1340 break;
1341 }
1342 }
1343diff --git a/tx.c b/tx.c
developerc1b2cd12022-07-28 18:35:24 +08001344index ae44afe0..bccd206e 100644
developer8cb3ac72022-07-04 10:55:14 +08001345--- a/tx.c
1346+++ b/tx.c
developerf50c1802022-07-05 20:35:53 +08001347@@ -767,3 +767,37 @@ mt76_token_release(struct mt76_dev *dev, int token, bool *wake)
developer8cb3ac72022-07-04 10:55:14 +08001348 return txwi;
1349 }
1350 EXPORT_SYMBOL_GPL(mt76_token_release);
1351+
1352+int mt76_rx_token_consume(struct mt76_dev *dev, void *ptr,
1353+ struct mt76_txwi_cache *r, dma_addr_t phys)
1354+{
1355+ int token;
1356+
1357+ spin_lock_bh(&dev->rx_token_lock);
1358+
1359+ token = idr_alloc(&dev->rx_token, r, 0, dev->rx_token_size, GFP_ATOMIC);
1360+
1361+ spin_unlock_bh(&dev->rx_token_lock);
1362+
1363+ r->buf = ptr;
1364+ r->dma_addr = phys;
1365+
1366+ return token;
1367+}
1368+EXPORT_SYMBOL_GPL(mt76_rx_token_consume);
1369+
1370+struct mt76_txwi_cache *
1371+mt76_rx_token_release(struct mt76_dev *dev, int token)
1372+{
1373+
1374+ struct mt76_txwi_cache *rxwi;
1375+
1376+ spin_lock_bh(&dev->rx_token_lock);
1377+
1378+ rxwi = idr_remove(&dev->rx_token, token);
1379+
1380+ spin_unlock_bh(&dev->rx_token_lock);
1381+
1382+ return rxwi;
1383+}
1384+EXPORT_SYMBOL_GPL(mt76_rx_token_release);
1385--
developerbbca0f92022-07-26 17:26:12 +080013862.18.0
developer8cb3ac72022-07-04 10:55:14 +08001387