blob: 5c5a05d418b18a0aff0b75ac4aca47fc9f45b17c [file] [log] [blame]
developerf50c1802022-07-05 20:35:53 +08001From 1abac441c94f3f32bd074b8b01c439263129102d Mon Sep 17 00:00:00 2001
developer8cb3ac72022-07-04 10:55:14 +08002From: Sujuan Chen <sujuan.chen@mediatek.com>
developerf50c1802022-07-05 20:35:53 +08003Date: Tue, 5 Jul 2022 19:42:55 +0800
developer8cb3ac72022-07-04 10:55:14 +08004Subject: [PATCH 2/3] mt76 add wed rx support
5
6Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
7---
developerf50c1802022-07-05 20:35:53 +08008 dma.c | 219 +++++++++++++++++++++++++++++++++--------
9 dma.h | 10 ++
developer8cb3ac72022-07-04 10:55:14 +080010 mac80211.c | 8 +-
11 mt76.h | 24 ++++-
12 mt7603/dma.c | 2 +-
13 mt7603/mt7603.h | 2 +-
14 mt7615/mac.c | 2 +-
15 mt7615/mt7615.h | 2 +-
developerf50c1802022-07-05 20:35:53 +080016 mt76_connac_mcu.c | 9 ++
developer8cb3ac72022-07-04 10:55:14 +080017 mt76x02.h | 2 +-
18 mt76x02_txrx.c | 2 +-
developerf50c1802022-07-05 20:35:53 +080019 mt7915/dma.c | 10 ++
20 mt7915/mac.c | 89 ++++++++++++++++-
21 mt7915/mcu.c | 3 +
22 mt7915/mmio.c | 26 ++++-
developer8cb3ac72022-07-04 10:55:14 +080023 mt7915/mt7915.h | 7 +-
24 mt7915/regs.h | 14 ++-
25 mt7921/mac.c | 2 +-
26 mt7921/mt7921.h | 4 +-
27 mt7921/pci_mac.c | 4 +-
28 tx.c | 34 +++++++
developerf50c1802022-07-05 20:35:53 +080029 21 files changed, 410 insertions(+), 65 deletions(-)
30 mode change 100755 => 100644 mt7915/mac.c
31 mode change 100755 => 100644 mt7915/mmio.c
developer8cb3ac72022-07-04 10:55:14 +080032
33diff --git a/dma.c b/dma.c
developerf50c1802022-07-05 20:35:53 +080034index 03ee910..094aede 100644
developer8cb3ac72022-07-04 10:55:14 +080035--- a/dma.c
36+++ b/dma.c
37@@ -98,6 +98,63 @@ mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t)
38 }
39 EXPORT_SYMBOL_GPL(mt76_put_txwi);
40
41+static struct mt76_txwi_cache *
42+mt76_alloc_rxwi(struct mt76_dev *dev)
43+{
44+ struct mt76_txwi_cache *r;
45+ int size;
46+
47+ size = L1_CACHE_ALIGN(sizeof(*r));
48+ r = kzalloc(size, GFP_ATOMIC);
49+ if (!r)
50+ return NULL;
51+
52+ r->buf = NULL;
53+
54+ return r;
55+}
56+
57+static struct mt76_txwi_cache *
58+__mt76_get_rxwi(struct mt76_dev *dev)
59+{
60+ struct mt76_txwi_cache *r = NULL;
61+
62+ spin_lock(&dev->wed_lock);
63+ if (!list_empty(&dev->rxwi_cache)) {
64+ r = list_first_entry(&dev->rxwi_cache, struct mt76_txwi_cache,
65+ list);
66+ if(r)
67+ list_del(&r->list);
68+ }
69+ spin_unlock(&dev->wed_lock);
70+
71+ return r;
72+}
73+
74+struct mt76_txwi_cache *
75+mt76_get_rxwi(struct mt76_dev *dev)
76+{
77+ struct mt76_txwi_cache *r = __mt76_get_rxwi(dev);
78+
79+ if (r)
80+ return r;
81+
82+ return mt76_alloc_rxwi(dev);
83+}
84+EXPORT_SYMBOL_GPL(mt76_get_rxwi);
85+
86+void
87+mt76_put_rxwi(struct mt76_dev *dev, struct mt76_txwi_cache *r)
88+{
89+ if (!r)
90+ return;
91+
92+ spin_lock(&dev->wed_lock);
93+ list_add(&r->list, &dev->rxwi_cache);
94+ spin_unlock(&dev->wed_lock);
95+}
96+EXPORT_SYMBOL_GPL(mt76_put_rxwi);
97+
98 static void
99 mt76_free_pending_txwi(struct mt76_dev *dev)
100 {
101@@ -141,12 +198,15 @@ mt76_dma_queue_reset(struct mt76_dev *dev, struct mt76_queue *q)
102 static int
103 mt76_dma_add_buf(struct mt76_dev *dev, struct mt76_queue *q,
104 struct mt76_queue_buf *buf, int nbufs, u32 info,
105- struct sk_buff *skb, void *txwi)
106+ struct sk_buff *skb, void *txwi, void *rxwi)
107 {
108+ struct mtk_wed_device *wed = &dev->mmio.wed;
109+
110 struct mt76_queue_entry *entry;
111 struct mt76_desc *desc;
112 u32 ctrl;
113 int i, idx = -1;
114+ int type;
115
116 if (txwi) {
117 q->entry[q->head].txwi = DMA_DUMMY_DATA;
118@@ -162,28 +222,42 @@ mt76_dma_add_buf(struct mt76_dev *dev, struct mt76_queue *q,
119 desc = &q->desc[idx];
120 entry = &q->entry[idx];
121
122- if (buf[0].skip_unmap)
123- entry->skip_buf0 = true;
124- entry->skip_buf1 = i == nbufs - 1;
125-
126- entry->dma_addr[0] = buf[0].addr;
127- entry->dma_len[0] = buf[0].len;
128-
129- ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, buf[0].len);
130- if (i < nbufs - 1) {
131- entry->dma_addr[1] = buf[1].addr;
132- entry->dma_len[1] = buf[1].len;
133- buf1 = buf[1].addr;
134- ctrl |= FIELD_PREP(MT_DMA_CTL_SD_LEN1, buf[1].len);
135- if (buf[1].skip_unmap)
136- entry->skip_buf1 = true;
137+ type = FIELD_GET(MT_QFLAG_WED_TYPE, q->flags);
138+ if (mtk_wed_device_active(wed) && type == MT76_WED_Q_RX) {
139+ struct mt76_txwi_cache *r = rxwi;
140+ int rx_token;
141+
142+ if (!r)
143+ return -ENOMEM;
144+
145+ rx_token = mt76_rx_token_consume(dev, (void *)skb, r, buf[0].addr);
146+
147+ buf1 |= FIELD_PREP(MT_DMA_CTL_TOKEN, rx_token);
148+ ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, MTK_WED_RX_PKT_SIZE);
149+ ctrl |= MT_DMA_CTL_TO_HOST;
150+ } else {
151+ if (buf[0].skip_unmap)
152+ entry->skip_buf0 = true;
153+ entry->skip_buf1 = i == nbufs - 1;
154+
155+ entry->dma_addr[0] = buf[0].addr;
156+ entry->dma_len[0] = buf[0].len;
157+
158+ ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, buf[0].len);
159+ if (i < nbufs - 1) {
160+ entry->dma_addr[1] = buf[1].addr;
161+ entry->dma_len[1] = buf[1].len;
162+ buf1 = buf[1].addr;
163+ ctrl |= FIELD_PREP(MT_DMA_CTL_SD_LEN1, buf[1].len);
164+ if (buf[1].skip_unmap)
165+ entry->skip_buf1 = true;
166+ }
167+ if (i == nbufs - 1)
168+ ctrl |= MT_DMA_CTL_LAST_SEC0;
169+ else if (i == nbufs - 2)
170+ ctrl |= MT_DMA_CTL_LAST_SEC1;
171 }
172
173- if (i == nbufs - 1)
174- ctrl |= MT_DMA_CTL_LAST_SEC0;
175- else if (i == nbufs - 2)
176- ctrl |= MT_DMA_CTL_LAST_SEC1;
177-
178 WRITE_ONCE(desc->buf0, cpu_to_le32(buf0));
179 WRITE_ONCE(desc->buf1, cpu_to_le32(buf1));
180 WRITE_ONCE(desc->info, cpu_to_le32(info));
181@@ -272,33 +346,63 @@ mt76_dma_tx_cleanup(struct mt76_dev *dev, struct mt76_queue *q, bool flush)
182
183 static void *
184 mt76_dma_get_buf(struct mt76_dev *dev, struct mt76_queue *q, int idx,
185- int *len, u32 *info, bool *more)
186+ int *len, u32 *info, bool *more, bool *drop)
187 {
188 struct mt76_queue_entry *e = &q->entry[idx];
189 struct mt76_desc *desc = &q->desc[idx];
190 dma_addr_t buf_addr;
191 void *buf = e->buf;
192 int buf_len = SKB_WITH_OVERHEAD(q->buf_size);
193+ struct mtk_wed_device *wed = &dev->mmio.wed;
194+ int type;
195
196- buf_addr = e->dma_addr[0];
197 if (len) {
198 u32 ctl = le32_to_cpu(READ_ONCE(desc->ctrl));
199 *len = FIELD_GET(MT_DMA_CTL_SD_LEN0, ctl);
200 *more = !(ctl & MT_DMA_CTL_LAST_SEC0);
201 }
202
203- if (info)
204- *info = le32_to_cpu(desc->info);
205+ type = FIELD_GET(MT_QFLAG_WED_TYPE, q->flags);
206+ if (mtk_wed_device_active(wed) && type == MT76_WED_Q_RX) {
207+ u32 token;
208+ struct mt76_txwi_cache *r;
209+
210+ token = FIELD_GET(MT_DMA_CTL_TOKEN, desc->buf1);
211+
212+ r = mt76_rx_token_release(dev, token);
213+ if (!r)
214+ return NULL;
215+
216+ buf = page_frag_alloc(&q->rx_page, q->buf_size, GFP_ATOMIC);
217+ if (!buf)
218+ return NULL;
219+
220+ memcpy(buf, r->buf, MTK_WED_RX_PKT_SIZE);
221+ buf_addr = r->dma_addr;
222+ buf_len = MTK_WED_RX_PKT_SIZE;
223+ r->dma_addr = 0;
224+ //r->buf = NULL;
225+
226+ mt76_put_rxwi(dev, r);
227+
228+ if (desc->ctrl & (MT_DMA_CTL_TO_HOST_A | MT_DMA_CTL_DROP))
229+ *drop = true;
230+ } else {
231+ buf_addr = e->dma_addr[0];
232+ e->buf = NULL;
233+ }
234
235 dma_unmap_single(dev->dma_dev, buf_addr, buf_len, DMA_FROM_DEVICE);
236- e->buf = NULL;
237+
238+ if (info)
239+ *info = le32_to_cpu(desc->info);
240
241 return buf;
242 }
243
244 static void *
245 mt76_dma_dequeue(struct mt76_dev *dev, struct mt76_queue *q, bool flush,
246- int *len, u32 *info, bool *more)
247+ int *len, u32 *info, bool *more, bool *drop)
248 {
249 int idx = q->tail;
250
251@@ -314,7 +418,7 @@ mt76_dma_dequeue(struct mt76_dev *dev, struct mt76_queue *q, bool flush,
252 q->tail = (q->tail + 1) % q->ndesc;
253 q->queued--;
254
255- return mt76_dma_get_buf(dev, q, idx, len, info, more);
256+ return mt76_dma_get_buf(dev, q, idx, len, info, more, drop);
257 }
258
259 static int
260@@ -336,7 +440,7 @@ mt76_dma_tx_queue_skb_raw(struct mt76_dev *dev, struct mt76_queue *q,
261 buf.len = skb->len;
262
263 spin_lock_bh(&q->lock);
264- mt76_dma_add_buf(dev, q, &buf, 1, tx_info, skb, NULL);
265+ mt76_dma_add_buf(dev, q, &buf, 1, tx_info, skb, NULL, NULL);
266 mt76_dma_kick_queue(dev, q);
267 spin_unlock_bh(&q->lock);
268
269@@ -413,7 +517,7 @@ mt76_dma_tx_queue_skb(struct mt76_dev *dev, struct mt76_queue *q,
270 goto unmap;
271
272 return mt76_dma_add_buf(dev, q, tx_info.buf, tx_info.nbuf,
273- tx_info.info, tx_info.skb, t);
274+ tx_info.info, tx_info.skb, t, NULL);
275
276 unmap:
277 for (n--; n > 0; n--)
278@@ -448,6 +552,7 @@ mt76_dma_rx_fill(struct mt76_dev *dev, struct mt76_queue *q)
279 int frames = 0;
280 int len = SKB_WITH_OVERHEAD(q->buf_size);
281 int offset = q->buf_offset;
282+ struct mtk_wed_device *wed = &dev->mmio.wed;
283
284 if (!q->ndesc)
285 return 0;
286@@ -456,10 +561,27 @@ mt76_dma_rx_fill(struct mt76_dev *dev, struct mt76_queue *q)
287
288 while (q->queued < q->ndesc - 1) {
289 struct mt76_queue_buf qbuf;
290+ int type = FIELD_GET(MT_QFLAG_WED_TYPE, q->flags);
291+ bool skip_alloc = false;
292+ struct mt76_txwi_cache *r = NULL;
293+
294+ if (mtk_wed_device_active(wed) && type == MT76_WED_Q_RX) {
295+ r = mt76_get_rxwi(dev);
296+ if (!r)
297+ return -ENOMEM;
298+
299+ if (r->buf) {
300+ skip_alloc = true;
301+ len = MTK_WED_RX_PKT_SIZE;
302+ buf = r->buf;
303+ }
304+ }
305
306- buf = page_frag_alloc(&q->rx_page, q->buf_size, GFP_ATOMIC);
307- if (!buf)
308- break;
309+ if (!skip_alloc) {
310+ buf = page_frag_alloc(&q->rx_page, q->buf_size, GFP_ATOMIC);
311+ if (!buf)
312+ break;
313+ }
314
315 addr = dma_map_single(dev->dma_dev, buf, len, DMA_FROM_DEVICE);
316 if (unlikely(dma_mapping_error(dev->dma_dev, addr))) {
317@@ -470,7 +592,7 @@ mt76_dma_rx_fill(struct mt76_dev *dev, struct mt76_queue *q)
318 qbuf.addr = addr + offset;
319 qbuf.len = len - offset;
320 qbuf.skip_unmap = false;
321- mt76_dma_add_buf(dev, q, &qbuf, 1, 0, buf, NULL);
322+ mt76_dma_add_buf(dev, q, &qbuf, 1, 0, buf, NULL, r);
323 frames++;
324 }
325
326@@ -516,6 +638,11 @@ mt76_dma_wed_setup(struct mt76_dev *dev, struct mt76_queue *q)
327 if (!ret)
328 q->wed_regs = wed->txfree_ring.reg_base;
329 break;
330+ case MT76_WED_Q_RX:
331+ ret = mtk_wed_device_rx_ring_setup(wed, ring, q->regs);
332+ if (!ret)
333+ q->wed_regs = wed->rx_ring[ring].reg_base;
334+ break;
335 default:
336 ret = -EINVAL;
337 }
338@@ -531,7 +658,8 @@ mt76_dma_alloc_queue(struct mt76_dev *dev, struct mt76_queue *q,
339 int idx, int n_desc, int bufsize,
340 u32 ring_base)
341 {
342- int ret, size;
343+ int ret, size, type;
344+ struct mtk_wed_device *wed = &dev->mmio.wed;
345
346 spin_lock_init(&q->lock);
347 spin_lock_init(&q->cleanup_lock);
348@@ -541,6 +669,11 @@ mt76_dma_alloc_queue(struct mt76_dev *dev, struct mt76_queue *q,
349 q->buf_size = bufsize;
350 q->hw_idx = idx;
351
352+ type = FIELD_GET(MT_QFLAG_WED_TYPE, q->flags);
353+ if (mtk_wed_device_active(wed) && type == MT76_WED_Q_RX)
354+ q->buf_size = SKB_DATA_ALIGN(NET_SKB_PAD + MTK_WED_RX_PKT_SIZE) +
355+ SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
356+
357 size = q->ndesc * sizeof(struct mt76_desc);
358 q->desc = dmam_alloc_coherent(dev->dma_dev, size, &q->desc_dma, GFP_KERNEL);
359 if (!q->desc)
360@@ -573,7 +706,7 @@ mt76_dma_rx_cleanup(struct mt76_dev *dev, struct mt76_queue *q)
361
362 spin_lock_bh(&q->lock);
363 do {
364- buf = mt76_dma_dequeue(dev, q, true, NULL, NULL, &more);
365+ buf = mt76_dma_dequeue(dev, q, true, NULL, NULL, &more, NULL);
366 if (!buf)
367 break;
368
369@@ -614,7 +747,7 @@ mt76_dma_rx_reset(struct mt76_dev *dev, enum mt76_rxq_id qid)
370
371 static void
372 mt76_add_fragment(struct mt76_dev *dev, struct mt76_queue *q, void *data,
373- int len, bool more)
374+ int len, bool more, u32 info)
375 {
376 struct sk_buff *skb = q->rx_head;
377 struct skb_shared_info *shinfo = skb_shinfo(skb);
378@@ -634,7 +767,7 @@ mt76_add_fragment(struct mt76_dev *dev, struct mt76_queue *q, void *data,
379
380 q->rx_head = NULL;
381 if (nr_frags < ARRAY_SIZE(shinfo->frags))
382- dev->drv->rx_skb(dev, q - dev->q_rx, skb);
383+ dev->drv->rx_skb(dev, q - dev->q_rx, skb, info);
384 else
385 dev_kfree_skb(skb);
386 }
387@@ -655,6 +788,7 @@ mt76_dma_rx_process(struct mt76_dev *dev, struct mt76_queue *q, int budget)
388 }
389
390 while (done < budget) {
391+ bool drop = false;
392 u32 info;
393
394 if (check_ddone) {
395@@ -665,10 +799,13 @@ mt76_dma_rx_process(struct mt76_dev *dev, struct mt76_queue *q, int budget)
396 break;
397 }
398
399- data = mt76_dma_dequeue(dev, q, false, &len, &info, &more);
400+ data = mt76_dma_dequeue(dev, q, false, &len, &info, &more, &drop);
401 if (!data)
402 break;
403
404+ if (drop)
405+ goto free_frag;
406+
407 if (q->rx_head)
408 data_len = q->buf_size;
409 else
410@@ -681,7 +818,7 @@ mt76_dma_rx_process(struct mt76_dev *dev, struct mt76_queue *q, int budget)
411 }
412
413 if (q->rx_head) {
414- mt76_add_fragment(dev, q, data, len, more);
415+ mt76_add_fragment(dev, q, data, len, more, info);
416 continue;
417 }
418
419@@ -708,7 +845,7 @@ mt76_dma_rx_process(struct mt76_dev *dev, struct mt76_queue *q, int budget)
420 continue;
421 }
422
423- dev->drv->rx_skb(dev, q - dev->q_rx, skb);
424+ dev->drv->rx_skb(dev, q - dev->q_rx, skb, info);
425 continue;
426
427 free_frag:
428diff --git a/dma.h b/dma.h
developerf50c1802022-07-05 20:35:53 +0800429index fdf786f..90370d1 100644
developer8cb3ac72022-07-04 10:55:14 +0800430--- a/dma.h
431+++ b/dma.h
432@@ -16,6 +16,16 @@
433 #define MT_DMA_CTL_LAST_SEC0 BIT(30)
434 #define MT_DMA_CTL_DMA_DONE BIT(31)
435
436+#define MT_DMA_CTL_TO_HOST BIT(8)
437+#define MT_DMA_CTL_TO_HOST_A BIT(12)
438+#define MT_DMA_CTL_DROP BIT(14)
439+
440+#define MT_DMA_CTL_TOKEN GENMASK(31, 16)
441+
442+#define MT_DMA_PPE_CPU_REASON GENMASK(15, 11)
443+#define MT_DMA_PPE_ENTRY GENMASK(30, 16)
444+#define MT_DMA_INFO_PPE_VLD BIT(31)
445+
446 #define MT_DMA_HDR_LEN 4
447 #define MT_RX_INFO_LEN 4
448 #define MT_FCE_INFO_LEN 4
449diff --git a/mac80211.c b/mac80211.c
developerf50c1802022-07-05 20:35:53 +0800450index af2c09a..fa5ce6e 100644
developer8cb3ac72022-07-04 10:55:14 +0800451--- a/mac80211.c
452+++ b/mac80211.c
453@@ -594,11 +594,14 @@ mt76_alloc_device(struct device *pdev, unsigned int size,
454 BIT(NL80211_IFTYPE_ADHOC);
455
456 spin_lock_init(&dev->token_lock);
457+ spin_lock_init(&dev->rx_token_lock);
458 idr_init(&dev->token);
459+ idr_init(&dev->rx_token);
460
461 INIT_LIST_HEAD(&dev->wcid_list);
462
463 INIT_LIST_HEAD(&dev->txwi_cache);
464+ INIT_LIST_HEAD(&dev->rxwi_cache);
465 dev->token_size = dev->drv->token_size;
466
467 for (i = 0; i < ARRAY_SIZE(dev->q_rx); i++)
468@@ -1296,7 +1299,10 @@ void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q,
469
470 while ((skb = __skb_dequeue(&dev->rx_skb[q])) != NULL) {
471 mt76_check_sta(dev, skb);
472- mt76_rx_aggr_reorder(skb, &frames);
473+ if (mtk_wed_device_active(&dev->mmio.wed))
474+ __skb_queue_tail(&frames, skb);
475+ else
476+ mt76_rx_aggr_reorder(skb, &frames);
477 }
478
479 mt76_rx_complete(dev, &frames, napi);
480diff --git a/mt76.h b/mt76.h
developerf50c1802022-07-05 20:35:53 +0800481index 4c8a671..24e4741 100644
developer8cb3ac72022-07-04 10:55:14 +0800482--- a/mt76.h
483+++ b/mt76.h
484@@ -20,6 +20,8 @@
485
486 #define MT_MCU_RING_SIZE 32
487 #define MT_RX_BUF_SIZE 2048
488+#define MTK_WED_RX_PKT_SIZE 1700
489+
490 #define MT_SKB_HEAD_LEN 256
491
492 #define MT_MAX_NON_AQL_PKT 16
493@@ -35,6 +37,7 @@
494 FIELD_PREP(MT_QFLAG_WED_TYPE, _type) | \
495 FIELD_PREP(MT_QFLAG_WED_RING, _n))
496 #define MT_WED_Q_TX(_n) __MT_WED_Q(MT76_WED_Q_TX, _n)
497+#define MT_WED_Q_RX(_n) __MT_WED_Q(MT76_WED_Q_RX, _n)
498 #define MT_WED_Q_TXFREE __MT_WED_Q(MT76_WED_Q_TXFREE, 0)
499
500 struct mt76_dev;
501@@ -56,6 +59,7 @@ enum mt76_bus_type {
502 enum mt76_wed_type {
503 MT76_WED_Q_TX,
504 MT76_WED_Q_TXFREE,
505+ MT76_WED_Q_RX,
506 };
507
508 struct mt76_bus_ops {
509@@ -305,7 +309,10 @@ struct mt76_txwi_cache {
510 struct list_head list;
511 dma_addr_t dma_addr;
512
513- struct sk_buff *skb;
514+ union {
515+ void *buf;
516+ struct sk_buff *skb;
517+ };
518 };
519
520 struct mt76_rx_tid {
521@@ -403,7 +410,7 @@ struct mt76_driver_ops {
522 bool (*rx_check)(struct mt76_dev *dev, void *data, int len);
523
524 void (*rx_skb)(struct mt76_dev *dev, enum mt76_rxq_id q,
525- struct sk_buff *skb);
526+ struct sk_buff *skb, u32 info);
527
528 void (*rx_poll_complete)(struct mt76_dev *dev, enum mt76_rxq_id q);
529
530@@ -747,6 +754,7 @@ struct mt76_dev {
531 struct ieee80211_hw *hw;
532
533 spinlock_t lock;
534+ spinlock_t wed_lock;
535 spinlock_t cc_lock;
536
537 u32 cur_cc_bss_rx;
538@@ -772,6 +780,7 @@ struct mt76_dev {
539 struct sk_buff_head rx_skb[__MT_RXQ_MAX];
540
541 struct list_head txwi_cache;
542+ struct list_head rxwi_cache;
543 struct mt76_queue *q_mcu[__MT_MCUQ_MAX];
544 struct mt76_queue q_rx[__MT_RXQ_MAX];
545 const struct mt76_queue_ops *queue_ops;
546@@ -785,6 +794,9 @@ struct mt76_dev {
547 u16 wed_token_count;
548 u16 token_count;
549 u16 token_size;
550+ u16 rx_token_size;
551+ spinlock_t rx_token_lock;
552+ struct idr rx_token;
553
554 wait_queue_head_t tx_wait;
555 /* spinclock used to protect wcid pktid linked list */
556@@ -1351,6 +1363,8 @@ mt76_tx_status_get_hw(struct mt76_dev *dev, struct sk_buff *skb)
557 }
558
559 void mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t);
560+void mt76_put_rxwi(struct mt76_dev *dev, struct mt76_txwi_cache *t);
561+struct mt76_txwi_cache *mt76_get_rxwi(struct mt76_dev *dev);
562 void mt76_rx_complete(struct mt76_dev *dev, struct sk_buff_head *frames,
563 struct napi_struct *napi);
564 void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q,
565@@ -1495,6 +1509,12 @@ struct mt76_txwi_cache *
566 mt76_token_release(struct mt76_dev *dev, int token, bool *wake);
567 int mt76_token_consume(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi);
568 void __mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked);
569+int mt76_rx_token_consume(struct mt76_dev *dev, void *ptr,
570+ struct mt76_txwi_cache *r, dma_addr_t phys);
571+void skb_trace(const struct sk_buff *skb, bool full_pkt);
572+
573+struct mt76_txwi_cache *
574+mt76_rx_token_release(struct mt76_dev *dev, int token);
575
576 static inline void mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked)
577 {
578diff --git a/mt7603/dma.c b/mt7603/dma.c
developerf50c1802022-07-05 20:35:53 +0800579index 590cff9..2ff71c5 100644
developer8cb3ac72022-07-04 10:55:14 +0800580--- a/mt7603/dma.c
581+++ b/mt7603/dma.c
582@@ -69,7 +69,7 @@ free:
583 }
584
585 void mt7603_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
586- struct sk_buff *skb)
587+ struct sk_buff *skb, u32 info)
588 {
589 struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76);
590 __le32 *rxd = (__le32 *)skb->data;
591diff --git a/mt7603/mt7603.h b/mt7603/mt7603.h
developerf50c1802022-07-05 20:35:53 +0800592index 0fd46d9..f2ce22a 100644
developer8cb3ac72022-07-04 10:55:14 +0800593--- a/mt7603/mt7603.h
594+++ b/mt7603/mt7603.h
595@@ -244,7 +244,7 @@ int mt7603_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
596 void mt7603_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue_entry *e);
597
598 void mt7603_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
599- struct sk_buff *skb);
600+ struct sk_buff *skb, u32 info);
601 void mt7603_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q);
602 void mt7603_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps);
603 int mt7603_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif,
604diff --git a/mt7615/mac.c b/mt7615/mac.c
developerf50c1802022-07-05 20:35:53 +0800605index 3728627..14cdd9a 100644
developer8cb3ac72022-07-04 10:55:14 +0800606--- a/mt7615/mac.c
607+++ b/mt7615/mac.c
developerf50c1802022-07-05 20:35:53 +0800608@@ -1648,7 +1648,7 @@ bool mt7615_rx_check(struct mt76_dev *mdev, void *data, int len)
developer8cb3ac72022-07-04 10:55:14 +0800609 EXPORT_SYMBOL_GPL(mt7615_rx_check);
610
611 void mt7615_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
612- struct sk_buff *skb)
613+ struct sk_buff *skb, u32 info)
614 {
615 struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
616 __le32 *rxd = (__le32 *)skb->data;
617diff --git a/mt7615/mt7615.h b/mt7615/mt7615.h
developerf50c1802022-07-05 20:35:53 +0800618index 25880d1..983469c 100644
developer8cb3ac72022-07-04 10:55:14 +0800619--- a/mt7615/mt7615.h
620+++ b/mt7615/mt7615.h
developerf50c1802022-07-05 20:35:53 +0800621@@ -511,7 +511,7 @@ void mt7615_tx_worker(struct mt76_worker *w);
developer8cb3ac72022-07-04 10:55:14 +0800622 void mt7615_tx_token_put(struct mt7615_dev *dev);
623 bool mt7615_rx_check(struct mt76_dev *mdev, void *data, int len);
624 void mt7615_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
625- struct sk_buff *skb);
626+ struct sk_buff *skb, u32 info);
627 void mt7615_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps);
628 int mt7615_mac_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif,
629 struct ieee80211_sta *sta);
630diff --git a/mt76_connac_mcu.c b/mt76_connac_mcu.c
developerf50c1802022-07-05 20:35:53 +0800631index cd35068..f90a08f 100644
developer8cb3ac72022-07-04 10:55:14 +0800632--- a/mt76_connac_mcu.c
633+++ b/mt76_connac_mcu.c
634@@ -1190,6 +1190,7 @@ int mt76_connac_mcu_sta_ba(struct mt76_dev *dev, struct mt76_vif *mvif,
635 int cmd, bool enable, bool tx)
636 {
637 struct mt76_wcid *wcid = (struct mt76_wcid *)params->sta->drv_priv;
638+ struct mtk_wed_device *wed = &dev->mmio.wed;
639 struct wtbl_req_hdr *wtbl_hdr;
640 struct tlv *sta_wtbl;
641 struct sk_buff *skb;
developerf50c1802022-07-05 20:35:53 +0800642@@ -1210,6 +1211,8 @@ int mt76_connac_mcu_sta_ba(struct mt76_dev *dev, struct mt76_vif *mvif,
developer8cb3ac72022-07-04 10:55:14 +0800643 mt76_connac_mcu_wtbl_ba_tlv(dev, skb, params, enable, tx, sta_wtbl,
644 wtbl_hdr);
645
developerf50c1802022-07-05 20:35:53 +0800646+ if (mtk_wed_device_active(wed) && wed->ver > MTK_WED_V1)
developer6adfa0e2022-07-06 16:25:53 +0800647+ mtk_wed_device_update_msg(wed, WED_WO_STA_REC, skb->data, skb->len);
developer8cb3ac72022-07-04 10:55:14 +0800648 ret = mt76_mcu_skb_send_msg(dev, skb, cmd, true);
649 if (ret)
650 return ret;
developerf50c1802022-07-05 20:35:53 +0800651@@ -1220,6 +1223,8 @@ int mt76_connac_mcu_sta_ba(struct mt76_dev *dev, struct mt76_vif *mvif,
developer8cb3ac72022-07-04 10:55:14 +0800652
653 mt76_connac_mcu_sta_ba_tlv(skb, params, enable, tx);
654
developerf50c1802022-07-05 20:35:53 +0800655+ if (mtk_wed_device_active(wed) && wed->ver > MTK_WED_V1)
656+ mtk_wed_device_update_msg(wed, WED_WO_STA_REC, skb->data, skb->len);
developer8cb3ac72022-07-04 10:55:14 +0800657 return mt76_mcu_skb_send_msg(dev, skb, cmd, true);
658 }
659 EXPORT_SYMBOL_GPL(mt76_connac_mcu_sta_ba);
developerf50c1802022-07-05 20:35:53 +0800660@@ -2634,6 +2639,7 @@ int mt76_connac_mcu_add_key(struct mt76_dev *dev, struct ieee80211_vif *vif,
developer8cb3ac72022-07-04 10:55:14 +0800661 struct mt76_wcid *wcid, enum set_key_cmd cmd)
662 {
663 struct mt76_vif *mvif = (struct mt76_vif *)vif->drv_priv;
664+ struct mtk_wed_device *wed = &dev->mmio.wed;
665 struct sk_buff *skb;
666 int ret;
667
developerf50c1802022-07-05 20:35:53 +0800668@@ -2645,6 +2651,9 @@ int mt76_connac_mcu_add_key(struct mt76_dev *dev, struct ieee80211_vif *vif,
developer8cb3ac72022-07-04 10:55:14 +0800669 if (ret)
670 return ret;
671
developerf50c1802022-07-05 20:35:53 +0800672+ if (mtk_wed_device_active(wed) && wed->ver > MTK_WED_V1)
developer8cb3ac72022-07-04 10:55:14 +0800673+ mtk_wed_device_update_msg(wed, WED_WO_STA_REC, skb->data, skb->len);
674+
675 return mt76_mcu_skb_send_msg(dev, skb, mcu_cmd, true);
676 }
677 EXPORT_SYMBOL_GPL(mt76_connac_mcu_add_key);
678diff --git a/mt76x02.h b/mt76x02.h
developerf50c1802022-07-05 20:35:53 +0800679index f76fd22..0b872af 100644
developer8cb3ac72022-07-04 10:55:14 +0800680--- a/mt76x02.h
681+++ b/mt76x02.h
682@@ -173,7 +173,7 @@ int mt76x02_set_rts_threshold(struct ieee80211_hw *hw, u32 val);
683 void mt76x02_remove_hdr_pad(struct sk_buff *skb, int len);
684 bool mt76x02_tx_status_data(struct mt76_dev *mdev, u8 *update);
685 void mt76x02_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
686- struct sk_buff *skb);
687+ struct sk_buff *skb, u32 info);
688 void mt76x02_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q);
689 irqreturn_t mt76x02_irq_handler(int irq, void *dev_instance);
690 void mt76x02_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control,
691diff --git a/mt76x02_txrx.c b/mt76x02_txrx.c
developerf50c1802022-07-05 20:35:53 +0800692index 96fdf42..bf24d3e 100644
developer8cb3ac72022-07-04 10:55:14 +0800693--- a/mt76x02_txrx.c
694+++ b/mt76x02_txrx.c
695@@ -33,7 +33,7 @@ void mt76x02_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control,
696 EXPORT_SYMBOL_GPL(mt76x02_tx);
697
698 void mt76x02_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
699- struct sk_buff *skb)
700+ struct sk_buff *skb, u32 info)
701 {
702 struct mt76x02_dev *dev = container_of(mdev, struct mt76x02_dev, mt76);
703 void *rxwi = skb->data;
704diff --git a/mt7915/dma.c b/mt7915/dma.c
developerf50c1802022-07-05 20:35:53 +0800705index 7122322..ac98e01 100644
developer8cb3ac72022-07-04 10:55:14 +0800706--- a/mt7915/dma.c
707+++ b/mt7915/dma.c
708@@ -376,6 +376,8 @@ int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2)
709 FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_TX0, 18) |
710 FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_TX1, 19) |
711 FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_RX1, 1));
712+ mt76_rmw(dev, MT_WFDMA0_EXT0_CFG, MT_WFDMA0_EXT0_RXWB_KEEP,
713+ MT_WFDMA0_EXT0_RXWB_KEEP);
714 } else {
715 mt76_wr(dev, MT_WFDMA_WED_RING_CONTROL,
716 FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_TX0, 18) |
developerf50c1802022-07-05 20:35:53 +0800717@@ -451,6 +453,10 @@ int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2)
developer8cb3ac72022-07-04 10:55:14 +0800718
719 /* rx data queue for band0 */
720 if (!dev->phy.band_idx) {
developerf50c1802022-07-05 20:35:53 +0800721+ if (mtk_wed_device_active(&dev->mt76.mmio.wed) &&
722+ dev->mt76.mmio.wed.ver > MTK_WED_V1)
developer8cb3ac72022-07-04 10:55:14 +0800723+ dev->mt76.q_rx[MT_RXQ_MAIN].flags = MT_WED_Q_RX(MT7915_RXQ_BAND0);
724+
725 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN],
726 MT_RXQ_ID(MT_RXQ_MAIN),
727 MT7915_RX_RING_SIZE,
developerf50c1802022-07-05 20:35:53 +0800728@@ -482,6 +488,10 @@ int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2)
developer8cb3ac72022-07-04 10:55:14 +0800729
730 if (dev->dbdc_support || dev->phy.band_idx) {
731 /* rx data queue for band1 */
developerf50c1802022-07-05 20:35:53 +0800732+ if (mtk_wed_device_active(&dev->mt76.mmio.wed) &&
733+ dev->mt76.mmio.wed.ver > MTK_WED_V1)
developer8cb3ac72022-07-04 10:55:14 +0800734+ dev->mt76.q_rx[MT_RXQ_EXT].flags = MT_WED_Q_RX(MT7915_RXQ_BAND1);
735+
736 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_EXT],
737 MT_RXQ_ID(MT_RXQ_EXT),
738 MT7915_RX_RING_SIZE,
739diff --git a/mt7915/mac.c b/mt7915/mac.c
developerf50c1802022-07-05 20:35:53 +0800740old mode 100755
741new mode 100644
742index bc8da4d..79b7d01
developer8cb3ac72022-07-04 10:55:14 +0800743--- a/mt7915/mac.c
744+++ b/mt7915/mac.c
745@@ -217,7 +217,7 @@ static void mt7915_mac_sta_poll(struct mt7915_dev *dev)
746 }
747
748 static int
749-mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
750+mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb, enum mt76_rxq_id q, u32 info)
751 {
752 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
753 struct mt76_phy *mphy = &dev->mt76.phy;
754@@ -494,6 +494,27 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
755 #endif
756 } else {
757 status->flag |= RX_FLAG_8023;
758+ if (msta || msta->vif) {
759+ struct mtk_wed_device *wed;
760+ int type;
761+
762+ wed = &dev->mt76.mmio.wed;
763+ type = FIELD_GET(MT_QFLAG_WED_TYPE, dev->mt76.q_rx[q].flags);
764+ if ((mtk_wed_device_active(wed) && type == MT76_WED_Q_RX) &&
765+ (info & MT_DMA_INFO_PPE_VLD)){
766+ struct ieee80211_vif *vif;
767+ u32 hash, reason;
768+
769+ vif = container_of((void *)msta->vif, struct ieee80211_vif,
770+ drv_priv);
771+
772+ skb->dev = ieee80211_vif_to_netdev(vif);
773+ reason = FIELD_GET(MT_DMA_PPE_CPU_REASON, info);
774+ hash = FIELD_GET(MT_DMA_PPE_ENTRY, info);
775+
776+ mtk_wed_device_ppe_check(wed, skb, reason, hash);
777+ }
778+ }
779 }
780
781 if (rxv && mode >= MT_PHY_TYPE_HE_SU && !(status->flag & RX_FLAG_8023))
developerf50c1802022-07-05 20:35:53 +0800782@@ -840,6 +861,68 @@ u32 mt7915_wed_init_buf(void *ptr, dma_addr_t phys, int token_id)
developer8cb3ac72022-07-04 10:55:14 +0800783 return MT_TXD_TXP_BUF_SIZE;
784 }
785
786+u32
787+mt7915_wed_init_rx_buf(struct mtk_wed_device *wed, int pkt_num)
788+{
789+ struct mtk_rxbm_desc *desc = wed->rx_buf_ring.desc;
790+ struct mt7915_dev *dev;
791+ dma_addr_t buf_phys;
792+ void *buf;
793+ int i, token, buf_size;
794+
795+ buf_size = SKB_DATA_ALIGN(NET_SKB_PAD + wed->wlan.rx_pkt_size) +
796+ SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
797+
798+ dev = container_of(wed, struct mt7915_dev, mt76.mmio.wed);
799+ for (i = 0; i < pkt_num; i++) {
800+ struct mt76_txwi_cache *r = mt76_get_rxwi(&dev->mt76);
801+
802+ buf = page_frag_alloc(&wed->rx_page, buf_size, GFP_ATOMIC);
803+ if (!buf)
804+ return -ENOMEM;
805+
806+ buf_phys = dma_map_single(dev->mt76.dma_dev, buf, wed->wlan.rx_pkt_size,
807+ DMA_TO_DEVICE);
808+
809+ if (unlikely(dma_mapping_error(dev->mt76.dev, buf_phys))) {
810+ skb_free_frag(buf);
811+ break;
812+ }
813+
814+ desc->buf0 = buf_phys;
815+
816+ token = mt76_rx_token_consume(&dev->mt76, buf, r, buf_phys);
817+
818+ desc->token |= FIELD_PREP(MT_DMA_CTL_TOKEN, token);
819+ desc++;
820+ }
821+
822+ return 0;
823+}
824+
825+void mt7915_wed_release_rx_buf(struct mtk_wed_device *wed)
826+{
827+ struct mt76_txwi_cache *rxwi;
828+ struct mt7915_dev *dev;
829+ int token;
830+
831+ dev = container_of(wed, struct mt7915_dev, mt76.mmio.wed);
832+
833+ for(token = 0; token < dev->mt76.rx_token_size; token++) {
834+ rxwi = mt76_rx_token_release(&dev->mt76, token);
835+ if(!rxwi)
836+ continue;
837+
838+ dma_unmap_single(dev->mt76.dma_dev, rxwi->dma_addr,
839+ wed->wlan.rx_pkt_size, DMA_FROM_DEVICE);
840+ skb_free_frag(rxwi->buf);
841+ rxwi->buf = NULL;
842+
843+ mt76_put_rxwi(&dev->mt76, rxwi);
844+ }
845+ return;
846+}
847+
848 static void
849 mt7915_tx_check_aggr(struct ieee80211_sta *sta, __le32 *txwi)
850 {
developerf50c1802022-07-05 20:35:53 +0800851@@ -1120,7 +1203,7 @@ bool mt7915_rx_check(struct mt76_dev *mdev, void *data, int len)
developer8cb3ac72022-07-04 10:55:14 +0800852 }
853
854 void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
855- struct sk_buff *skb)
856+ struct sk_buff *skb, u32 info)
857 {
858 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
859 __le32 *rxd = (__le32 *)skb->data;
developerf50c1802022-07-05 20:35:53 +0800860@@ -1154,7 +1237,7 @@ void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
developer8cb3ac72022-07-04 10:55:14 +0800861 dev_kfree_skb(skb);
862 break;
863 case PKT_TYPE_NORMAL:
864- if (!mt7915_mac_fill_rx(dev, skb)) {
865+ if (!mt7915_mac_fill_rx(dev, skb, q, info)) {
866 mt76_rx(&dev->mt76, q, skb);
867 return;
868 }
869diff --git a/mt7915/mcu.c b/mt7915/mcu.c
developerf50c1802022-07-05 20:35:53 +0800870index 1468c3c..4f64df4 100644
developer8cb3ac72022-07-04 10:55:14 +0800871--- a/mt7915/mcu.c
872+++ b/mt7915/mcu.c
873@@ -1704,6 +1704,7 @@ int mt7915_mcu_add_sta(struct mt7915_dev *dev, struct ieee80211_vif *vif,
874 struct ieee80211_sta *sta, bool enable)
875 {
876 struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv;
877+ struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
878 struct mt7915_sta *msta;
879 struct sk_buff *skb;
880 int ret;
developerf50c1802022-07-05 20:35:53 +0800881@@ -1756,6 +1757,8 @@ int mt7915_mcu_add_sta(struct mt7915_dev *dev, struct ieee80211_vif *vif,
developer8cb3ac72022-07-04 10:55:14 +0800882 return ret;
883 }
884 out:
developerf50c1802022-07-05 20:35:53 +0800885+ if (mtk_wed_device_active(wed) && wed->ver > MTK_WED_V1)
886+ mtk_wed_device_update_msg(wed, WED_WO_STA_REC, skb->data, skb->len);
developer8cb3ac72022-07-04 10:55:14 +0800887 return mt76_mcu_skb_send_msg(&dev->mt76, skb,
888 MCU_EXT_CMD(STA_REC_UPDATE), true);
889 }
890diff --git a/mt7915/mmio.c b/mt7915/mmio.c
developerf50c1802022-07-05 20:35:53 +0800891old mode 100755
892new mode 100644
893index b4a3120..08ff556
developer8cb3ac72022-07-04 10:55:14 +0800894--- a/mt7915/mmio.c
895+++ b/mt7915/mmio.c
896@@ -28,6 +28,9 @@ static const u32 mt7915_reg[] = {
897 [FW_EXCEPTION_ADDR] = 0x219848,
898 [SWDEF_BASE_ADDR] = 0x41f200,
899 [EXCEPTION_BASE_ADDR] = 0x219848,
900+ [WED_TX_RING] = 0xd7300,
901+ [WED_RX_RING] = 0xd7410,
902+ [WED_RX_DATA_RING] = 0xd4500,
903 };
904
905 static const u32 mt7916_reg[] = {
906@@ -45,6 +48,9 @@ static const u32 mt7916_reg[] = {
907 [FW_EXCEPTION_ADDR] = 0x022050bc,
908 [SWDEF_BASE_ADDR] = 0x411400,
909 [EXCEPTION_BASE_ADDR] = 0x022050BC,
910+ [WED_TX_RING] = 0xd7300,
911+ [WED_RX_RING] = 0xd7410,
912+ [WED_RX_DATA_RING] = 0xd4540,
913 };
914
915 static const u32 mt7986_reg[] = {
916@@ -62,6 +68,9 @@ static const u32 mt7986_reg[] = {
917 [FW_EXCEPTION_ADDR] = 0x02204ffc,
918 [SWDEF_BASE_ADDR] = 0x411400,
919 [EXCEPTION_BASE_ADDR] = 0x02204FFC,
920+ [WED_TX_RING] = 0x24420,
921+ [WED_RX_RING] = 0x24520,
922+ [WED_RX_DATA_RING] = 0x24540,
923 };
924
925 static const u32 mt7915_offs[] = {
developerf50c1802022-07-05 20:35:53 +0800926@@ -710,6 +719,7 @@ mt7915_pci_wed_init(struct mt7915_dev *dev, struct device *pdev, int *irq)
927 wed->wlan.bus_type = MTK_BUS_TYPE_PCIE;
928 wed->wlan.wpdma_int = base + MT_INT_WED_SOURCE_CSR;
929 wed->wlan.wpdma_mask = base + MT_INT_WED_MASK_CSR;
930+ wed->wlan.wpdma_phys = base + MT_WFDMA_EXT_CSR_BASE;
931 } else {
932 struct platform_device *plat_dev;
933 struct resource *res;
934@@ -722,12 +732,19 @@ mt7915_pci_wed_init(struct mt7915_dev *dev, struct device *pdev, int *irq)
developer8cb3ac72022-07-04 10:55:14 +0800935 wed->wlan.wpdma_int = base + MT_INT_SOURCE_CSR;
936 wed->wlan.wpdma_mask = base + MT_INT_MASK_CSR;
937 }
938+ wed->wlan.rx_pkt = MT7915_WED_RX_TOKEN_SIZE;
939+ wed->wlan.phy_base = base;
940 wed->wlan.wpdma_tx = base + MT_TXQ_WED_RING_BASE;
941 wed->wlan.wpdma_txfree = base + MT_RXQ_WED_RING_BASE;
942+ wed->wlan.wpdma_rx_glo = base + MT_WPDMA_GLO_CFG;
943+ wed->wlan.wpdma_rx = base + MT_RXQ_WED_DATA_RING_BASE;
944
945 wed->wlan.tx_tbit[0] = MT_WED_TX_DONE_BAND0;
946 wed->wlan.tx_tbit[1] = MT_WED_TX_DONE_BAND1;
947 wed->wlan.txfree_tbit = MT_WED_TX_FREE_DONE;
948+ wed->wlan.rx_tbit[0] = MT_WED_RX_DONE_BAND0;
949+ wed->wlan.rx_tbit[1] = MT_WED_RX_DONE_BAND1;
950+
951 wed->wlan.nbuf = 7168;
952 wed->wlan.token_start = MT7915_TOKEN_SIZE - wed->wlan.nbuf;
953 wed->wlan.init_buf = mt7915_wed_init_buf;
developerf50c1802022-07-05 20:35:53 +0800954@@ -735,12 +752,15 @@ mt7915_pci_wed_init(struct mt7915_dev *dev, struct device *pdev, int *irq)
developer8cb3ac72022-07-04 10:55:14 +0800955 wed->wlan.offload_enable = mt7915_wed_offload_enable;
956 wed->wlan.offload_disable = mt7915_wed_offload_disable;
957
958+ wed->wlan.rx_nbuf = 65536;
959+ wed->wlan.rx_pkt_size = MTK_WED_RX_PKT_SIZE;
960+ wed->wlan.init_rx_buf = mt7915_wed_init_rx_buf;
961+ wed->wlan.release_rx_buf = mt7915_wed_release_rx_buf;
962+
963+ dev->mt76.rx_token_size = wed->wlan.rx_pkt + MT7915_RX_RING_SIZE * 2;
964 if (mtk_wed_device_attach(wed) != 0)
965 return 0;
966
developerf50c1802022-07-05 20:35:53 +0800967- if (wed->ver == MTK_WED_V1)
968- wed->wlan.wpdma_phys = base + MT_WFDMA_EXT_CSR_BASE;
969-
970 *irq = wed->irq;
971 dev->mt76.dma_dev = wed->dev;
972 mdev->token_size = wed->wlan.token_start;
developer8cb3ac72022-07-04 10:55:14 +0800973diff --git a/mt7915/mt7915.h b/mt7915/mt7915.h
developerf50c1802022-07-05 20:35:53 +0800974index fe407c5..e2f0d41 100644
developer8cb3ac72022-07-04 10:55:14 +0800975--- a/mt7915/mt7915.h
976+++ b/mt7915/mt7915.h
developerf50c1802022-07-05 20:35:53 +0800977@@ -69,6 +69,7 @@
developer8cb3ac72022-07-04 10:55:14 +0800978 #define MT7915_MAX_STA_TWT_AGRT 8
979 #define MT7915_MIN_TWT_DUR 64
980 #define MT7915_MAX_QUEUE (__MT_RXQ_MAX + __MT_MCUQ_MAX + 2)
981+#define MT7915_WED_RX_TOKEN_SIZE 12288
982
983 struct mt7915_vif;
984 struct mt7915_sta;
developerf50c1802022-07-05 20:35:53 +0800985@@ -531,7 +532,9 @@ void mt7915_wfsys_reset(struct mt7915_dev *dev);
developer8cb3ac72022-07-04 10:55:14 +0800986 irqreturn_t mt7915_irq_handler(int irq, void *dev_instance);
987 u64 __mt7915_get_tsf(struct ieee80211_hw *hw, struct mt7915_vif *mvif);
988 u32 mt7915_wed_init_buf(void *ptr, dma_addr_t phys, int token_id);
989-
990+u32 mt7915_wed_init_rx_buf(struct mtk_wed_device *wed,
991+ int pkt_num);
992+void mt7915_wed_release_rx_buf(struct mtk_wed_device *wed);
993 int mt7915_register_device(struct mt7915_dev *dev);
994 void mt7915_unregister_device(struct mt7915_dev *dev);
995 int mt7915_eeprom_init(struct mt7915_dev *dev);
developerf50c1802022-07-05 20:35:53 +0800996@@ -683,7 +686,7 @@ int mt7915_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
developer8cb3ac72022-07-04 10:55:14 +0800997 struct mt76_tx_info *tx_info);
998 void mt7915_tx_token_put(struct mt7915_dev *dev);
999 void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1000- struct sk_buff *skb);
1001+ struct sk_buff *skb, u32 info);
1002 bool mt7915_rx_check(struct mt76_dev *mdev, void *data, int len);
1003 void mt7915_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps);
1004 void mt7915_stats_work(struct work_struct *work);
1005diff --git a/mt7915/regs.h b/mt7915/regs.h
developerf50c1802022-07-05 20:35:53 +08001006index ffda5f6..08bf84c 100644
developer8cb3ac72022-07-04 10:55:14 +08001007--- a/mt7915/regs.h
1008+++ b/mt7915/regs.h
1009@@ -33,6 +33,9 @@ enum reg_rev {
1010 FW_EXCEPTION_ADDR,
1011 SWDEF_BASE_ADDR,
1012 EXCEPTION_BASE_ADDR,
1013+ WED_TX_RING,
1014+ WED_RX_RING,
1015+ WED_RX_DATA_RING,
1016 __MT_REG_MAX,
1017 };
1018
1019@@ -570,9 +573,13 @@ enum offs_rev {
1020 #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2 BIT(21)
1021
1022 #define MT_WFDMA0_RST_DTX_PTR MT_WFDMA0(0x20c)
1023+#define MT_WFDMA0_EXT0_CFG MT_WFDMA0(0x2b0)
1024+#define MT_WFDMA0_EXT0_RXWB_KEEP BIT(10)
1025+
1026 #define MT_WFDMA0_PRI_DLY_INT_CFG0 MT_WFDMA0(0x2f0)
1027 #define MT_WFDMA0_PRI_DLY_INT_CFG1 MT_WFDMA0(0x2f4)
1028 #define MT_WFDMA0_PRI_DLY_INT_CFG2 MT_WFDMA0(0x2f8)
1029+#define MT_WPDMA_GLO_CFG MT_WFDMA0(0x208)
1030
1031 #define MT_WFDMA0_MCU_HOST_INT_ENA MT_WFDMA0(0x1f4)
1032 #define MT_WFDMA0_MT_WA_WDT_INT BIT(31)
1033@@ -670,12 +677,15 @@ enum offs_rev {
1034 #define MT_TXQ_EXT_CTRL(q) (MT_Q_BASE(__TXQ(q)) + 0x600 + \
1035 MT_TXQ_ID(q)* 0x4)
1036
1037-#define MT_TXQ_WED_RING_BASE (!is_mt7986(mdev)? 0xd7300 : 0x24420)
1038-#define MT_RXQ_WED_RING_BASE (!is_mt7986(mdev)? 0xd7410 : 0x24520)
1039+#define MT_TXQ_WED_RING_BASE __REG(WED_TX_RING)
1040+#define MT_RXQ_WED_RING_BASE __REG(WED_RX_RING)
1041+#define MT_RXQ_WED_DATA_RING_BASE __REG(WED_RX_DATA_RING)
1042
1043 #define MT_WED_TX_DONE_BAND0 (is_mt7915(mdev)? 4 : 30)
1044 #define MT_WED_TX_DONE_BAND1 (is_mt7915(mdev)? 5 : 31)
1045 #define MT_WED_TX_FREE_DONE (is_mt7915(mdev)? 1 : 2)
1046+#define MT_WED_RX_DONE_BAND0 (is_mt7915(mdev)? 16 : 22)
1047+#define MT_WED_RX_DONE_BAND1 (is_mt7915(mdev)? 17 : 23)
1048
1049 #define MT_INT_SOURCE_CSR __REG(INT_SOURCE_CSR)
1050 #define MT_INT_MASK_CSR __REG(INT_MASK_CSR)
1051diff --git a/mt7921/mac.c b/mt7921/mac.c
developerf50c1802022-07-05 20:35:53 +08001052index 4fcadf8..4897940 100644
developer8cb3ac72022-07-04 10:55:14 +08001053--- a/mt7921/mac.c
1054+++ b/mt7921/mac.c
1055@@ -555,7 +555,7 @@ out:
1056 EXPORT_SYMBOL_GPL(mt7921_mac_add_txs);
1057
1058 void mt7921_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1059- struct sk_buff *skb)
1060+ struct sk_buff *skb, u32 info)
1061 {
1062 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
1063 __le32 *rxd = (__le32 *)skb->data;
1064diff --git a/mt7921/mt7921.h b/mt7921/mt7921.h
developerf50c1802022-07-05 20:35:53 +08001065index efeb82c..4b2e974 100644
developer8cb3ac72022-07-04 10:55:14 +08001066--- a/mt7921/mt7921.h
1067+++ b/mt7921/mt7921.h
1068@@ -388,7 +388,7 @@ int mt7921e_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
1069 void mt7921_tx_worker(struct mt76_worker *w);
1070 void mt7921_tx_token_put(struct mt7921_dev *dev);
1071 void mt7921_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1072- struct sk_buff *skb);
1073+ struct sk_buff *skb, u32 info);
1074 void mt7921_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps);
1075 void mt7921_stats_work(struct work_struct *work);
1076 void mt7921_set_stream_he_caps(struct mt7921_phy *phy);
1077@@ -424,7 +424,7 @@ int mt7921_mcu_parse_response(struct mt76_dev *mdev, int cmd,
1078
1079 bool mt7921e_rx_check(struct mt76_dev *mdev, void *data, int len);
1080 void mt7921e_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1081- struct sk_buff *skb);
1082+ struct sk_buff *skb, u32 info);
1083 int mt7921e_driver_own(struct mt7921_dev *dev);
1084 int mt7921e_mac_reset(struct mt7921_dev *dev);
1085 int mt7921e_mcu_init(struct mt7921_dev *dev);
1086diff --git a/mt7921/pci_mac.c b/mt7921/pci_mac.c
developerf50c1802022-07-05 20:35:53 +08001087index e180067..ca982eb 100644
developer8cb3ac72022-07-04 10:55:14 +08001088--- a/mt7921/pci_mac.c
1089+++ b/mt7921/pci_mac.c
1090@@ -182,7 +182,7 @@ bool mt7921e_rx_check(struct mt76_dev *mdev, void *data, int len)
1091 }
1092
1093 void mt7921e_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1094- struct sk_buff *skb)
1095+ struct sk_buff *skb, u32 info)
1096 {
1097 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
1098 __le32 *rxd = (__le32 *)skb->data;
1099@@ -196,7 +196,7 @@ void mt7921e_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1100 napi_consume_skb(skb, 1);
1101 break;
1102 default:
1103- mt7921_queue_rx_skb(mdev, q, skb);
1104+ mt7921_queue_rx_skb(mdev, q, skb, info);
1105 break;
1106 }
1107 }
1108diff --git a/tx.c b/tx.c
developerf50c1802022-07-05 20:35:53 +08001109index ae44afe..bccd206 100644
developer8cb3ac72022-07-04 10:55:14 +08001110--- a/tx.c
1111+++ b/tx.c
developerf50c1802022-07-05 20:35:53 +08001112@@ -767,3 +767,37 @@ mt76_token_release(struct mt76_dev *dev, int token, bool *wake)
developer8cb3ac72022-07-04 10:55:14 +08001113 return txwi;
1114 }
1115 EXPORT_SYMBOL_GPL(mt76_token_release);
1116+
1117+int mt76_rx_token_consume(struct mt76_dev *dev, void *ptr,
1118+ struct mt76_txwi_cache *r, dma_addr_t phys)
1119+{
1120+ int token;
1121+
1122+ spin_lock_bh(&dev->rx_token_lock);
1123+
1124+ token = idr_alloc(&dev->rx_token, r, 0, dev->rx_token_size, GFP_ATOMIC);
1125+
1126+ spin_unlock_bh(&dev->rx_token_lock);
1127+
1128+ r->buf = ptr;
1129+ r->dma_addr = phys;
1130+
1131+ return token;
1132+}
1133+EXPORT_SYMBOL_GPL(mt76_rx_token_consume);
1134+
1135+struct mt76_txwi_cache *
1136+mt76_rx_token_release(struct mt76_dev *dev, int token)
1137+{
1138+
1139+ struct mt76_txwi_cache *rxwi;
1140+
1141+ spin_lock_bh(&dev->rx_token_lock);
1142+
1143+ rxwi = idr_remove(&dev->rx_token, token);
1144+
1145+ spin_unlock_bh(&dev->rx_token_lock);
1146+
1147+ return rxwi;
1148+}
1149+EXPORT_SYMBOL_GPL(mt76_rx_token_release);
1150--
11512.18.0
1152