blob: 826543430f15d522420a79ce5b318cb89aec82b9 [file] [log] [blame]
developerd59e4772022-07-14 13:48:49 +08001From a6bbc51840c63e5992c2d0cee9fbbb795312da0c Mon Sep 17 00:00:00 2001
developer8cb3ac72022-07-04 10:55:14 +08002From: Sujuan Chen <sujuan.chen@mediatek.com>
developerf50c1802022-07-05 20:35:53 +08003Date: Tue, 5 Jul 2022 19:42:55 +0800
developerd59e4772022-07-14 13:48:49 +08004Subject: [PATCH 3002/3003] mt76 add wed rx support
developer8cb3ac72022-07-04 10:55:14 +08005
6Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
7---
developerc32bdb22022-07-20 16:15:39 +08008 drivers/net/wireless/mediatek/mt76/dma.c | 250 +++++++++++++++---
developerd59e4772022-07-14 13:48:49 +08009 drivers/net/wireless/mediatek/mt76/dma.h | 10 +
10 drivers/net/wireless/mediatek/mt76/mac80211.c | 8 +-
11 drivers/net/wireless/mediatek/mt76/mt76.h | 24 +-
12 .../net/wireless/mediatek/mt76/mt7603/dma.c | 2 +-
13 .../wireless/mediatek/mt76/mt7603/mt7603.h | 2 +-
14 .../net/wireless/mediatek/mt76/mt7615/mac.c | 2 +-
15 .../wireless/mediatek/mt76/mt7615/mt7615.h | 2 +-
16 .../wireless/mediatek/mt76/mt76_connac_mcu.c | 9 +
17 drivers/net/wireless/mediatek/mt76/mt76x02.h | 2 +-
18 .../net/wireless/mediatek/mt76/mt76x02_txrx.c | 2 +-
19 .../net/wireless/mediatek/mt76/mt7915/dma.c | 10 +
20 .../net/wireless/mediatek/mt76/mt7915/mac.c | 103 +++++++-
21 .../net/wireless/mediatek/mt76/mt7915/mcu.c | 3 +
22 .../net/wireless/mediatek/mt76/mt7915/mmio.c | 26 +-
23 .../wireless/mediatek/mt76/mt7915/mt7915.h | 7 +-
24 .../net/wireless/mediatek/mt76/mt7915/regs.h | 14 +-
25 .../net/wireless/mediatek/mt76/mt7921/mac.c | 2 +-
26 .../wireless/mediatek/mt76/mt7921/mt7921.h | 4 +-
27 .../wireless/mediatek/mt76/mt7921/pci_mac.c | 4 +-
28 drivers/net/wireless/mediatek/mt76/tx.c | 34 +++
developera3f86ed2022-07-08 14:15:13 +080029 21 files changed, 448 insertions(+), 68 deletions(-)
developer8cb3ac72022-07-04 10:55:14 +080030
31diff --git a/dma.c b/dma.c
developerd59e4772022-07-14 13:48:49 +080032index 03ee9109..3acba9a3 100644
developer8cb3ac72022-07-04 10:55:14 +080033--- a/dma.c
34+++ b/dma.c
35@@ -98,6 +98,63 @@ mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t)
36 }
37 EXPORT_SYMBOL_GPL(mt76_put_txwi);
38
39+static struct mt76_txwi_cache *
40+mt76_alloc_rxwi(struct mt76_dev *dev)
41+{
42+ struct mt76_txwi_cache *r;
43+ int size;
44+
45+ size = L1_CACHE_ALIGN(sizeof(*r));
46+ r = kzalloc(size, GFP_ATOMIC);
47+ if (!r)
48+ return NULL;
49+
50+ r->buf = NULL;
51+
52+ return r;
53+}
54+
55+static struct mt76_txwi_cache *
56+__mt76_get_rxwi(struct mt76_dev *dev)
57+{
58+ struct mt76_txwi_cache *r = NULL;
59+
60+ spin_lock(&dev->wed_lock);
61+ if (!list_empty(&dev->rxwi_cache)) {
62+ r = list_first_entry(&dev->rxwi_cache, struct mt76_txwi_cache,
63+ list);
64+ if(r)
65+ list_del(&r->list);
66+ }
67+ spin_unlock(&dev->wed_lock);
68+
69+ return r;
70+}
71+
72+struct mt76_txwi_cache *
73+mt76_get_rxwi(struct mt76_dev *dev)
74+{
75+ struct mt76_txwi_cache *r = __mt76_get_rxwi(dev);
76+
77+ if (r)
78+ return r;
79+
80+ return mt76_alloc_rxwi(dev);
81+}
82+EXPORT_SYMBOL_GPL(mt76_get_rxwi);
83+
84+void
85+mt76_put_rxwi(struct mt76_dev *dev, struct mt76_txwi_cache *r)
86+{
87+ if (!r)
88+ return;
89+
90+ spin_lock(&dev->wed_lock);
91+ list_add(&r->list, &dev->rxwi_cache);
92+ spin_unlock(&dev->wed_lock);
93+}
94+EXPORT_SYMBOL_GPL(mt76_put_rxwi);
95+
96 static void
97 mt76_free_pending_txwi(struct mt76_dev *dev)
98 {
developera3f86ed2022-07-08 14:15:13 +080099@@ -112,6 +169,21 @@ mt76_free_pending_txwi(struct mt76_dev *dev)
100 local_bh_enable();
101 }
102
103+static void
104+mt76_free_pending_rxwi(struct mt76_dev *dev)
105+{
106+ struct mt76_txwi_cache *r;
107+
108+ local_bh_disable();
109+ while ((r = __mt76_get_rxwi(dev)) != NULL) {
110+ if (r->buf)
111+ skb_free_frag(r->buf);
112+
113+ kfree(r);
114+ }
115+ local_bh_enable();
116+}
117+
118 static void
119 mt76_dma_sync_idx(struct mt76_dev *dev, struct mt76_queue *q)
120 {
121@@ -141,12 +213,15 @@ mt76_dma_queue_reset(struct mt76_dev *dev, struct mt76_queue *q)
developer8cb3ac72022-07-04 10:55:14 +0800122 static int
123 mt76_dma_add_buf(struct mt76_dev *dev, struct mt76_queue *q,
124 struct mt76_queue_buf *buf, int nbufs, u32 info,
125- struct sk_buff *skb, void *txwi)
126+ struct sk_buff *skb, void *txwi, void *rxwi)
127 {
128+ struct mtk_wed_device *wed = &dev->mmio.wed;
129+
130 struct mt76_queue_entry *entry;
131 struct mt76_desc *desc;
132 u32 ctrl;
133 int i, idx = -1;
134+ int type;
135
136 if (txwi) {
137 q->entry[q->head].txwi = DMA_DUMMY_DATA;
developera3f86ed2022-07-08 14:15:13 +0800138@@ -162,28 +237,42 @@ mt76_dma_add_buf(struct mt76_dev *dev, struct mt76_queue *q,
developer8cb3ac72022-07-04 10:55:14 +0800139 desc = &q->desc[idx];
140 entry = &q->entry[idx];
141
142- if (buf[0].skip_unmap)
143- entry->skip_buf0 = true;
144- entry->skip_buf1 = i == nbufs - 1;
145-
146- entry->dma_addr[0] = buf[0].addr;
147- entry->dma_len[0] = buf[0].len;
148-
149- ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, buf[0].len);
150- if (i < nbufs - 1) {
151- entry->dma_addr[1] = buf[1].addr;
152- entry->dma_len[1] = buf[1].len;
153- buf1 = buf[1].addr;
154- ctrl |= FIELD_PREP(MT_DMA_CTL_SD_LEN1, buf[1].len);
155- if (buf[1].skip_unmap)
156- entry->skip_buf1 = true;
157+ type = FIELD_GET(MT_QFLAG_WED_TYPE, q->flags);
158+ if (mtk_wed_device_active(wed) && type == MT76_WED_Q_RX) {
159+ struct mt76_txwi_cache *r = rxwi;
160+ int rx_token;
161+
162+ if (!r)
163+ return -ENOMEM;
164+
165+ rx_token = mt76_rx_token_consume(dev, (void *)skb, r, buf[0].addr);
166+
167+ buf1 |= FIELD_PREP(MT_DMA_CTL_TOKEN, rx_token);
168+ ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, MTK_WED_RX_PKT_SIZE);
169+ ctrl |= MT_DMA_CTL_TO_HOST;
170+ } else {
171+ if (buf[0].skip_unmap)
172+ entry->skip_buf0 = true;
173+ entry->skip_buf1 = i == nbufs - 1;
174+
175+ entry->dma_addr[0] = buf[0].addr;
176+ entry->dma_len[0] = buf[0].len;
177+
178+ ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, buf[0].len);
179+ if (i < nbufs - 1) {
180+ entry->dma_addr[1] = buf[1].addr;
181+ entry->dma_len[1] = buf[1].len;
182+ buf1 = buf[1].addr;
183+ ctrl |= FIELD_PREP(MT_DMA_CTL_SD_LEN1, buf[1].len);
184+ if (buf[1].skip_unmap)
185+ entry->skip_buf1 = true;
186+ }
187+ if (i == nbufs - 1)
188+ ctrl |= MT_DMA_CTL_LAST_SEC0;
189+ else if (i == nbufs - 2)
190+ ctrl |= MT_DMA_CTL_LAST_SEC1;
191 }
192
193- if (i == nbufs - 1)
194- ctrl |= MT_DMA_CTL_LAST_SEC0;
195- else if (i == nbufs - 2)
196- ctrl |= MT_DMA_CTL_LAST_SEC1;
197-
198 WRITE_ONCE(desc->buf0, cpu_to_le32(buf0));
199 WRITE_ONCE(desc->buf1, cpu_to_le32(buf1));
200 WRITE_ONCE(desc->info, cpu_to_le32(info));
developerc32bdb22022-07-20 16:15:39 +0800201@@ -272,33 +361,65 @@ mt76_dma_tx_cleanup(struct mt76_dev *dev, struct mt76_queue *q, bool flush)
developer8cb3ac72022-07-04 10:55:14 +0800202
203 static void *
204 mt76_dma_get_buf(struct mt76_dev *dev, struct mt76_queue *q, int idx,
205- int *len, u32 *info, bool *more)
206+ int *len, u32 *info, bool *more, bool *drop)
207 {
208 struct mt76_queue_entry *e = &q->entry[idx];
209 struct mt76_desc *desc = &q->desc[idx];
210 dma_addr_t buf_addr;
developerc32bdb22022-07-20 16:15:39 +0800211- void *buf = e->buf;
212+ void *buf = e->buf, *copy = NULL;
developer8cb3ac72022-07-04 10:55:14 +0800213 int buf_len = SKB_WITH_OVERHEAD(q->buf_size);
214+ struct mtk_wed_device *wed = &dev->mmio.wed;
215+ int type;
216
217- buf_addr = e->dma_addr[0];
218 if (len) {
219 u32 ctl = le32_to_cpu(READ_ONCE(desc->ctrl));
220 *len = FIELD_GET(MT_DMA_CTL_SD_LEN0, ctl);
221 *more = !(ctl & MT_DMA_CTL_LAST_SEC0);
222 }
223
224- if (info)
225- *info = le32_to_cpu(desc->info);
226+ type = FIELD_GET(MT_QFLAG_WED_TYPE, q->flags);
227+ if (mtk_wed_device_active(wed) && type == MT76_WED_Q_RX) {
228+ u32 token;
229+ struct mt76_txwi_cache *r;
230+
231+ token = FIELD_GET(MT_DMA_CTL_TOKEN, desc->buf1);
232+
233+ r = mt76_rx_token_release(dev, token);
234+ if (!r)
235+ return NULL;
236+
237+ buf = page_frag_alloc(&q->rx_page, q->buf_size, GFP_ATOMIC);
238+ if (!buf)
239+ return NULL;
240+
developerc32bdb22022-07-20 16:15:39 +0800241+ copy = r->buf;
developer8cb3ac72022-07-04 10:55:14 +0800242+ buf_addr = r->dma_addr;
243+ buf_len = MTK_WED_RX_PKT_SIZE;
244+ r->dma_addr = 0;
developer8cb3ac72022-07-04 10:55:14 +0800245+
246+ mt76_put_rxwi(dev, r);
247+
248+ if (desc->ctrl & (MT_DMA_CTL_TO_HOST_A | MT_DMA_CTL_DROP))
249+ *drop = true;
250+ } else {
251+ buf_addr = e->dma_addr[0];
252+ e->buf = NULL;
253+ }
254
255 dma_unmap_single(dev->dma_dev, buf_addr, buf_len, DMA_FROM_DEVICE);
256- e->buf = NULL;
257+
developerc32bdb22022-07-20 16:15:39 +0800258+ if (copy)
259+ memcpy(buf, copy, MTK_WED_RX_PKT_SIZE);
260+
developer8cb3ac72022-07-04 10:55:14 +0800261+ if (info)
262+ *info = le32_to_cpu(desc->info);
263
264 return buf;
265 }
266
267 static void *
268 mt76_dma_dequeue(struct mt76_dev *dev, struct mt76_queue *q, bool flush,
269- int *len, u32 *info, bool *more)
270+ int *len, u32 *info, bool *more, bool *drop)
271 {
272 int idx = q->tail;
273
developera3f86ed2022-07-08 14:15:13 +0800274@@ -314,7 +433,7 @@ mt76_dma_dequeue(struct mt76_dev *dev, struct mt76_queue *q, bool flush,
developer8cb3ac72022-07-04 10:55:14 +0800275 q->tail = (q->tail + 1) % q->ndesc;
276 q->queued--;
277
278- return mt76_dma_get_buf(dev, q, idx, len, info, more);
279+ return mt76_dma_get_buf(dev, q, idx, len, info, more, drop);
280 }
281
282 static int
developera3f86ed2022-07-08 14:15:13 +0800283@@ -336,7 +455,7 @@ mt76_dma_tx_queue_skb_raw(struct mt76_dev *dev, struct mt76_queue *q,
developer8cb3ac72022-07-04 10:55:14 +0800284 buf.len = skb->len;
285
286 spin_lock_bh(&q->lock);
287- mt76_dma_add_buf(dev, q, &buf, 1, tx_info, skb, NULL);
288+ mt76_dma_add_buf(dev, q, &buf, 1, tx_info, skb, NULL, NULL);
289 mt76_dma_kick_queue(dev, q);
290 spin_unlock_bh(&q->lock);
291
developera3f86ed2022-07-08 14:15:13 +0800292@@ -413,7 +532,7 @@ mt76_dma_tx_queue_skb(struct mt76_dev *dev, struct mt76_queue *q,
developer8cb3ac72022-07-04 10:55:14 +0800293 goto unmap;
294
295 return mt76_dma_add_buf(dev, q, tx_info.buf, tx_info.nbuf,
296- tx_info.info, tx_info.skb, t);
297+ tx_info.info, tx_info.skb, t, NULL);
298
299 unmap:
300 for (n--; n > 0; n--)
developera3f86ed2022-07-08 14:15:13 +0800301@@ -448,6 +567,8 @@ mt76_dma_rx_fill(struct mt76_dev *dev, struct mt76_queue *q)
developer8cb3ac72022-07-04 10:55:14 +0800302 int frames = 0;
303 int len = SKB_WITH_OVERHEAD(q->buf_size);
304 int offset = q->buf_offset;
305+ struct mtk_wed_device *wed = &dev->mmio.wed;
developera3f86ed2022-07-08 14:15:13 +0800306+ struct page_frag_cache *rx_page;
developer8cb3ac72022-07-04 10:55:14 +0800307
308 if (!q->ndesc)
309 return 0;
developera3f86ed2022-07-08 14:15:13 +0800310@@ -456,10 +577,29 @@ mt76_dma_rx_fill(struct mt76_dev *dev, struct mt76_queue *q)
developer8cb3ac72022-07-04 10:55:14 +0800311
312 while (q->queued < q->ndesc - 1) {
313 struct mt76_queue_buf qbuf;
314+ int type = FIELD_GET(MT_QFLAG_WED_TYPE, q->flags);
315+ bool skip_alloc = false;
316+ struct mt76_txwi_cache *r = NULL;
317+
developera3f86ed2022-07-08 14:15:13 +0800318+ rx_page = &q->rx_page;
developer8cb3ac72022-07-04 10:55:14 +0800319+ if (mtk_wed_device_active(wed) && type == MT76_WED_Q_RX) {
developera3f86ed2022-07-08 14:15:13 +0800320+ rx_page = &wed->rx_page;
developer8cb3ac72022-07-04 10:55:14 +0800321+ r = mt76_get_rxwi(dev);
322+ if (!r)
323+ return -ENOMEM;
324+
325+ if (r->buf) {
326+ skip_alloc = true;
327+ len = MTK_WED_RX_PKT_SIZE;
328+ buf = r->buf;
329+ }
330+ }
331
332- buf = page_frag_alloc(&q->rx_page, q->buf_size, GFP_ATOMIC);
333- if (!buf)
334- break;
335+ if (!skip_alloc) {
developera3f86ed2022-07-08 14:15:13 +0800336+ buf = page_frag_alloc(rx_page, q->buf_size, GFP_ATOMIC);
developer8cb3ac72022-07-04 10:55:14 +0800337+ if (!buf)
338+ break;
339+ }
340
341 addr = dma_map_single(dev->dma_dev, buf, len, DMA_FROM_DEVICE);
342 if (unlikely(dma_mapping_error(dev->dma_dev, addr))) {
developera3f86ed2022-07-08 14:15:13 +0800343@@ -470,7 +610,7 @@ mt76_dma_rx_fill(struct mt76_dev *dev, struct mt76_queue *q)
developer8cb3ac72022-07-04 10:55:14 +0800344 qbuf.addr = addr + offset;
345 qbuf.len = len - offset;
346 qbuf.skip_unmap = false;
347- mt76_dma_add_buf(dev, q, &qbuf, 1, 0, buf, NULL);
348+ mt76_dma_add_buf(dev, q, &qbuf, 1, 0, buf, NULL, r);
349 frames++;
350 }
351
developera3f86ed2022-07-08 14:15:13 +0800352@@ -516,6 +656,11 @@ mt76_dma_wed_setup(struct mt76_dev *dev, struct mt76_queue *q)
developer8cb3ac72022-07-04 10:55:14 +0800353 if (!ret)
354 q->wed_regs = wed->txfree_ring.reg_base;
355 break;
356+ case MT76_WED_Q_RX:
357+ ret = mtk_wed_device_rx_ring_setup(wed, ring, q->regs);
358+ if (!ret)
359+ q->wed_regs = wed->rx_ring[ring].reg_base;
360+ break;
361 default:
362 ret = -EINVAL;
363 }
developera3f86ed2022-07-08 14:15:13 +0800364@@ -531,7 +676,8 @@ mt76_dma_alloc_queue(struct mt76_dev *dev, struct mt76_queue *q,
developer8cb3ac72022-07-04 10:55:14 +0800365 int idx, int n_desc, int bufsize,
366 u32 ring_base)
367 {
368- int ret, size;
369+ int ret, size, type;
370+ struct mtk_wed_device *wed = &dev->mmio.wed;
371
372 spin_lock_init(&q->lock);
373 spin_lock_init(&q->cleanup_lock);
developera3f86ed2022-07-08 14:15:13 +0800374@@ -541,6 +687,11 @@ mt76_dma_alloc_queue(struct mt76_dev *dev, struct mt76_queue *q,
developer8cb3ac72022-07-04 10:55:14 +0800375 q->buf_size = bufsize;
376 q->hw_idx = idx;
377
378+ type = FIELD_GET(MT_QFLAG_WED_TYPE, q->flags);
379+ if (mtk_wed_device_active(wed) && type == MT76_WED_Q_RX)
380+ q->buf_size = SKB_DATA_ALIGN(NET_SKB_PAD + MTK_WED_RX_PKT_SIZE) +
381+ SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
382+
383 size = q->ndesc * sizeof(struct mt76_desc);
384 q->desc = dmam_alloc_coherent(dev->dma_dev, size, &q->desc_dma, GFP_KERNEL);
385 if (!q->desc)
developera3f86ed2022-07-08 14:15:13 +0800386@@ -573,7 +724,7 @@ mt76_dma_rx_cleanup(struct mt76_dev *dev, struct mt76_queue *q)
developer8cb3ac72022-07-04 10:55:14 +0800387
388 spin_lock_bh(&q->lock);
389 do {
390- buf = mt76_dma_dequeue(dev, q, true, NULL, NULL, &more);
391+ buf = mt76_dma_dequeue(dev, q, true, NULL, NULL, &more, NULL);
392 if (!buf)
393 break;
394
developera3f86ed2022-07-08 14:15:13 +0800395@@ -614,7 +765,7 @@ mt76_dma_rx_reset(struct mt76_dev *dev, enum mt76_rxq_id qid)
developer8cb3ac72022-07-04 10:55:14 +0800396
397 static void
398 mt76_add_fragment(struct mt76_dev *dev, struct mt76_queue *q, void *data,
399- int len, bool more)
400+ int len, bool more, u32 info)
401 {
402 struct sk_buff *skb = q->rx_head;
403 struct skb_shared_info *shinfo = skb_shinfo(skb);
developera3f86ed2022-07-08 14:15:13 +0800404@@ -634,7 +785,7 @@ mt76_add_fragment(struct mt76_dev *dev, struct mt76_queue *q, void *data,
developer8cb3ac72022-07-04 10:55:14 +0800405
406 q->rx_head = NULL;
407 if (nr_frags < ARRAY_SIZE(shinfo->frags))
408- dev->drv->rx_skb(dev, q - dev->q_rx, skb);
409+ dev->drv->rx_skb(dev, q - dev->q_rx, skb, info);
410 else
411 dev_kfree_skb(skb);
412 }
developera3f86ed2022-07-08 14:15:13 +0800413@@ -655,6 +806,7 @@ mt76_dma_rx_process(struct mt76_dev *dev, struct mt76_queue *q, int budget)
developer8cb3ac72022-07-04 10:55:14 +0800414 }
415
416 while (done < budget) {
417+ bool drop = false;
418 u32 info;
419
420 if (check_ddone) {
developera3f86ed2022-07-08 14:15:13 +0800421@@ -665,10 +817,13 @@ mt76_dma_rx_process(struct mt76_dev *dev, struct mt76_queue *q, int budget)
developer8cb3ac72022-07-04 10:55:14 +0800422 break;
423 }
424
425- data = mt76_dma_dequeue(dev, q, false, &len, &info, &more);
426+ data = mt76_dma_dequeue(dev, q, false, &len, &info, &more, &drop);
427 if (!data)
428 break;
429
430+ if (drop)
431+ goto free_frag;
432+
433 if (q->rx_head)
434 data_len = q->buf_size;
435 else
developera3f86ed2022-07-08 14:15:13 +0800436@@ -681,7 +836,7 @@ mt76_dma_rx_process(struct mt76_dev *dev, struct mt76_queue *q, int budget)
developer8cb3ac72022-07-04 10:55:14 +0800437 }
438
439 if (q->rx_head) {
440- mt76_add_fragment(dev, q, data, len, more);
441+ mt76_add_fragment(dev, q, data, len, more, info);
442 continue;
443 }
444
developera3f86ed2022-07-08 14:15:13 +0800445@@ -708,7 +863,7 @@ mt76_dma_rx_process(struct mt76_dev *dev, struct mt76_queue *q, int budget)
developer8cb3ac72022-07-04 10:55:14 +0800446 continue;
447 }
448
449- dev->drv->rx_skb(dev, q - dev->q_rx, skb);
450+ dev->drv->rx_skb(dev, q - dev->q_rx, skb, info);
451 continue;
452
453 free_frag:
developerd59e4772022-07-14 13:48:49 +0800454@@ -785,7 +940,7 @@ EXPORT_SYMBOL_GPL(mt76_dma_attach);
developera3f86ed2022-07-08 14:15:13 +0800455
456 void mt76_dma_cleanup(struct mt76_dev *dev)
457 {
458- int i;
developera3f86ed2022-07-08 14:15:13 +0800459+ int i, type;
developerd59e4772022-07-14 13:48:49 +0800460
developera3f86ed2022-07-08 14:15:13 +0800461 mt76_worker_disable(&dev->tx_worker);
462 netif_napi_del(&dev->tx_napi);
developera3f86ed2022-07-08 14:15:13 +0800463@@ -801,12 +956,17 @@ void mt76_dma_cleanup(struct mt76_dev *dev)
464
465 mt76_for_each_q_rx(dev, i) {
466 netif_napi_del(&dev->napi[i]);
467- mt76_dma_rx_cleanup(dev, &dev->q_rx[i]);
468+ type = FIELD_GET(MT_QFLAG_WED_TYPE, dev->q_rx[i].flags);
469+ if (type != MT76_WED_Q_RX)
470+ mt76_dma_rx_cleanup(dev, &dev->q_rx[i]);
471 }
472
473 mt76_free_pending_txwi(dev);
474+ mt76_free_pending_rxwi(dev);
475
476 if (mtk_wed_device_active(&dev->mmio.wed))
477 mtk_wed_device_detach(&dev->mmio.wed);
478+
479+ mt76_free_pending_rxwi(dev);
480 }
481 EXPORT_SYMBOL_GPL(mt76_dma_cleanup);
developer8cb3ac72022-07-04 10:55:14 +0800482diff --git a/dma.h b/dma.h
developerd59e4772022-07-14 13:48:49 +0800483index fdf786f9..90370d12 100644
developer8cb3ac72022-07-04 10:55:14 +0800484--- a/dma.h
485+++ b/dma.h
486@@ -16,6 +16,16 @@
487 #define MT_DMA_CTL_LAST_SEC0 BIT(30)
488 #define MT_DMA_CTL_DMA_DONE BIT(31)
489
490+#define MT_DMA_CTL_TO_HOST BIT(8)
491+#define MT_DMA_CTL_TO_HOST_A BIT(12)
492+#define MT_DMA_CTL_DROP BIT(14)
493+
494+#define MT_DMA_CTL_TOKEN GENMASK(31, 16)
495+
496+#define MT_DMA_PPE_CPU_REASON GENMASK(15, 11)
497+#define MT_DMA_PPE_ENTRY GENMASK(30, 16)
498+#define MT_DMA_INFO_PPE_VLD BIT(31)
499+
500 #define MT_DMA_HDR_LEN 4
501 #define MT_RX_INFO_LEN 4
502 #define MT_FCE_INFO_LEN 4
503diff --git a/mac80211.c b/mac80211.c
developerd59e4772022-07-14 13:48:49 +0800504index af2c09ad..fa5ce6ec 100644
developer8cb3ac72022-07-04 10:55:14 +0800505--- a/mac80211.c
506+++ b/mac80211.c
507@@ -594,11 +594,14 @@ mt76_alloc_device(struct device *pdev, unsigned int size,
508 BIT(NL80211_IFTYPE_ADHOC);
509
510 spin_lock_init(&dev->token_lock);
511+ spin_lock_init(&dev->rx_token_lock);
512 idr_init(&dev->token);
513+ idr_init(&dev->rx_token);
514
515 INIT_LIST_HEAD(&dev->wcid_list);
516
517 INIT_LIST_HEAD(&dev->txwi_cache);
518+ INIT_LIST_HEAD(&dev->rxwi_cache);
519 dev->token_size = dev->drv->token_size;
520
521 for (i = 0; i < ARRAY_SIZE(dev->q_rx); i++)
522@@ -1296,7 +1299,10 @@ void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q,
523
524 while ((skb = __skb_dequeue(&dev->rx_skb[q])) != NULL) {
525 mt76_check_sta(dev, skb);
526- mt76_rx_aggr_reorder(skb, &frames);
527+ if (mtk_wed_device_active(&dev->mmio.wed))
528+ __skb_queue_tail(&frames, skb);
529+ else
530+ mt76_rx_aggr_reorder(skb, &frames);
531 }
532
533 mt76_rx_complete(dev, &frames, napi);
534diff --git a/mt76.h b/mt76.h
developerd59e4772022-07-14 13:48:49 +0800535index 49314895..9162213a 100644
developer8cb3ac72022-07-04 10:55:14 +0800536--- a/mt76.h
537+++ b/mt76.h
538@@ -20,6 +20,8 @@
539
540 #define MT_MCU_RING_SIZE 32
541 #define MT_RX_BUF_SIZE 2048
542+#define MTK_WED_RX_PKT_SIZE 1700
543+
544 #define MT_SKB_HEAD_LEN 256
545
546 #define MT_MAX_NON_AQL_PKT 16
547@@ -35,6 +37,7 @@
548 FIELD_PREP(MT_QFLAG_WED_TYPE, _type) | \
549 FIELD_PREP(MT_QFLAG_WED_RING, _n))
550 #define MT_WED_Q_TX(_n) __MT_WED_Q(MT76_WED_Q_TX, _n)
551+#define MT_WED_Q_RX(_n) __MT_WED_Q(MT76_WED_Q_RX, _n)
552 #define MT_WED_Q_TXFREE __MT_WED_Q(MT76_WED_Q_TXFREE, 0)
553
554 struct mt76_dev;
555@@ -56,6 +59,7 @@ enum mt76_bus_type {
556 enum mt76_wed_type {
557 MT76_WED_Q_TX,
558 MT76_WED_Q_TXFREE,
559+ MT76_WED_Q_RX,
560 };
561
562 struct mt76_bus_ops {
563@@ -305,7 +309,10 @@ struct mt76_txwi_cache {
564 struct list_head list;
565 dma_addr_t dma_addr;
566
567- struct sk_buff *skb;
568+ union {
569+ void *buf;
570+ struct sk_buff *skb;
571+ };
572 };
573
574 struct mt76_rx_tid {
575@@ -403,7 +410,7 @@ struct mt76_driver_ops {
576 bool (*rx_check)(struct mt76_dev *dev, void *data, int len);
577
578 void (*rx_skb)(struct mt76_dev *dev, enum mt76_rxq_id q,
579- struct sk_buff *skb);
580+ struct sk_buff *skb, u32 info);
581
582 void (*rx_poll_complete)(struct mt76_dev *dev, enum mt76_rxq_id q);
583
584@@ -747,6 +754,7 @@ struct mt76_dev {
585 struct ieee80211_hw *hw;
586
587 spinlock_t lock;
588+ spinlock_t wed_lock;
589 spinlock_t cc_lock;
590
591 u32 cur_cc_bss_rx;
592@@ -772,6 +780,7 @@ struct mt76_dev {
593 struct sk_buff_head rx_skb[__MT_RXQ_MAX];
594
595 struct list_head txwi_cache;
596+ struct list_head rxwi_cache;
597 struct mt76_queue *q_mcu[__MT_MCUQ_MAX];
598 struct mt76_queue q_rx[__MT_RXQ_MAX];
599 const struct mt76_queue_ops *queue_ops;
600@@ -785,6 +794,9 @@ struct mt76_dev {
601 u16 wed_token_count;
602 u16 token_count;
603 u16 token_size;
604+ u16 rx_token_size;
605+ spinlock_t rx_token_lock;
606+ struct idr rx_token;
607
608 wait_queue_head_t tx_wait;
609 /* spinclock used to protect wcid pktid linked list */
developerd59e4772022-07-14 13:48:49 +0800610@@ -1352,6 +1364,8 @@ mt76_tx_status_get_hw(struct mt76_dev *dev, struct sk_buff *skb)
developer8cb3ac72022-07-04 10:55:14 +0800611 }
612
613 void mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t);
614+void mt76_put_rxwi(struct mt76_dev *dev, struct mt76_txwi_cache *t);
615+struct mt76_txwi_cache *mt76_get_rxwi(struct mt76_dev *dev);
616 void mt76_rx_complete(struct mt76_dev *dev, struct sk_buff_head *frames,
617 struct napi_struct *napi);
618 void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q,
developerd59e4772022-07-14 13:48:49 +0800619@@ -1496,6 +1510,12 @@ struct mt76_txwi_cache *
developer8cb3ac72022-07-04 10:55:14 +0800620 mt76_token_release(struct mt76_dev *dev, int token, bool *wake);
621 int mt76_token_consume(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi);
622 void __mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked);
623+int mt76_rx_token_consume(struct mt76_dev *dev, void *ptr,
624+ struct mt76_txwi_cache *r, dma_addr_t phys);
625+void skb_trace(const struct sk_buff *skb, bool full_pkt);
626+
627+struct mt76_txwi_cache *
628+mt76_rx_token_release(struct mt76_dev *dev, int token);
629
630 static inline void mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked)
631 {
632diff --git a/mt7603/dma.c b/mt7603/dma.c
developerd59e4772022-07-14 13:48:49 +0800633index 590cff9d..2ff71c53 100644
developer8cb3ac72022-07-04 10:55:14 +0800634--- a/mt7603/dma.c
635+++ b/mt7603/dma.c
636@@ -69,7 +69,7 @@ free:
637 }
638
639 void mt7603_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
640- struct sk_buff *skb)
641+ struct sk_buff *skb, u32 info)
642 {
643 struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76);
644 __le32 *rxd = (__le32 *)skb->data;
645diff --git a/mt7603/mt7603.h b/mt7603/mt7603.h
developerd59e4772022-07-14 13:48:49 +0800646index 0fd46d90..f2ce22ae 100644
developer8cb3ac72022-07-04 10:55:14 +0800647--- a/mt7603/mt7603.h
648+++ b/mt7603/mt7603.h
649@@ -244,7 +244,7 @@ int mt7603_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
650 void mt7603_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue_entry *e);
651
652 void mt7603_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
653- struct sk_buff *skb);
654+ struct sk_buff *skb, u32 info);
655 void mt7603_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q);
656 void mt7603_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps);
657 int mt7603_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif,
658diff --git a/mt7615/mac.c b/mt7615/mac.c
developerd59e4772022-07-14 13:48:49 +0800659index 37286276..14cdd9a2 100644
developer8cb3ac72022-07-04 10:55:14 +0800660--- a/mt7615/mac.c
661+++ b/mt7615/mac.c
developerf50c1802022-07-05 20:35:53 +0800662@@ -1648,7 +1648,7 @@ bool mt7615_rx_check(struct mt76_dev *mdev, void *data, int len)
developer8cb3ac72022-07-04 10:55:14 +0800663 EXPORT_SYMBOL_GPL(mt7615_rx_check);
664
665 void mt7615_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
666- struct sk_buff *skb)
667+ struct sk_buff *skb, u32 info)
668 {
669 struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
670 __le32 *rxd = (__le32 *)skb->data;
671diff --git a/mt7615/mt7615.h b/mt7615/mt7615.h
developerd59e4772022-07-14 13:48:49 +0800672index 25880d1a..983469c7 100644
developer8cb3ac72022-07-04 10:55:14 +0800673--- a/mt7615/mt7615.h
674+++ b/mt7615/mt7615.h
developerf50c1802022-07-05 20:35:53 +0800675@@ -511,7 +511,7 @@ void mt7615_tx_worker(struct mt76_worker *w);
developer8cb3ac72022-07-04 10:55:14 +0800676 void mt7615_tx_token_put(struct mt7615_dev *dev);
677 bool mt7615_rx_check(struct mt76_dev *mdev, void *data, int len);
678 void mt7615_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
679- struct sk_buff *skb);
680+ struct sk_buff *skb, u32 info);
681 void mt7615_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps);
682 int mt7615_mac_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif,
683 struct ieee80211_sta *sta);
684diff --git a/mt76_connac_mcu.c b/mt76_connac_mcu.c
developerd59e4772022-07-14 13:48:49 +0800685index cd350689..24548469 100644
developer8cb3ac72022-07-04 10:55:14 +0800686--- a/mt76_connac_mcu.c
687+++ b/mt76_connac_mcu.c
688@@ -1190,6 +1190,7 @@ int mt76_connac_mcu_sta_ba(struct mt76_dev *dev, struct mt76_vif *mvif,
689 int cmd, bool enable, bool tx)
690 {
691 struct mt76_wcid *wcid = (struct mt76_wcid *)params->sta->drv_priv;
692+ struct mtk_wed_device *wed = &dev->mmio.wed;
693 struct wtbl_req_hdr *wtbl_hdr;
694 struct tlv *sta_wtbl;
695 struct sk_buff *skb;
developerf50c1802022-07-05 20:35:53 +0800696@@ -1210,6 +1211,8 @@ int mt76_connac_mcu_sta_ba(struct mt76_dev *dev, struct mt76_vif *mvif,
developer8cb3ac72022-07-04 10:55:14 +0800697 mt76_connac_mcu_wtbl_ba_tlv(dev, skb, params, enable, tx, sta_wtbl,
698 wtbl_hdr);
699
developerf50c1802022-07-05 20:35:53 +0800700+ if (mtk_wed_device_active(wed) && wed->ver > MTK_WED_V1)
developer6adfa0e2022-07-06 16:25:53 +0800701+ mtk_wed_device_update_msg(wed, WED_WO_STA_REC, skb->data, skb->len);
developer8cb3ac72022-07-04 10:55:14 +0800702 ret = mt76_mcu_skb_send_msg(dev, skb, cmd, true);
703 if (ret)
704 return ret;
developerf50c1802022-07-05 20:35:53 +0800705@@ -1220,6 +1223,8 @@ int mt76_connac_mcu_sta_ba(struct mt76_dev *dev, struct mt76_vif *mvif,
developer8cb3ac72022-07-04 10:55:14 +0800706
707 mt76_connac_mcu_sta_ba_tlv(skb, params, enable, tx);
708
developerf50c1802022-07-05 20:35:53 +0800709+ if (mtk_wed_device_active(wed) && wed->ver > MTK_WED_V1)
710+ mtk_wed_device_update_msg(wed, WED_WO_STA_REC, skb->data, skb->len);
developer8cb3ac72022-07-04 10:55:14 +0800711 return mt76_mcu_skb_send_msg(dev, skb, cmd, true);
712 }
713 EXPORT_SYMBOL_GPL(mt76_connac_mcu_sta_ba);
developerf50c1802022-07-05 20:35:53 +0800714@@ -2634,6 +2639,7 @@ int mt76_connac_mcu_add_key(struct mt76_dev *dev, struct ieee80211_vif *vif,
developer8cb3ac72022-07-04 10:55:14 +0800715 struct mt76_wcid *wcid, enum set_key_cmd cmd)
716 {
717 struct mt76_vif *mvif = (struct mt76_vif *)vif->drv_priv;
718+ struct mtk_wed_device *wed = &dev->mmio.wed;
719 struct sk_buff *skb;
720 int ret;
721
developerf50c1802022-07-05 20:35:53 +0800722@@ -2645,6 +2651,9 @@ int mt76_connac_mcu_add_key(struct mt76_dev *dev, struct ieee80211_vif *vif,
developer8cb3ac72022-07-04 10:55:14 +0800723 if (ret)
724 return ret;
725
developerf50c1802022-07-05 20:35:53 +0800726+ if (mtk_wed_device_active(wed) && wed->ver > MTK_WED_V1)
developer8cb3ac72022-07-04 10:55:14 +0800727+ mtk_wed_device_update_msg(wed, WED_WO_STA_REC, skb->data, skb->len);
728+
729 return mt76_mcu_skb_send_msg(dev, skb, mcu_cmd, true);
730 }
731 EXPORT_SYMBOL_GPL(mt76_connac_mcu_add_key);
732diff --git a/mt76x02.h b/mt76x02.h
developerd59e4772022-07-14 13:48:49 +0800733index f76fd22e..0b872af1 100644
developer8cb3ac72022-07-04 10:55:14 +0800734--- a/mt76x02.h
735+++ b/mt76x02.h
736@@ -173,7 +173,7 @@ int mt76x02_set_rts_threshold(struct ieee80211_hw *hw, u32 val);
737 void mt76x02_remove_hdr_pad(struct sk_buff *skb, int len);
738 bool mt76x02_tx_status_data(struct mt76_dev *mdev, u8 *update);
739 void mt76x02_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
740- struct sk_buff *skb);
741+ struct sk_buff *skb, u32 info);
742 void mt76x02_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q);
743 irqreturn_t mt76x02_irq_handler(int irq, void *dev_instance);
744 void mt76x02_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control,
745diff --git a/mt76x02_txrx.c b/mt76x02_txrx.c
developerd59e4772022-07-14 13:48:49 +0800746index 96fdf423..bf24d3e0 100644
developer8cb3ac72022-07-04 10:55:14 +0800747--- a/mt76x02_txrx.c
748+++ b/mt76x02_txrx.c
749@@ -33,7 +33,7 @@ void mt76x02_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control,
750 EXPORT_SYMBOL_GPL(mt76x02_tx);
751
752 void mt76x02_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
753- struct sk_buff *skb)
754+ struct sk_buff *skb, u32 info)
755 {
756 struct mt76x02_dev *dev = container_of(mdev, struct mt76x02_dev, mt76);
757 void *rxwi = skb->data;
758diff --git a/mt7915/dma.c b/mt7915/dma.c
developerd59e4772022-07-14 13:48:49 +0800759index 71223221..ac98e01b 100644
developer8cb3ac72022-07-04 10:55:14 +0800760--- a/mt7915/dma.c
761+++ b/mt7915/dma.c
762@@ -376,6 +376,8 @@ int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2)
763 FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_TX0, 18) |
764 FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_TX1, 19) |
765 FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_RX1, 1));
766+ mt76_rmw(dev, MT_WFDMA0_EXT0_CFG, MT_WFDMA0_EXT0_RXWB_KEEP,
767+ MT_WFDMA0_EXT0_RXWB_KEEP);
768 } else {
769 mt76_wr(dev, MT_WFDMA_WED_RING_CONTROL,
770 FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_TX0, 18) |
developerf50c1802022-07-05 20:35:53 +0800771@@ -451,6 +453,10 @@ int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2)
developer8cb3ac72022-07-04 10:55:14 +0800772
773 /* rx data queue for band0 */
774 if (!dev->phy.band_idx) {
developerf50c1802022-07-05 20:35:53 +0800775+ if (mtk_wed_device_active(&dev->mt76.mmio.wed) &&
776+ dev->mt76.mmio.wed.ver > MTK_WED_V1)
developer8cb3ac72022-07-04 10:55:14 +0800777+ dev->mt76.q_rx[MT_RXQ_MAIN].flags = MT_WED_Q_RX(MT7915_RXQ_BAND0);
778+
779 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN],
780 MT_RXQ_ID(MT_RXQ_MAIN),
781 MT7915_RX_RING_SIZE,
developerf50c1802022-07-05 20:35:53 +0800782@@ -482,6 +488,10 @@ int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2)
developer8cb3ac72022-07-04 10:55:14 +0800783
784 if (dev->dbdc_support || dev->phy.band_idx) {
785 /* rx data queue for band1 */
developerf50c1802022-07-05 20:35:53 +0800786+ if (mtk_wed_device_active(&dev->mt76.mmio.wed) &&
787+ dev->mt76.mmio.wed.ver > MTK_WED_V1)
developer8cb3ac72022-07-04 10:55:14 +0800788+ dev->mt76.q_rx[MT_RXQ_EXT].flags = MT_WED_Q_RX(MT7915_RXQ_BAND1);
789+
790 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_EXT],
791 MT_RXQ_ID(MT_RXQ_EXT),
792 MT7915_RX_RING_SIZE,
793diff --git a/mt7915/mac.c b/mt7915/mac.c
developerd59e4772022-07-14 13:48:49 +0800794index db21d83e..1f8e1230 100644
developer8cb3ac72022-07-04 10:55:14 +0800795--- a/mt7915/mac.c
796+++ b/mt7915/mac.c
797@@ -217,7 +217,7 @@ static void mt7915_mac_sta_poll(struct mt7915_dev *dev)
798 }
799
800 static int
801-mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
802+mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb, enum mt76_rxq_id q, u32 info)
803 {
804 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
805 struct mt76_phy *mphy = &dev->mt76.phy;
developera3f86ed2022-07-08 14:15:13 +0800806@@ -234,7 +234,7 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
807 bool unicast, insert_ccmp_hdr = false;
808 u8 remove_pad, amsdu_info;
809 u8 mode = 0, qos_ctl = 0;
810- struct mt7915_sta *msta;
811+ struct mt7915_sta *msta = NULL;
812 bool hdr_trans;
813 u16 hdr_gap;
814 u16 seq_ctrl = 0;
developer8cb3ac72022-07-04 10:55:14 +0800815@@ -494,6 +494,27 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
816 #endif
817 } else {
818 status->flag |= RX_FLAG_8023;
developera3f86ed2022-07-08 14:15:13 +0800819+ if (msta && msta->vif) {
developer8cb3ac72022-07-04 10:55:14 +0800820+ struct mtk_wed_device *wed;
821+ int type;
822+
823+ wed = &dev->mt76.mmio.wed;
824+ type = FIELD_GET(MT_QFLAG_WED_TYPE, dev->mt76.q_rx[q].flags);
825+ if ((mtk_wed_device_active(wed) && type == MT76_WED_Q_RX) &&
developera3f86ed2022-07-08 14:15:13 +0800826+ (info & MT_DMA_INFO_PPE_VLD)) {
developer8cb3ac72022-07-04 10:55:14 +0800827+ struct ieee80211_vif *vif;
828+ u32 hash, reason;
829+
830+ vif = container_of((void *)msta->vif, struct ieee80211_vif,
developera3f86ed2022-07-08 14:15:13 +0800831+ drv_priv);
developer8cb3ac72022-07-04 10:55:14 +0800832+
833+ skb->dev = ieee80211_vif_to_netdev(vif);
834+ reason = FIELD_GET(MT_DMA_PPE_CPU_REASON, info);
835+ hash = FIELD_GET(MT_DMA_PPE_ENTRY, info);
836+
837+ mtk_wed_device_ppe_check(wed, skb, reason, hash);
838+ }
839+ }
840 }
841
842 if (rxv && mode >= MT_PHY_TYPE_HE_SU && !(status->flag & RX_FLAG_8023))
developera3f86ed2022-07-08 14:15:13 +0800843@@ -840,6 +861,80 @@ u32 mt7915_wed_init_buf(void *ptr, dma_addr_t phys, int token_id)
developer8cb3ac72022-07-04 10:55:14 +0800844 return MT_TXD_TXP_BUF_SIZE;
845 }
846
847+u32
848+mt7915_wed_init_rx_buf(struct mtk_wed_device *wed, int pkt_num)
849+{
850+ struct mtk_rxbm_desc *desc = wed->rx_buf_ring.desc;
851+ struct mt7915_dev *dev;
852+ dma_addr_t buf_phys;
853+ void *buf;
854+ int i, token, buf_size;
855+
856+ buf_size = SKB_DATA_ALIGN(NET_SKB_PAD + wed->wlan.rx_pkt_size) +
857+ SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
858+
859+ dev = container_of(wed, struct mt7915_dev, mt76.mmio.wed);
860+ for (i = 0; i < pkt_num; i++) {
861+ struct mt76_txwi_cache *r = mt76_get_rxwi(&dev->mt76);
862+
863+ buf = page_frag_alloc(&wed->rx_page, buf_size, GFP_ATOMIC);
864+ if (!buf)
865+ return -ENOMEM;
866+
867+ buf_phys = dma_map_single(dev->mt76.dma_dev, buf, wed->wlan.rx_pkt_size,
868+ DMA_TO_DEVICE);
869+
870+ if (unlikely(dma_mapping_error(dev->mt76.dev, buf_phys))) {
871+ skb_free_frag(buf);
872+ break;
873+ }
874+
875+ desc->buf0 = buf_phys;
876+
877+ token = mt76_rx_token_consume(&dev->mt76, buf, r, buf_phys);
878+
879+ desc->token |= FIELD_PREP(MT_DMA_CTL_TOKEN, token);
880+ desc++;
881+ }
882+
883+ return 0;
884+}
885+
886+void mt7915_wed_release_rx_buf(struct mtk_wed_device *wed)
887+{
888+ struct mt76_txwi_cache *rxwi;
889+ struct mt7915_dev *dev;
developera3f86ed2022-07-08 14:15:13 +0800890+ struct page *page;
developer8cb3ac72022-07-04 10:55:14 +0800891+ int token;
892+
893+ dev = container_of(wed, struct mt7915_dev, mt76.mmio.wed);
894+
895+ for(token = 0; token < dev->mt76.rx_token_size; token++) {
896+ rxwi = mt76_rx_token_release(&dev->mt76, token);
897+ if(!rxwi)
898+ continue;
899+
developera3f86ed2022-07-08 14:15:13 +0800900+ if(!rxwi->buf)
901+ continue;
902+
developer8cb3ac72022-07-04 10:55:14 +0800903+ dma_unmap_single(dev->mt76.dma_dev, rxwi->dma_addr,
904+ wed->wlan.rx_pkt_size, DMA_FROM_DEVICE);
905+ skb_free_frag(rxwi->buf);
906+ rxwi->buf = NULL;
907+
908+ mt76_put_rxwi(&dev->mt76, rxwi);
909+ }
developera3f86ed2022-07-08 14:15:13 +0800910+
911+ if (wed->rx_page.va)
912+ return;
913+
914+ page = virt_to_page(wed->rx_page.va);
915+ __page_frag_cache_drain(page, wed->rx_page.pagecnt_bias);
916+ memset(&wed->rx_page, 0, sizeof(wed->rx_page));
917+
developer8cb3ac72022-07-04 10:55:14 +0800918+ return;
919+}
920+
921 static void
922 mt7915_tx_check_aggr(struct ieee80211_sta *sta, __le32 *txwi)
923 {
developera3f86ed2022-07-08 14:15:13 +0800924@@ -1120,7 +1215,7 @@ bool mt7915_rx_check(struct mt76_dev *mdev, void *data, int len)
developer8cb3ac72022-07-04 10:55:14 +0800925 }
926
927 void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
928- struct sk_buff *skb)
929+ struct sk_buff *skb, u32 info)
930 {
931 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
932 __le32 *rxd = (__le32 *)skb->data;
developera3f86ed2022-07-08 14:15:13 +0800933@@ -1154,7 +1249,7 @@ void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
developer8cb3ac72022-07-04 10:55:14 +0800934 dev_kfree_skb(skb);
935 break;
936 case PKT_TYPE_NORMAL:
937- if (!mt7915_mac_fill_rx(dev, skb)) {
938+ if (!mt7915_mac_fill_rx(dev, skb, q, info)) {
939 mt76_rx(&dev->mt76, q, skb);
940 return;
941 }
942diff --git a/mt7915/mcu.c b/mt7915/mcu.c
developerd59e4772022-07-14 13:48:49 +0800943index 674cbc4e..0ae6daf3 100644
developer8cb3ac72022-07-04 10:55:14 +0800944--- a/mt7915/mcu.c
945+++ b/mt7915/mcu.c
developerd59e4772022-07-14 13:48:49 +0800946@@ -1723,6 +1723,7 @@ int mt7915_mcu_add_sta(struct mt7915_dev *dev, struct ieee80211_vif *vif,
developer8cb3ac72022-07-04 10:55:14 +0800947 struct ieee80211_sta *sta, bool enable)
948 {
949 struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv;
950+ struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
951 struct mt7915_sta *msta;
952 struct sk_buff *skb;
953 int ret;
developerd59e4772022-07-14 13:48:49 +0800954@@ -1775,6 +1776,8 @@ int mt7915_mcu_add_sta(struct mt7915_dev *dev, struct ieee80211_vif *vif,
developer8cb3ac72022-07-04 10:55:14 +0800955 return ret;
956 }
957 out:
developerf50c1802022-07-05 20:35:53 +0800958+ if (mtk_wed_device_active(wed) && wed->ver > MTK_WED_V1)
959+ mtk_wed_device_update_msg(wed, WED_WO_STA_REC, skb->data, skb->len);
developer8cb3ac72022-07-04 10:55:14 +0800960 return mt76_mcu_skb_send_msg(&dev->mt76, skb,
961 MCU_EXT_CMD(STA_REC_UPDATE), true);
962 }
963diff --git a/mt7915/mmio.c b/mt7915/mmio.c
developerd59e4772022-07-14 13:48:49 +0800964index b4a3120d..08ff556e 100644
developer8cb3ac72022-07-04 10:55:14 +0800965--- a/mt7915/mmio.c
966+++ b/mt7915/mmio.c
967@@ -28,6 +28,9 @@ static const u32 mt7915_reg[] = {
968 [FW_EXCEPTION_ADDR] = 0x219848,
969 [SWDEF_BASE_ADDR] = 0x41f200,
970 [EXCEPTION_BASE_ADDR] = 0x219848,
971+ [WED_TX_RING] = 0xd7300,
972+ [WED_RX_RING] = 0xd7410,
973+ [WED_RX_DATA_RING] = 0xd4500,
974 };
975
976 static const u32 mt7916_reg[] = {
977@@ -45,6 +48,9 @@ static const u32 mt7916_reg[] = {
978 [FW_EXCEPTION_ADDR] = 0x022050bc,
979 [SWDEF_BASE_ADDR] = 0x411400,
980 [EXCEPTION_BASE_ADDR] = 0x022050BC,
981+ [WED_TX_RING] = 0xd7300,
982+ [WED_RX_RING] = 0xd7410,
983+ [WED_RX_DATA_RING] = 0xd4540,
984 };
985
986 static const u32 mt7986_reg[] = {
987@@ -62,6 +68,9 @@ static const u32 mt7986_reg[] = {
988 [FW_EXCEPTION_ADDR] = 0x02204ffc,
989 [SWDEF_BASE_ADDR] = 0x411400,
990 [EXCEPTION_BASE_ADDR] = 0x02204FFC,
991+ [WED_TX_RING] = 0x24420,
992+ [WED_RX_RING] = 0x24520,
993+ [WED_RX_DATA_RING] = 0x24540,
994 };
995
996 static const u32 mt7915_offs[] = {
developerf50c1802022-07-05 20:35:53 +0800997@@ -710,6 +719,7 @@ mt7915_pci_wed_init(struct mt7915_dev *dev, struct device *pdev, int *irq)
998 wed->wlan.bus_type = MTK_BUS_TYPE_PCIE;
999 wed->wlan.wpdma_int = base + MT_INT_WED_SOURCE_CSR;
1000 wed->wlan.wpdma_mask = base + MT_INT_WED_MASK_CSR;
1001+ wed->wlan.wpdma_phys = base + MT_WFDMA_EXT_CSR_BASE;
1002 } else {
1003 struct platform_device *plat_dev;
1004 struct resource *res;
1005@@ -722,12 +732,19 @@ mt7915_pci_wed_init(struct mt7915_dev *dev, struct device *pdev, int *irq)
developer8cb3ac72022-07-04 10:55:14 +08001006 wed->wlan.wpdma_int = base + MT_INT_SOURCE_CSR;
1007 wed->wlan.wpdma_mask = base + MT_INT_MASK_CSR;
1008 }
1009+ wed->wlan.rx_pkt = MT7915_WED_RX_TOKEN_SIZE;
1010+ wed->wlan.phy_base = base;
1011 wed->wlan.wpdma_tx = base + MT_TXQ_WED_RING_BASE;
1012 wed->wlan.wpdma_txfree = base + MT_RXQ_WED_RING_BASE;
1013+ wed->wlan.wpdma_rx_glo = base + MT_WPDMA_GLO_CFG;
1014+ wed->wlan.wpdma_rx = base + MT_RXQ_WED_DATA_RING_BASE;
1015
1016 wed->wlan.tx_tbit[0] = MT_WED_TX_DONE_BAND0;
1017 wed->wlan.tx_tbit[1] = MT_WED_TX_DONE_BAND1;
1018 wed->wlan.txfree_tbit = MT_WED_TX_FREE_DONE;
1019+ wed->wlan.rx_tbit[0] = MT_WED_RX_DONE_BAND0;
1020+ wed->wlan.rx_tbit[1] = MT_WED_RX_DONE_BAND1;
1021+
1022 wed->wlan.nbuf = 7168;
1023 wed->wlan.token_start = MT7915_TOKEN_SIZE - wed->wlan.nbuf;
1024 wed->wlan.init_buf = mt7915_wed_init_buf;
developerf50c1802022-07-05 20:35:53 +08001025@@ -735,12 +752,15 @@ mt7915_pci_wed_init(struct mt7915_dev *dev, struct device *pdev, int *irq)
developer8cb3ac72022-07-04 10:55:14 +08001026 wed->wlan.offload_enable = mt7915_wed_offload_enable;
1027 wed->wlan.offload_disable = mt7915_wed_offload_disable;
1028
1029+ wed->wlan.rx_nbuf = 65536;
1030+ wed->wlan.rx_pkt_size = MTK_WED_RX_PKT_SIZE;
1031+ wed->wlan.init_rx_buf = mt7915_wed_init_rx_buf;
1032+ wed->wlan.release_rx_buf = mt7915_wed_release_rx_buf;
1033+
1034+ dev->mt76.rx_token_size = wed->wlan.rx_pkt + MT7915_RX_RING_SIZE * 2;
1035 if (mtk_wed_device_attach(wed) != 0)
1036 return 0;
1037
developerf50c1802022-07-05 20:35:53 +08001038- if (wed->ver == MTK_WED_V1)
1039- wed->wlan.wpdma_phys = base + MT_WFDMA_EXT_CSR_BASE;
1040-
1041 *irq = wed->irq;
1042 dev->mt76.dma_dev = wed->dev;
1043 mdev->token_size = wed->wlan.token_start;
developer8cb3ac72022-07-04 10:55:14 +08001044diff --git a/mt7915/mt7915.h b/mt7915/mt7915.h
developerd59e4772022-07-14 13:48:49 +08001045index 39127922..22399cc7 100644
developer8cb3ac72022-07-04 10:55:14 +08001046--- a/mt7915/mt7915.h
1047+++ b/mt7915/mt7915.h
developerd59e4772022-07-14 13:48:49 +08001048@@ -78,6 +78,7 @@
developer8cb3ac72022-07-04 10:55:14 +08001049 #define MT7915_MAX_STA_TWT_AGRT 8
1050 #define MT7915_MIN_TWT_DUR 64
1051 #define MT7915_MAX_QUEUE (__MT_RXQ_MAX + __MT_MCUQ_MAX + 2)
1052+#define MT7915_WED_RX_TOKEN_SIZE 12288
1053
1054 struct mt7915_vif;
1055 struct mt7915_sta;
developerd59e4772022-07-14 13:48:49 +08001056@@ -541,7 +542,9 @@ void mt7915_wfsys_reset(struct mt7915_dev *dev);
developer8cb3ac72022-07-04 10:55:14 +08001057 irqreturn_t mt7915_irq_handler(int irq, void *dev_instance);
1058 u64 __mt7915_get_tsf(struct ieee80211_hw *hw, struct mt7915_vif *mvif);
1059 u32 mt7915_wed_init_buf(void *ptr, dma_addr_t phys, int token_id);
1060-
1061+u32 mt7915_wed_init_rx_buf(struct mtk_wed_device *wed,
1062+ int pkt_num);
1063+void mt7915_wed_release_rx_buf(struct mtk_wed_device *wed);
1064 int mt7915_register_device(struct mt7915_dev *dev);
1065 void mt7915_unregister_device(struct mt7915_dev *dev);
1066 int mt7915_eeprom_init(struct mt7915_dev *dev);
developerd59e4772022-07-14 13:48:49 +08001067@@ -693,7 +696,7 @@ int mt7915_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
developer8cb3ac72022-07-04 10:55:14 +08001068 struct mt76_tx_info *tx_info);
1069 void mt7915_tx_token_put(struct mt7915_dev *dev);
1070 void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1071- struct sk_buff *skb);
1072+ struct sk_buff *skb, u32 info);
1073 bool mt7915_rx_check(struct mt76_dev *mdev, void *data, int len);
1074 void mt7915_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps);
1075 void mt7915_stats_work(struct work_struct *work);
1076diff --git a/mt7915/regs.h b/mt7915/regs.h
developerd59e4772022-07-14 13:48:49 +08001077index ffda5f6b..08bf84ce 100644
developer8cb3ac72022-07-04 10:55:14 +08001078--- a/mt7915/regs.h
1079+++ b/mt7915/regs.h
1080@@ -33,6 +33,9 @@ enum reg_rev {
1081 FW_EXCEPTION_ADDR,
1082 SWDEF_BASE_ADDR,
1083 EXCEPTION_BASE_ADDR,
1084+ WED_TX_RING,
1085+ WED_RX_RING,
1086+ WED_RX_DATA_RING,
1087 __MT_REG_MAX,
1088 };
1089
1090@@ -570,9 +573,13 @@ enum offs_rev {
1091 #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2 BIT(21)
1092
1093 #define MT_WFDMA0_RST_DTX_PTR MT_WFDMA0(0x20c)
1094+#define MT_WFDMA0_EXT0_CFG MT_WFDMA0(0x2b0)
1095+#define MT_WFDMA0_EXT0_RXWB_KEEP BIT(10)
1096+
1097 #define MT_WFDMA0_PRI_DLY_INT_CFG0 MT_WFDMA0(0x2f0)
1098 #define MT_WFDMA0_PRI_DLY_INT_CFG1 MT_WFDMA0(0x2f4)
1099 #define MT_WFDMA0_PRI_DLY_INT_CFG2 MT_WFDMA0(0x2f8)
1100+#define MT_WPDMA_GLO_CFG MT_WFDMA0(0x208)
1101
1102 #define MT_WFDMA0_MCU_HOST_INT_ENA MT_WFDMA0(0x1f4)
1103 #define MT_WFDMA0_MT_WA_WDT_INT BIT(31)
1104@@ -670,12 +677,15 @@ enum offs_rev {
1105 #define MT_TXQ_EXT_CTRL(q) (MT_Q_BASE(__TXQ(q)) + 0x600 + \
1106 MT_TXQ_ID(q)* 0x4)
1107
1108-#define MT_TXQ_WED_RING_BASE (!is_mt7986(mdev)? 0xd7300 : 0x24420)
1109-#define MT_RXQ_WED_RING_BASE (!is_mt7986(mdev)? 0xd7410 : 0x24520)
1110+#define MT_TXQ_WED_RING_BASE __REG(WED_TX_RING)
1111+#define MT_RXQ_WED_RING_BASE __REG(WED_RX_RING)
1112+#define MT_RXQ_WED_DATA_RING_BASE __REG(WED_RX_DATA_RING)
1113
1114 #define MT_WED_TX_DONE_BAND0 (is_mt7915(mdev)? 4 : 30)
1115 #define MT_WED_TX_DONE_BAND1 (is_mt7915(mdev)? 5 : 31)
1116 #define MT_WED_TX_FREE_DONE (is_mt7915(mdev)? 1 : 2)
1117+#define MT_WED_RX_DONE_BAND0 (is_mt7915(mdev)? 16 : 22)
1118+#define MT_WED_RX_DONE_BAND1 (is_mt7915(mdev)? 17 : 23)
1119
1120 #define MT_INT_SOURCE_CSR __REG(INT_SOURCE_CSR)
1121 #define MT_INT_MASK_CSR __REG(INT_MASK_CSR)
1122diff --git a/mt7921/mac.c b/mt7921/mac.c
developerd59e4772022-07-14 13:48:49 +08001123index 4fcadf86..4897940b 100644
developer8cb3ac72022-07-04 10:55:14 +08001124--- a/mt7921/mac.c
1125+++ b/mt7921/mac.c
1126@@ -555,7 +555,7 @@ out:
1127 EXPORT_SYMBOL_GPL(mt7921_mac_add_txs);
1128
1129 void mt7921_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1130- struct sk_buff *skb)
1131+ struct sk_buff *skb, u32 info)
1132 {
1133 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
1134 __le32 *rxd = (__le32 *)skb->data;
1135diff --git a/mt7921/mt7921.h b/mt7921/mt7921.h
developerd59e4772022-07-14 13:48:49 +08001136index efeb82cb..4b2e974b 100644
developer8cb3ac72022-07-04 10:55:14 +08001137--- a/mt7921/mt7921.h
1138+++ b/mt7921/mt7921.h
1139@@ -388,7 +388,7 @@ int mt7921e_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
1140 void mt7921_tx_worker(struct mt76_worker *w);
1141 void mt7921_tx_token_put(struct mt7921_dev *dev);
1142 void mt7921_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1143- struct sk_buff *skb);
1144+ struct sk_buff *skb, u32 info);
1145 void mt7921_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps);
1146 void mt7921_stats_work(struct work_struct *work);
1147 void mt7921_set_stream_he_caps(struct mt7921_phy *phy);
1148@@ -424,7 +424,7 @@ int mt7921_mcu_parse_response(struct mt76_dev *mdev, int cmd,
1149
1150 bool mt7921e_rx_check(struct mt76_dev *mdev, void *data, int len);
1151 void mt7921e_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1152- struct sk_buff *skb);
1153+ struct sk_buff *skb, u32 info);
1154 int mt7921e_driver_own(struct mt7921_dev *dev);
1155 int mt7921e_mac_reset(struct mt7921_dev *dev);
1156 int mt7921e_mcu_init(struct mt7921_dev *dev);
1157diff --git a/mt7921/pci_mac.c b/mt7921/pci_mac.c
developerd59e4772022-07-14 13:48:49 +08001158index e1800674..ca982eb5 100644
developer8cb3ac72022-07-04 10:55:14 +08001159--- a/mt7921/pci_mac.c
1160+++ b/mt7921/pci_mac.c
1161@@ -182,7 +182,7 @@ bool mt7921e_rx_check(struct mt76_dev *mdev, void *data, int len)
1162 }
1163
1164 void mt7921e_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1165- struct sk_buff *skb)
1166+ struct sk_buff *skb, u32 info)
1167 {
1168 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
1169 __le32 *rxd = (__le32 *)skb->data;
1170@@ -196,7 +196,7 @@ void mt7921e_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1171 napi_consume_skb(skb, 1);
1172 break;
1173 default:
1174- mt7921_queue_rx_skb(mdev, q, skb);
1175+ mt7921_queue_rx_skb(mdev, q, skb, info);
1176 break;
1177 }
1178 }
1179diff --git a/tx.c b/tx.c
developerd59e4772022-07-14 13:48:49 +08001180index ae44afe0..bccd206e 100644
developer8cb3ac72022-07-04 10:55:14 +08001181--- a/tx.c
1182+++ b/tx.c
developerf50c1802022-07-05 20:35:53 +08001183@@ -767,3 +767,37 @@ mt76_token_release(struct mt76_dev *dev, int token, bool *wake)
developer8cb3ac72022-07-04 10:55:14 +08001184 return txwi;
1185 }
1186 EXPORT_SYMBOL_GPL(mt76_token_release);
1187+
1188+int mt76_rx_token_consume(struct mt76_dev *dev, void *ptr,
1189+ struct mt76_txwi_cache *r, dma_addr_t phys)
1190+{
1191+ int token;
1192+
1193+ spin_lock_bh(&dev->rx_token_lock);
1194+
1195+ token = idr_alloc(&dev->rx_token, r, 0, dev->rx_token_size, GFP_ATOMIC);
1196+
1197+ spin_unlock_bh(&dev->rx_token_lock);
1198+
1199+ r->buf = ptr;
1200+ r->dma_addr = phys;
1201+
1202+ return token;
1203+}
1204+EXPORT_SYMBOL_GPL(mt76_rx_token_consume);
1205+
1206+struct mt76_txwi_cache *
1207+mt76_rx_token_release(struct mt76_dev *dev, int token)
1208+{
1209+
1210+ struct mt76_txwi_cache *rxwi;
1211+
1212+ spin_lock_bh(&dev->rx_token_lock);
1213+
1214+ rxwi = idr_remove(&dev->rx_token, token);
1215+
1216+ spin_unlock_bh(&dev->rx_token_lock);
1217+
1218+ return rxwi;
1219+}
1220+EXPORT_SYMBOL_GPL(mt76_rx_token_release);
1221--
developerd59e4772022-07-14 13:48:49 +080012222.25.1
developer8cb3ac72022-07-04 10:55:14 +08001223