blob: 7040ca6dd029a401099782bc01eb7508b8428fd5 [file] [log] [blame]
developerf50c1802022-07-05 20:35:53 +08001From 1abac441c94f3f32bd074b8b01c439263129102d Mon Sep 17 00:00:00 2001
developer8cb3ac72022-07-04 10:55:14 +08002From: Sujuan Chen <sujuan.chen@mediatek.com>
developerf50c1802022-07-05 20:35:53 +08003Date: Tue, 5 Jul 2022 19:42:55 +0800
developer8cb3ac72022-07-04 10:55:14 +08004Subject: [PATCH 2/3] mt76 add wed rx support
5
6Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
7---
developera3f86ed2022-07-08 14:15:13 +08008 dma.c | 248 +++++++++++++++++++++++++++++++++--------
developerf50c1802022-07-05 20:35:53 +08009 dma.h | 10 ++
developer8cb3ac72022-07-04 10:55:14 +080010 mac80211.c | 8 +-
developera3f86ed2022-07-08 14:15:13 +080011 mt76.h | 24 +++-
developer8cb3ac72022-07-04 10:55:14 +080012 mt7603/dma.c | 2 +-
13 mt7603/mt7603.h | 2 +-
14 mt7615/mac.c | 2 +-
15 mt7615/mt7615.h | 2 +-
developerf50c1802022-07-05 20:35:53 +080016 mt76_connac_mcu.c | 9 ++
developer8cb3ac72022-07-04 10:55:14 +080017 mt76x02.h | 2 +-
18 mt76x02_txrx.c | 2 +-
developerf50c1802022-07-05 20:35:53 +080019 mt7915/dma.c | 10 ++
developera3f86ed2022-07-08 14:15:13 +080020 mt7915/mac.c | 101 ++++++++++++++++-
developerf50c1802022-07-05 20:35:53 +080021 mt7915/mcu.c | 3 +
22 mt7915/mmio.c | 26 ++++-
developer8cb3ac72022-07-04 10:55:14 +080023 mt7915/mt7915.h | 7 +-
24 mt7915/regs.h | 14 ++-
25 mt7921/mac.c | 2 +-
26 mt7921/mt7921.h | 4 +-
27 mt7921/pci_mac.c | 4 +-
developera3f86ed2022-07-08 14:15:13 +080028 tx.c | 34 ++++++
29 21 files changed, 448 insertions(+), 68 deletions(-)
developer8cb3ac72022-07-04 10:55:14 +080030
31diff --git a/dma.c b/dma.c
developera3f86ed2022-07-08 14:15:13 +080032index 03ee910..e46dbed 100644
developer8cb3ac72022-07-04 10:55:14 +080033--- a/dma.c
34+++ b/dma.c
35@@ -98,6 +98,63 @@ mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t)
36 }
37 EXPORT_SYMBOL_GPL(mt76_put_txwi);
38
39+static struct mt76_txwi_cache *
40+mt76_alloc_rxwi(struct mt76_dev *dev)
41+{
42+ struct mt76_txwi_cache *r;
43+ int size;
44+
45+ size = L1_CACHE_ALIGN(sizeof(*r));
46+ r = kzalloc(size, GFP_ATOMIC);
47+ if (!r)
48+ return NULL;
49+
50+ r->buf = NULL;
51+
52+ return r;
53+}
54+
55+static struct mt76_txwi_cache *
56+__mt76_get_rxwi(struct mt76_dev *dev)
57+{
58+ struct mt76_txwi_cache *r = NULL;
59+
60+ spin_lock(&dev->wed_lock);
61+ if (!list_empty(&dev->rxwi_cache)) {
62+ r = list_first_entry(&dev->rxwi_cache, struct mt76_txwi_cache,
63+ list);
64+ if(r)
65+ list_del(&r->list);
66+ }
67+ spin_unlock(&dev->wed_lock);
68+
69+ return r;
70+}
71+
72+struct mt76_txwi_cache *
73+mt76_get_rxwi(struct mt76_dev *dev)
74+{
75+ struct mt76_txwi_cache *r = __mt76_get_rxwi(dev);
76+
77+ if (r)
78+ return r;
79+
80+ return mt76_alloc_rxwi(dev);
81+}
82+EXPORT_SYMBOL_GPL(mt76_get_rxwi);
83+
84+void
85+mt76_put_rxwi(struct mt76_dev *dev, struct mt76_txwi_cache *r)
86+{
87+ if (!r)
88+ return;
89+
90+ spin_lock(&dev->wed_lock);
91+ list_add(&r->list, &dev->rxwi_cache);
92+ spin_unlock(&dev->wed_lock);
93+}
94+EXPORT_SYMBOL_GPL(mt76_put_rxwi);
95+
96 static void
97 mt76_free_pending_txwi(struct mt76_dev *dev)
98 {
developera3f86ed2022-07-08 14:15:13 +080099@@ -112,6 +169,21 @@ mt76_free_pending_txwi(struct mt76_dev *dev)
100 local_bh_enable();
101 }
102
103+static void
104+mt76_free_pending_rxwi(struct mt76_dev *dev)
105+{
106+ struct mt76_txwi_cache *r;
107+
108+ local_bh_disable();
109+ while ((r = __mt76_get_rxwi(dev)) != NULL) {
110+ if (r->buf)
111+ skb_free_frag(r->buf);
112+
113+ kfree(r);
114+ }
115+ local_bh_enable();
116+}
117+
118 static void
119 mt76_dma_sync_idx(struct mt76_dev *dev, struct mt76_queue *q)
120 {
121@@ -141,12 +213,15 @@ mt76_dma_queue_reset(struct mt76_dev *dev, struct mt76_queue *q)
developer8cb3ac72022-07-04 10:55:14 +0800122 static int
123 mt76_dma_add_buf(struct mt76_dev *dev, struct mt76_queue *q,
124 struct mt76_queue_buf *buf, int nbufs, u32 info,
125- struct sk_buff *skb, void *txwi)
126+ struct sk_buff *skb, void *txwi, void *rxwi)
127 {
128+ struct mtk_wed_device *wed = &dev->mmio.wed;
129+
130 struct mt76_queue_entry *entry;
131 struct mt76_desc *desc;
132 u32 ctrl;
133 int i, idx = -1;
134+ int type;
135
136 if (txwi) {
137 q->entry[q->head].txwi = DMA_DUMMY_DATA;
developera3f86ed2022-07-08 14:15:13 +0800138@@ -162,28 +237,42 @@ mt76_dma_add_buf(struct mt76_dev *dev, struct mt76_queue *q,
developer8cb3ac72022-07-04 10:55:14 +0800139 desc = &q->desc[idx];
140 entry = &q->entry[idx];
141
142- if (buf[0].skip_unmap)
143- entry->skip_buf0 = true;
144- entry->skip_buf1 = i == nbufs - 1;
145-
146- entry->dma_addr[0] = buf[0].addr;
147- entry->dma_len[0] = buf[0].len;
148-
149- ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, buf[0].len);
150- if (i < nbufs - 1) {
151- entry->dma_addr[1] = buf[1].addr;
152- entry->dma_len[1] = buf[1].len;
153- buf1 = buf[1].addr;
154- ctrl |= FIELD_PREP(MT_DMA_CTL_SD_LEN1, buf[1].len);
155- if (buf[1].skip_unmap)
156- entry->skip_buf1 = true;
157+ type = FIELD_GET(MT_QFLAG_WED_TYPE, q->flags);
158+ if (mtk_wed_device_active(wed) && type == MT76_WED_Q_RX) {
159+ struct mt76_txwi_cache *r = rxwi;
160+ int rx_token;
161+
162+ if (!r)
163+ return -ENOMEM;
164+
165+ rx_token = mt76_rx_token_consume(dev, (void *)skb, r, buf[0].addr);
166+
167+ buf1 |= FIELD_PREP(MT_DMA_CTL_TOKEN, rx_token);
168+ ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, MTK_WED_RX_PKT_SIZE);
169+ ctrl |= MT_DMA_CTL_TO_HOST;
170+ } else {
171+ if (buf[0].skip_unmap)
172+ entry->skip_buf0 = true;
173+ entry->skip_buf1 = i == nbufs - 1;
174+
175+ entry->dma_addr[0] = buf[0].addr;
176+ entry->dma_len[0] = buf[0].len;
177+
178+ ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, buf[0].len);
179+ if (i < nbufs - 1) {
180+ entry->dma_addr[1] = buf[1].addr;
181+ entry->dma_len[1] = buf[1].len;
182+ buf1 = buf[1].addr;
183+ ctrl |= FIELD_PREP(MT_DMA_CTL_SD_LEN1, buf[1].len);
184+ if (buf[1].skip_unmap)
185+ entry->skip_buf1 = true;
186+ }
187+ if (i == nbufs - 1)
188+ ctrl |= MT_DMA_CTL_LAST_SEC0;
189+ else if (i == nbufs - 2)
190+ ctrl |= MT_DMA_CTL_LAST_SEC1;
191 }
192
193- if (i == nbufs - 1)
194- ctrl |= MT_DMA_CTL_LAST_SEC0;
195- else if (i == nbufs - 2)
196- ctrl |= MT_DMA_CTL_LAST_SEC1;
197-
198 WRITE_ONCE(desc->buf0, cpu_to_le32(buf0));
199 WRITE_ONCE(desc->buf1, cpu_to_le32(buf1));
200 WRITE_ONCE(desc->info, cpu_to_le32(info));
developera3f86ed2022-07-08 14:15:13 +0800201@@ -272,33 +361,63 @@ mt76_dma_tx_cleanup(struct mt76_dev *dev, struct mt76_queue *q, bool flush)
developer8cb3ac72022-07-04 10:55:14 +0800202
203 static void *
204 mt76_dma_get_buf(struct mt76_dev *dev, struct mt76_queue *q, int idx,
205- int *len, u32 *info, bool *more)
206+ int *len, u32 *info, bool *more, bool *drop)
207 {
208 struct mt76_queue_entry *e = &q->entry[idx];
209 struct mt76_desc *desc = &q->desc[idx];
210 dma_addr_t buf_addr;
211 void *buf = e->buf;
212 int buf_len = SKB_WITH_OVERHEAD(q->buf_size);
213+ struct mtk_wed_device *wed = &dev->mmio.wed;
214+ int type;
215
216- buf_addr = e->dma_addr[0];
217 if (len) {
218 u32 ctl = le32_to_cpu(READ_ONCE(desc->ctrl));
219 *len = FIELD_GET(MT_DMA_CTL_SD_LEN0, ctl);
220 *more = !(ctl & MT_DMA_CTL_LAST_SEC0);
221 }
222
223- if (info)
224- *info = le32_to_cpu(desc->info);
225+ type = FIELD_GET(MT_QFLAG_WED_TYPE, q->flags);
226+ if (mtk_wed_device_active(wed) && type == MT76_WED_Q_RX) {
227+ u32 token;
228+ struct mt76_txwi_cache *r;
229+
230+ token = FIELD_GET(MT_DMA_CTL_TOKEN, desc->buf1);
231+
232+ r = mt76_rx_token_release(dev, token);
233+ if (!r)
234+ return NULL;
235+
236+ buf = page_frag_alloc(&q->rx_page, q->buf_size, GFP_ATOMIC);
237+ if (!buf)
238+ return NULL;
239+
240+ memcpy(buf, r->buf, MTK_WED_RX_PKT_SIZE);
241+ buf_addr = r->dma_addr;
242+ buf_len = MTK_WED_RX_PKT_SIZE;
243+ r->dma_addr = 0;
244+ //r->buf = NULL;
245+
246+ mt76_put_rxwi(dev, r);
247+
248+ if (desc->ctrl & (MT_DMA_CTL_TO_HOST_A | MT_DMA_CTL_DROP))
249+ *drop = true;
250+ } else {
251+ buf_addr = e->dma_addr[0];
252+ e->buf = NULL;
253+ }
254
255 dma_unmap_single(dev->dma_dev, buf_addr, buf_len, DMA_FROM_DEVICE);
256- e->buf = NULL;
257+
258+ if (info)
259+ *info = le32_to_cpu(desc->info);
260
261 return buf;
262 }
263
264 static void *
265 mt76_dma_dequeue(struct mt76_dev *dev, struct mt76_queue *q, bool flush,
266- int *len, u32 *info, bool *more)
267+ int *len, u32 *info, bool *more, bool *drop)
268 {
269 int idx = q->tail;
270
developera3f86ed2022-07-08 14:15:13 +0800271@@ -314,7 +433,7 @@ mt76_dma_dequeue(struct mt76_dev *dev, struct mt76_queue *q, bool flush,
developer8cb3ac72022-07-04 10:55:14 +0800272 q->tail = (q->tail + 1) % q->ndesc;
273 q->queued--;
274
275- return mt76_dma_get_buf(dev, q, idx, len, info, more);
276+ return mt76_dma_get_buf(dev, q, idx, len, info, more, drop);
277 }
278
279 static int
developera3f86ed2022-07-08 14:15:13 +0800280@@ -336,7 +455,7 @@ mt76_dma_tx_queue_skb_raw(struct mt76_dev *dev, struct mt76_queue *q,
developer8cb3ac72022-07-04 10:55:14 +0800281 buf.len = skb->len;
282
283 spin_lock_bh(&q->lock);
284- mt76_dma_add_buf(dev, q, &buf, 1, tx_info, skb, NULL);
285+ mt76_dma_add_buf(dev, q, &buf, 1, tx_info, skb, NULL, NULL);
286 mt76_dma_kick_queue(dev, q);
287 spin_unlock_bh(&q->lock);
288
developera3f86ed2022-07-08 14:15:13 +0800289@@ -413,7 +532,7 @@ mt76_dma_tx_queue_skb(struct mt76_dev *dev, struct mt76_queue *q,
developer8cb3ac72022-07-04 10:55:14 +0800290 goto unmap;
291
292 return mt76_dma_add_buf(dev, q, tx_info.buf, tx_info.nbuf,
293- tx_info.info, tx_info.skb, t);
294+ tx_info.info, tx_info.skb, t, NULL);
295
296 unmap:
297 for (n--; n > 0; n--)
developera3f86ed2022-07-08 14:15:13 +0800298@@ -448,6 +567,8 @@ mt76_dma_rx_fill(struct mt76_dev *dev, struct mt76_queue *q)
developer8cb3ac72022-07-04 10:55:14 +0800299 int frames = 0;
300 int len = SKB_WITH_OVERHEAD(q->buf_size);
301 int offset = q->buf_offset;
302+ struct mtk_wed_device *wed = &dev->mmio.wed;
developera3f86ed2022-07-08 14:15:13 +0800303+ struct page_frag_cache *rx_page;
developer8cb3ac72022-07-04 10:55:14 +0800304
305 if (!q->ndesc)
306 return 0;
developera3f86ed2022-07-08 14:15:13 +0800307@@ -456,10 +577,29 @@ mt76_dma_rx_fill(struct mt76_dev *dev, struct mt76_queue *q)
developer8cb3ac72022-07-04 10:55:14 +0800308
309 while (q->queued < q->ndesc - 1) {
310 struct mt76_queue_buf qbuf;
311+ int type = FIELD_GET(MT_QFLAG_WED_TYPE, q->flags);
312+ bool skip_alloc = false;
313+ struct mt76_txwi_cache *r = NULL;
314+
developera3f86ed2022-07-08 14:15:13 +0800315+ rx_page = &q->rx_page;
developer8cb3ac72022-07-04 10:55:14 +0800316+ if (mtk_wed_device_active(wed) && type == MT76_WED_Q_RX) {
developera3f86ed2022-07-08 14:15:13 +0800317+ rx_page = &wed->rx_page;
developer8cb3ac72022-07-04 10:55:14 +0800318+ r = mt76_get_rxwi(dev);
319+ if (!r)
320+ return -ENOMEM;
321+
322+ if (r->buf) {
323+ skip_alloc = true;
324+ len = MTK_WED_RX_PKT_SIZE;
325+ buf = r->buf;
326+ }
327+ }
328
329- buf = page_frag_alloc(&q->rx_page, q->buf_size, GFP_ATOMIC);
330- if (!buf)
331- break;
332+ if (!skip_alloc) {
developera3f86ed2022-07-08 14:15:13 +0800333+ buf = page_frag_alloc(rx_page, q->buf_size, GFP_ATOMIC);
developer8cb3ac72022-07-04 10:55:14 +0800334+ if (!buf)
335+ break;
336+ }
337
338 addr = dma_map_single(dev->dma_dev, buf, len, DMA_FROM_DEVICE);
339 if (unlikely(dma_mapping_error(dev->dma_dev, addr))) {
developera3f86ed2022-07-08 14:15:13 +0800340@@ -470,7 +610,7 @@ mt76_dma_rx_fill(struct mt76_dev *dev, struct mt76_queue *q)
developer8cb3ac72022-07-04 10:55:14 +0800341 qbuf.addr = addr + offset;
342 qbuf.len = len - offset;
343 qbuf.skip_unmap = false;
344- mt76_dma_add_buf(dev, q, &qbuf, 1, 0, buf, NULL);
345+ mt76_dma_add_buf(dev, q, &qbuf, 1, 0, buf, NULL, r);
346 frames++;
347 }
348
developera3f86ed2022-07-08 14:15:13 +0800349@@ -516,6 +656,11 @@ mt76_dma_wed_setup(struct mt76_dev *dev, struct mt76_queue *q)
developer8cb3ac72022-07-04 10:55:14 +0800350 if (!ret)
351 q->wed_regs = wed->txfree_ring.reg_base;
352 break;
353+ case MT76_WED_Q_RX:
354+ ret = mtk_wed_device_rx_ring_setup(wed, ring, q->regs);
355+ if (!ret)
356+ q->wed_regs = wed->rx_ring[ring].reg_base;
357+ break;
358 default:
359 ret = -EINVAL;
360 }
developera3f86ed2022-07-08 14:15:13 +0800361@@ -531,7 +676,8 @@ mt76_dma_alloc_queue(struct mt76_dev *dev, struct mt76_queue *q,
developer8cb3ac72022-07-04 10:55:14 +0800362 int idx, int n_desc, int bufsize,
363 u32 ring_base)
364 {
365- int ret, size;
366+ int ret, size, type;
367+ struct mtk_wed_device *wed = &dev->mmio.wed;
368
369 spin_lock_init(&q->lock);
370 spin_lock_init(&q->cleanup_lock);
developera3f86ed2022-07-08 14:15:13 +0800371@@ -541,6 +687,11 @@ mt76_dma_alloc_queue(struct mt76_dev *dev, struct mt76_queue *q,
developer8cb3ac72022-07-04 10:55:14 +0800372 q->buf_size = bufsize;
373 q->hw_idx = idx;
374
375+ type = FIELD_GET(MT_QFLAG_WED_TYPE, q->flags);
376+ if (mtk_wed_device_active(wed) && type == MT76_WED_Q_RX)
377+ q->buf_size = SKB_DATA_ALIGN(NET_SKB_PAD + MTK_WED_RX_PKT_SIZE) +
378+ SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
379+
380 size = q->ndesc * sizeof(struct mt76_desc);
381 q->desc = dmam_alloc_coherent(dev->dma_dev, size, &q->desc_dma, GFP_KERNEL);
382 if (!q->desc)
developera3f86ed2022-07-08 14:15:13 +0800383@@ -573,7 +724,7 @@ mt76_dma_rx_cleanup(struct mt76_dev *dev, struct mt76_queue *q)
developer8cb3ac72022-07-04 10:55:14 +0800384
385 spin_lock_bh(&q->lock);
386 do {
387- buf = mt76_dma_dequeue(dev, q, true, NULL, NULL, &more);
388+ buf = mt76_dma_dequeue(dev, q, true, NULL, NULL, &more, NULL);
389 if (!buf)
390 break;
391
developera3f86ed2022-07-08 14:15:13 +0800392@@ -614,7 +765,7 @@ mt76_dma_rx_reset(struct mt76_dev *dev, enum mt76_rxq_id qid)
developer8cb3ac72022-07-04 10:55:14 +0800393
394 static void
395 mt76_add_fragment(struct mt76_dev *dev, struct mt76_queue *q, void *data,
396- int len, bool more)
397+ int len, bool more, u32 info)
398 {
399 struct sk_buff *skb = q->rx_head;
400 struct skb_shared_info *shinfo = skb_shinfo(skb);
developera3f86ed2022-07-08 14:15:13 +0800401@@ -634,7 +785,7 @@ mt76_add_fragment(struct mt76_dev *dev, struct mt76_queue *q, void *data,
developer8cb3ac72022-07-04 10:55:14 +0800402
403 q->rx_head = NULL;
404 if (nr_frags < ARRAY_SIZE(shinfo->frags))
405- dev->drv->rx_skb(dev, q - dev->q_rx, skb);
406+ dev->drv->rx_skb(dev, q - dev->q_rx, skb, info);
407 else
408 dev_kfree_skb(skb);
409 }
developera3f86ed2022-07-08 14:15:13 +0800410@@ -655,6 +806,7 @@ mt76_dma_rx_process(struct mt76_dev *dev, struct mt76_queue *q, int budget)
developer8cb3ac72022-07-04 10:55:14 +0800411 }
412
413 while (done < budget) {
414+ bool drop = false;
415 u32 info;
416
417 if (check_ddone) {
developera3f86ed2022-07-08 14:15:13 +0800418@@ -665,10 +817,13 @@ mt76_dma_rx_process(struct mt76_dev *dev, struct mt76_queue *q, int budget)
developer8cb3ac72022-07-04 10:55:14 +0800419 break;
420 }
421
422- data = mt76_dma_dequeue(dev, q, false, &len, &info, &more);
423+ data = mt76_dma_dequeue(dev, q, false, &len, &info, &more, &drop);
424 if (!data)
425 break;
426
427+ if (drop)
428+ goto free_frag;
429+
430 if (q->rx_head)
431 data_len = q->buf_size;
432 else
developera3f86ed2022-07-08 14:15:13 +0800433@@ -681,7 +836,7 @@ mt76_dma_rx_process(struct mt76_dev *dev, struct mt76_queue *q, int budget)
developer8cb3ac72022-07-04 10:55:14 +0800434 }
435
436 if (q->rx_head) {
437- mt76_add_fragment(dev, q, data, len, more);
438+ mt76_add_fragment(dev, q, data, len, more, info);
439 continue;
440 }
441
developera3f86ed2022-07-08 14:15:13 +0800442@@ -708,7 +863,7 @@ mt76_dma_rx_process(struct mt76_dev *dev, struct mt76_queue *q, int budget)
developer8cb3ac72022-07-04 10:55:14 +0800443 continue;
444 }
445
446- dev->drv->rx_skb(dev, q - dev->q_rx, skb);
447+ dev->drv->rx_skb(dev, q - dev->q_rx, skb, info);
448 continue;
449
450 free_frag:
developera3f86ed2022-07-08 14:15:13 +0800451@@ -785,8 +940,8 @@ EXPORT_SYMBOL_GPL(mt76_dma_attach);
452
453 void mt76_dma_cleanup(struct mt76_dev *dev)
454 {
455- int i;
456-
457+ int i, type;
458+
459 mt76_worker_disable(&dev->tx_worker);
460 netif_napi_del(&dev->tx_napi);
461
462@@ -801,12 +956,17 @@ void mt76_dma_cleanup(struct mt76_dev *dev)
463
464 mt76_for_each_q_rx(dev, i) {
465 netif_napi_del(&dev->napi[i]);
466- mt76_dma_rx_cleanup(dev, &dev->q_rx[i]);
467+ type = FIELD_GET(MT_QFLAG_WED_TYPE, dev->q_rx[i].flags);
468+ if (type != MT76_WED_Q_RX)
469+ mt76_dma_rx_cleanup(dev, &dev->q_rx[i]);
470 }
471
472 mt76_free_pending_txwi(dev);
473+ mt76_free_pending_rxwi(dev);
474
475 if (mtk_wed_device_active(&dev->mmio.wed))
476 mtk_wed_device_detach(&dev->mmio.wed);
477+
478+ mt76_free_pending_rxwi(dev);
479 }
480 EXPORT_SYMBOL_GPL(mt76_dma_cleanup);
developer8cb3ac72022-07-04 10:55:14 +0800481diff --git a/dma.h b/dma.h
developerf50c1802022-07-05 20:35:53 +0800482index fdf786f..90370d1 100644
developer8cb3ac72022-07-04 10:55:14 +0800483--- a/dma.h
484+++ b/dma.h
485@@ -16,6 +16,16 @@
486 #define MT_DMA_CTL_LAST_SEC0 BIT(30)
487 #define MT_DMA_CTL_DMA_DONE BIT(31)
488
489+#define MT_DMA_CTL_TO_HOST BIT(8)
490+#define MT_DMA_CTL_TO_HOST_A BIT(12)
491+#define MT_DMA_CTL_DROP BIT(14)
492+
493+#define MT_DMA_CTL_TOKEN GENMASK(31, 16)
494+
495+#define MT_DMA_PPE_CPU_REASON GENMASK(15, 11)
496+#define MT_DMA_PPE_ENTRY GENMASK(30, 16)
497+#define MT_DMA_INFO_PPE_VLD BIT(31)
498+
499 #define MT_DMA_HDR_LEN 4
500 #define MT_RX_INFO_LEN 4
501 #define MT_FCE_INFO_LEN 4
502diff --git a/mac80211.c b/mac80211.c
developerf50c1802022-07-05 20:35:53 +0800503index af2c09a..fa5ce6e 100644
developer8cb3ac72022-07-04 10:55:14 +0800504--- a/mac80211.c
505+++ b/mac80211.c
506@@ -594,11 +594,14 @@ mt76_alloc_device(struct device *pdev, unsigned int size,
507 BIT(NL80211_IFTYPE_ADHOC);
508
509 spin_lock_init(&dev->token_lock);
510+ spin_lock_init(&dev->rx_token_lock);
511 idr_init(&dev->token);
512+ idr_init(&dev->rx_token);
513
514 INIT_LIST_HEAD(&dev->wcid_list);
515
516 INIT_LIST_HEAD(&dev->txwi_cache);
517+ INIT_LIST_HEAD(&dev->rxwi_cache);
518 dev->token_size = dev->drv->token_size;
519
520 for (i = 0; i < ARRAY_SIZE(dev->q_rx); i++)
521@@ -1296,7 +1299,10 @@ void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q,
522
523 while ((skb = __skb_dequeue(&dev->rx_skb[q])) != NULL) {
524 mt76_check_sta(dev, skb);
525- mt76_rx_aggr_reorder(skb, &frames);
526+ if (mtk_wed_device_active(&dev->mmio.wed))
527+ __skb_queue_tail(&frames, skb);
528+ else
529+ mt76_rx_aggr_reorder(skb, &frames);
530 }
531
532 mt76_rx_complete(dev, &frames, napi);
533diff --git a/mt76.h b/mt76.h
developerf50c1802022-07-05 20:35:53 +0800534index 4c8a671..24e4741 100644
developer8cb3ac72022-07-04 10:55:14 +0800535--- a/mt76.h
536+++ b/mt76.h
537@@ -20,6 +20,8 @@
538
539 #define MT_MCU_RING_SIZE 32
540 #define MT_RX_BUF_SIZE 2048
541+#define MTK_WED_RX_PKT_SIZE 1700
542+
543 #define MT_SKB_HEAD_LEN 256
544
545 #define MT_MAX_NON_AQL_PKT 16
546@@ -35,6 +37,7 @@
547 FIELD_PREP(MT_QFLAG_WED_TYPE, _type) | \
548 FIELD_PREP(MT_QFLAG_WED_RING, _n))
549 #define MT_WED_Q_TX(_n) __MT_WED_Q(MT76_WED_Q_TX, _n)
550+#define MT_WED_Q_RX(_n) __MT_WED_Q(MT76_WED_Q_RX, _n)
551 #define MT_WED_Q_TXFREE __MT_WED_Q(MT76_WED_Q_TXFREE, 0)
552
553 struct mt76_dev;
554@@ -56,6 +59,7 @@ enum mt76_bus_type {
555 enum mt76_wed_type {
556 MT76_WED_Q_TX,
557 MT76_WED_Q_TXFREE,
558+ MT76_WED_Q_RX,
559 };
560
561 struct mt76_bus_ops {
562@@ -305,7 +309,10 @@ struct mt76_txwi_cache {
563 struct list_head list;
564 dma_addr_t dma_addr;
565
566- struct sk_buff *skb;
567+ union {
568+ void *buf;
569+ struct sk_buff *skb;
570+ };
571 };
572
573 struct mt76_rx_tid {
574@@ -403,7 +410,7 @@ struct mt76_driver_ops {
575 bool (*rx_check)(struct mt76_dev *dev, void *data, int len);
576
577 void (*rx_skb)(struct mt76_dev *dev, enum mt76_rxq_id q,
578- struct sk_buff *skb);
579+ struct sk_buff *skb, u32 info);
580
581 void (*rx_poll_complete)(struct mt76_dev *dev, enum mt76_rxq_id q);
582
583@@ -747,6 +754,7 @@ struct mt76_dev {
584 struct ieee80211_hw *hw;
585
586 spinlock_t lock;
587+ spinlock_t wed_lock;
588 spinlock_t cc_lock;
589
590 u32 cur_cc_bss_rx;
591@@ -772,6 +780,7 @@ struct mt76_dev {
592 struct sk_buff_head rx_skb[__MT_RXQ_MAX];
593
594 struct list_head txwi_cache;
595+ struct list_head rxwi_cache;
596 struct mt76_queue *q_mcu[__MT_MCUQ_MAX];
597 struct mt76_queue q_rx[__MT_RXQ_MAX];
598 const struct mt76_queue_ops *queue_ops;
599@@ -785,6 +794,9 @@ struct mt76_dev {
600 u16 wed_token_count;
601 u16 token_count;
602 u16 token_size;
603+ u16 rx_token_size;
604+ spinlock_t rx_token_lock;
605+ struct idr rx_token;
606
607 wait_queue_head_t tx_wait;
608 /* spinclock used to protect wcid pktid linked list */
609@@ -1351,6 +1363,8 @@ mt76_tx_status_get_hw(struct mt76_dev *dev, struct sk_buff *skb)
610 }
611
612 void mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t);
613+void mt76_put_rxwi(struct mt76_dev *dev, struct mt76_txwi_cache *t);
614+struct mt76_txwi_cache *mt76_get_rxwi(struct mt76_dev *dev);
615 void mt76_rx_complete(struct mt76_dev *dev, struct sk_buff_head *frames,
616 struct napi_struct *napi);
617 void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q,
618@@ -1495,6 +1509,12 @@ struct mt76_txwi_cache *
619 mt76_token_release(struct mt76_dev *dev, int token, bool *wake);
620 int mt76_token_consume(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi);
621 void __mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked);
622+int mt76_rx_token_consume(struct mt76_dev *dev, void *ptr,
623+ struct mt76_txwi_cache *r, dma_addr_t phys);
624+void skb_trace(const struct sk_buff *skb, bool full_pkt);
625+
626+struct mt76_txwi_cache *
627+mt76_rx_token_release(struct mt76_dev *dev, int token);
628
629 static inline void mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked)
630 {
631diff --git a/mt7603/dma.c b/mt7603/dma.c
developerf50c1802022-07-05 20:35:53 +0800632index 590cff9..2ff71c5 100644
developer8cb3ac72022-07-04 10:55:14 +0800633--- a/mt7603/dma.c
634+++ b/mt7603/dma.c
635@@ -69,7 +69,7 @@ free:
636 }
637
638 void mt7603_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
639- struct sk_buff *skb)
640+ struct sk_buff *skb, u32 info)
641 {
642 struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76);
643 __le32 *rxd = (__le32 *)skb->data;
644diff --git a/mt7603/mt7603.h b/mt7603/mt7603.h
developerf50c1802022-07-05 20:35:53 +0800645index 0fd46d9..f2ce22a 100644
developer8cb3ac72022-07-04 10:55:14 +0800646--- a/mt7603/mt7603.h
647+++ b/mt7603/mt7603.h
648@@ -244,7 +244,7 @@ int mt7603_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
649 void mt7603_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue_entry *e);
650
651 void mt7603_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
652- struct sk_buff *skb);
653+ struct sk_buff *skb, u32 info);
654 void mt7603_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q);
655 void mt7603_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps);
656 int mt7603_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif,
657diff --git a/mt7615/mac.c b/mt7615/mac.c
developerf50c1802022-07-05 20:35:53 +0800658index 3728627..14cdd9a 100644
developer8cb3ac72022-07-04 10:55:14 +0800659--- a/mt7615/mac.c
660+++ b/mt7615/mac.c
developerf50c1802022-07-05 20:35:53 +0800661@@ -1648,7 +1648,7 @@ bool mt7615_rx_check(struct mt76_dev *mdev, void *data, int len)
developer8cb3ac72022-07-04 10:55:14 +0800662 EXPORT_SYMBOL_GPL(mt7615_rx_check);
663
664 void mt7615_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
665- struct sk_buff *skb)
666+ struct sk_buff *skb, u32 info)
667 {
668 struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
669 __le32 *rxd = (__le32 *)skb->data;
670diff --git a/mt7615/mt7615.h b/mt7615/mt7615.h
developerf50c1802022-07-05 20:35:53 +0800671index 25880d1..983469c 100644
developer8cb3ac72022-07-04 10:55:14 +0800672--- a/mt7615/mt7615.h
673+++ b/mt7615/mt7615.h
developerf50c1802022-07-05 20:35:53 +0800674@@ -511,7 +511,7 @@ void mt7615_tx_worker(struct mt76_worker *w);
developer8cb3ac72022-07-04 10:55:14 +0800675 void mt7615_tx_token_put(struct mt7615_dev *dev);
676 bool mt7615_rx_check(struct mt76_dev *mdev, void *data, int len);
677 void mt7615_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
678- struct sk_buff *skb);
679+ struct sk_buff *skb, u32 info);
680 void mt7615_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps);
681 int mt7615_mac_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif,
682 struct ieee80211_sta *sta);
683diff --git a/mt76_connac_mcu.c b/mt76_connac_mcu.c
developera3f86ed2022-07-08 14:15:13 +0800684index cd35068..2454846 100644
developer8cb3ac72022-07-04 10:55:14 +0800685--- a/mt76_connac_mcu.c
686+++ b/mt76_connac_mcu.c
687@@ -1190,6 +1190,7 @@ int mt76_connac_mcu_sta_ba(struct mt76_dev *dev, struct mt76_vif *mvif,
688 int cmd, bool enable, bool tx)
689 {
690 struct mt76_wcid *wcid = (struct mt76_wcid *)params->sta->drv_priv;
691+ struct mtk_wed_device *wed = &dev->mmio.wed;
692 struct wtbl_req_hdr *wtbl_hdr;
693 struct tlv *sta_wtbl;
694 struct sk_buff *skb;
developerf50c1802022-07-05 20:35:53 +0800695@@ -1210,6 +1211,8 @@ int mt76_connac_mcu_sta_ba(struct mt76_dev *dev, struct mt76_vif *mvif,
developer8cb3ac72022-07-04 10:55:14 +0800696 mt76_connac_mcu_wtbl_ba_tlv(dev, skb, params, enable, tx, sta_wtbl,
697 wtbl_hdr);
698
developerf50c1802022-07-05 20:35:53 +0800699+ if (mtk_wed_device_active(wed) && wed->ver > MTK_WED_V1)
developer6adfa0e2022-07-06 16:25:53 +0800700+ mtk_wed_device_update_msg(wed, WED_WO_STA_REC, skb->data, skb->len);
developer8cb3ac72022-07-04 10:55:14 +0800701 ret = mt76_mcu_skb_send_msg(dev, skb, cmd, true);
702 if (ret)
703 return ret;
developerf50c1802022-07-05 20:35:53 +0800704@@ -1220,6 +1223,8 @@ int mt76_connac_mcu_sta_ba(struct mt76_dev *dev, struct mt76_vif *mvif,
developer8cb3ac72022-07-04 10:55:14 +0800705
706 mt76_connac_mcu_sta_ba_tlv(skb, params, enable, tx);
707
developerf50c1802022-07-05 20:35:53 +0800708+ if (mtk_wed_device_active(wed) && wed->ver > MTK_WED_V1)
709+ mtk_wed_device_update_msg(wed, WED_WO_STA_REC, skb->data, skb->len);
developer8cb3ac72022-07-04 10:55:14 +0800710 return mt76_mcu_skb_send_msg(dev, skb, cmd, true);
711 }
712 EXPORT_SYMBOL_GPL(mt76_connac_mcu_sta_ba);
developerf50c1802022-07-05 20:35:53 +0800713@@ -2634,6 +2639,7 @@ int mt76_connac_mcu_add_key(struct mt76_dev *dev, struct ieee80211_vif *vif,
developer8cb3ac72022-07-04 10:55:14 +0800714 struct mt76_wcid *wcid, enum set_key_cmd cmd)
715 {
716 struct mt76_vif *mvif = (struct mt76_vif *)vif->drv_priv;
717+ struct mtk_wed_device *wed = &dev->mmio.wed;
718 struct sk_buff *skb;
719 int ret;
720
developerf50c1802022-07-05 20:35:53 +0800721@@ -2645,6 +2651,9 @@ int mt76_connac_mcu_add_key(struct mt76_dev *dev, struct ieee80211_vif *vif,
developer8cb3ac72022-07-04 10:55:14 +0800722 if (ret)
723 return ret;
724
developerf50c1802022-07-05 20:35:53 +0800725+ if (mtk_wed_device_active(wed) && wed->ver > MTK_WED_V1)
developer8cb3ac72022-07-04 10:55:14 +0800726+ mtk_wed_device_update_msg(wed, WED_WO_STA_REC, skb->data, skb->len);
727+
728 return mt76_mcu_skb_send_msg(dev, skb, mcu_cmd, true);
729 }
730 EXPORT_SYMBOL_GPL(mt76_connac_mcu_add_key);
731diff --git a/mt76x02.h b/mt76x02.h
developerf50c1802022-07-05 20:35:53 +0800732index f76fd22..0b872af 100644
developer8cb3ac72022-07-04 10:55:14 +0800733--- a/mt76x02.h
734+++ b/mt76x02.h
735@@ -173,7 +173,7 @@ int mt76x02_set_rts_threshold(struct ieee80211_hw *hw, u32 val);
736 void mt76x02_remove_hdr_pad(struct sk_buff *skb, int len);
737 bool mt76x02_tx_status_data(struct mt76_dev *mdev, u8 *update);
738 void mt76x02_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
739- struct sk_buff *skb);
740+ struct sk_buff *skb, u32 info);
741 void mt76x02_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q);
742 irqreturn_t mt76x02_irq_handler(int irq, void *dev_instance);
743 void mt76x02_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control,
744diff --git a/mt76x02_txrx.c b/mt76x02_txrx.c
developerf50c1802022-07-05 20:35:53 +0800745index 96fdf42..bf24d3e 100644
developer8cb3ac72022-07-04 10:55:14 +0800746--- a/mt76x02_txrx.c
747+++ b/mt76x02_txrx.c
748@@ -33,7 +33,7 @@ void mt76x02_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control,
749 EXPORT_SYMBOL_GPL(mt76x02_tx);
750
751 void mt76x02_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
752- struct sk_buff *skb)
753+ struct sk_buff *skb, u32 info)
754 {
755 struct mt76x02_dev *dev = container_of(mdev, struct mt76x02_dev, mt76);
756 void *rxwi = skb->data;
757diff --git a/mt7915/dma.c b/mt7915/dma.c
developerf50c1802022-07-05 20:35:53 +0800758index 7122322..ac98e01 100644
developer8cb3ac72022-07-04 10:55:14 +0800759--- a/mt7915/dma.c
760+++ b/mt7915/dma.c
761@@ -376,6 +376,8 @@ int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2)
762 FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_TX0, 18) |
763 FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_TX1, 19) |
764 FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_RX1, 1));
765+ mt76_rmw(dev, MT_WFDMA0_EXT0_CFG, MT_WFDMA0_EXT0_RXWB_KEEP,
766+ MT_WFDMA0_EXT0_RXWB_KEEP);
767 } else {
768 mt76_wr(dev, MT_WFDMA_WED_RING_CONTROL,
769 FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_TX0, 18) |
developerf50c1802022-07-05 20:35:53 +0800770@@ -451,6 +453,10 @@ int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2)
developer8cb3ac72022-07-04 10:55:14 +0800771
772 /* rx data queue for band0 */
773 if (!dev->phy.band_idx) {
developerf50c1802022-07-05 20:35:53 +0800774+ if (mtk_wed_device_active(&dev->mt76.mmio.wed) &&
775+ dev->mt76.mmio.wed.ver > MTK_WED_V1)
developer8cb3ac72022-07-04 10:55:14 +0800776+ dev->mt76.q_rx[MT_RXQ_MAIN].flags = MT_WED_Q_RX(MT7915_RXQ_BAND0);
777+
778 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN],
779 MT_RXQ_ID(MT_RXQ_MAIN),
780 MT7915_RX_RING_SIZE,
developerf50c1802022-07-05 20:35:53 +0800781@@ -482,6 +488,10 @@ int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2)
developer8cb3ac72022-07-04 10:55:14 +0800782
783 if (dev->dbdc_support || dev->phy.band_idx) {
784 /* rx data queue for band1 */
developerf50c1802022-07-05 20:35:53 +0800785+ if (mtk_wed_device_active(&dev->mt76.mmio.wed) &&
786+ dev->mt76.mmio.wed.ver > MTK_WED_V1)
developer8cb3ac72022-07-04 10:55:14 +0800787+ dev->mt76.q_rx[MT_RXQ_EXT].flags = MT_WED_Q_RX(MT7915_RXQ_BAND1);
788+
789 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_EXT],
790 MT_RXQ_ID(MT_RXQ_EXT),
791 MT7915_RX_RING_SIZE,
792diff --git a/mt7915/mac.c b/mt7915/mac.c
developera3f86ed2022-07-08 14:15:13 +0800793index bc8da4d..dd87a40 100644
developer8cb3ac72022-07-04 10:55:14 +0800794--- a/mt7915/mac.c
795+++ b/mt7915/mac.c
796@@ -217,7 +217,7 @@ static void mt7915_mac_sta_poll(struct mt7915_dev *dev)
797 }
798
799 static int
800-mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
801+mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb, enum mt76_rxq_id q, u32 info)
802 {
803 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
804 struct mt76_phy *mphy = &dev->mt76.phy;
developera3f86ed2022-07-08 14:15:13 +0800805@@ -234,7 +234,7 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
806 bool unicast, insert_ccmp_hdr = false;
807 u8 remove_pad, amsdu_info;
808 u8 mode = 0, qos_ctl = 0;
809- struct mt7915_sta *msta;
810+ struct mt7915_sta *msta = NULL;
811 bool hdr_trans;
812 u16 hdr_gap;
813 u16 seq_ctrl = 0;
developer8cb3ac72022-07-04 10:55:14 +0800814@@ -494,6 +494,27 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
815 #endif
816 } else {
817 status->flag |= RX_FLAG_8023;
developera3f86ed2022-07-08 14:15:13 +0800818+ if (msta && msta->vif) {
developer8cb3ac72022-07-04 10:55:14 +0800819+ struct mtk_wed_device *wed;
820+ int type;
821+
822+ wed = &dev->mt76.mmio.wed;
823+ type = FIELD_GET(MT_QFLAG_WED_TYPE, dev->mt76.q_rx[q].flags);
824+ if ((mtk_wed_device_active(wed) && type == MT76_WED_Q_RX) &&
developera3f86ed2022-07-08 14:15:13 +0800825+ (info & MT_DMA_INFO_PPE_VLD)) {
developer8cb3ac72022-07-04 10:55:14 +0800826+ struct ieee80211_vif *vif;
827+ u32 hash, reason;
828+
829+ vif = container_of((void *)msta->vif, struct ieee80211_vif,
developera3f86ed2022-07-08 14:15:13 +0800830+ drv_priv);
developer8cb3ac72022-07-04 10:55:14 +0800831+
832+ skb->dev = ieee80211_vif_to_netdev(vif);
833+ reason = FIELD_GET(MT_DMA_PPE_CPU_REASON, info);
834+ hash = FIELD_GET(MT_DMA_PPE_ENTRY, info);
835+
836+ mtk_wed_device_ppe_check(wed, skb, reason, hash);
837+ }
838+ }
839 }
840
841 if (rxv && mode >= MT_PHY_TYPE_HE_SU && !(status->flag & RX_FLAG_8023))
developera3f86ed2022-07-08 14:15:13 +0800842@@ -840,6 +861,80 @@ u32 mt7915_wed_init_buf(void *ptr, dma_addr_t phys, int token_id)
developer8cb3ac72022-07-04 10:55:14 +0800843 return MT_TXD_TXP_BUF_SIZE;
844 }
845
846+u32
847+mt7915_wed_init_rx_buf(struct mtk_wed_device *wed, int pkt_num)
848+{
849+ struct mtk_rxbm_desc *desc = wed->rx_buf_ring.desc;
850+ struct mt7915_dev *dev;
851+ dma_addr_t buf_phys;
852+ void *buf;
853+ int i, token, buf_size;
854+
855+ buf_size = SKB_DATA_ALIGN(NET_SKB_PAD + wed->wlan.rx_pkt_size) +
856+ SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
857+
858+ dev = container_of(wed, struct mt7915_dev, mt76.mmio.wed);
859+ for (i = 0; i < pkt_num; i++) {
860+ struct mt76_txwi_cache *r = mt76_get_rxwi(&dev->mt76);
861+
862+ buf = page_frag_alloc(&wed->rx_page, buf_size, GFP_ATOMIC);
863+ if (!buf)
864+ return -ENOMEM;
865+
866+ buf_phys = dma_map_single(dev->mt76.dma_dev, buf, wed->wlan.rx_pkt_size,
867+ DMA_TO_DEVICE);
868+
869+ if (unlikely(dma_mapping_error(dev->mt76.dev, buf_phys))) {
870+ skb_free_frag(buf);
871+ break;
872+ }
873+
874+ desc->buf0 = buf_phys;
875+
876+ token = mt76_rx_token_consume(&dev->mt76, buf, r, buf_phys);
877+
878+ desc->token |= FIELD_PREP(MT_DMA_CTL_TOKEN, token);
879+ desc++;
880+ }
881+
882+ return 0;
883+}
884+
885+void mt7915_wed_release_rx_buf(struct mtk_wed_device *wed)
886+{
887+ struct mt76_txwi_cache *rxwi;
888+ struct mt7915_dev *dev;
developera3f86ed2022-07-08 14:15:13 +0800889+ struct page *page;
developer8cb3ac72022-07-04 10:55:14 +0800890+ int token;
891+
892+ dev = container_of(wed, struct mt7915_dev, mt76.mmio.wed);
893+
894+ for(token = 0; token < dev->mt76.rx_token_size; token++) {
895+ rxwi = mt76_rx_token_release(&dev->mt76, token);
896+ if(!rxwi)
897+ continue;
898+
developera3f86ed2022-07-08 14:15:13 +0800899+ if(!rxwi->buf)
900+ continue;
901+
developer8cb3ac72022-07-04 10:55:14 +0800902+ dma_unmap_single(dev->mt76.dma_dev, rxwi->dma_addr,
903+ wed->wlan.rx_pkt_size, DMA_FROM_DEVICE);
904+ skb_free_frag(rxwi->buf);
905+ rxwi->buf = NULL;
906+
907+ mt76_put_rxwi(&dev->mt76, rxwi);
908+ }
developera3f86ed2022-07-08 14:15:13 +0800909+
910+ if (wed->rx_page.va)
911+ return;
912+
913+ page = virt_to_page(wed->rx_page.va);
914+ __page_frag_cache_drain(page, wed->rx_page.pagecnt_bias);
915+ memset(&wed->rx_page, 0, sizeof(wed->rx_page));
916+
developer8cb3ac72022-07-04 10:55:14 +0800917+ return;
918+}
919+
920 static void
921 mt7915_tx_check_aggr(struct ieee80211_sta *sta, __le32 *txwi)
922 {
developera3f86ed2022-07-08 14:15:13 +0800923@@ -1120,7 +1215,7 @@ bool mt7915_rx_check(struct mt76_dev *mdev, void *data, int len)
developer8cb3ac72022-07-04 10:55:14 +0800924 }
925
926 void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
927- struct sk_buff *skb)
928+ struct sk_buff *skb, u32 info)
929 {
930 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
931 __le32 *rxd = (__le32 *)skb->data;
developera3f86ed2022-07-08 14:15:13 +0800932@@ -1154,7 +1249,7 @@ void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
developer8cb3ac72022-07-04 10:55:14 +0800933 dev_kfree_skb(skb);
934 break;
935 case PKT_TYPE_NORMAL:
936- if (!mt7915_mac_fill_rx(dev, skb)) {
937+ if (!mt7915_mac_fill_rx(dev, skb, q, info)) {
938 mt76_rx(&dev->mt76, q, skb);
939 return;
940 }
941diff --git a/mt7915/mcu.c b/mt7915/mcu.c
developera3f86ed2022-07-08 14:15:13 +0800942index 1468c3c..5eace9e 100644
developer8cb3ac72022-07-04 10:55:14 +0800943--- a/mt7915/mcu.c
944+++ b/mt7915/mcu.c
945@@ -1704,6 +1704,7 @@ int mt7915_mcu_add_sta(struct mt7915_dev *dev, struct ieee80211_vif *vif,
946 struct ieee80211_sta *sta, bool enable)
947 {
948 struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv;
949+ struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
950 struct mt7915_sta *msta;
951 struct sk_buff *skb;
952 int ret;
developerf50c1802022-07-05 20:35:53 +0800953@@ -1756,6 +1757,8 @@ int mt7915_mcu_add_sta(struct mt7915_dev *dev, struct ieee80211_vif *vif,
developer8cb3ac72022-07-04 10:55:14 +0800954 return ret;
955 }
956 out:
developerf50c1802022-07-05 20:35:53 +0800957+ if (mtk_wed_device_active(wed) && wed->ver > MTK_WED_V1)
958+ mtk_wed_device_update_msg(wed, WED_WO_STA_REC, skb->data, skb->len);
developer8cb3ac72022-07-04 10:55:14 +0800959 return mt76_mcu_skb_send_msg(&dev->mt76, skb,
960 MCU_EXT_CMD(STA_REC_UPDATE), true);
961 }
962diff --git a/mt7915/mmio.c b/mt7915/mmio.c
developera3f86ed2022-07-08 14:15:13 +0800963index b4a3120..08ff556 100644
developer8cb3ac72022-07-04 10:55:14 +0800964--- a/mt7915/mmio.c
965+++ b/mt7915/mmio.c
966@@ -28,6 +28,9 @@ static const u32 mt7915_reg[] = {
967 [FW_EXCEPTION_ADDR] = 0x219848,
968 [SWDEF_BASE_ADDR] = 0x41f200,
969 [EXCEPTION_BASE_ADDR] = 0x219848,
970+ [WED_TX_RING] = 0xd7300,
971+ [WED_RX_RING] = 0xd7410,
972+ [WED_RX_DATA_RING] = 0xd4500,
973 };
974
975 static const u32 mt7916_reg[] = {
976@@ -45,6 +48,9 @@ static const u32 mt7916_reg[] = {
977 [FW_EXCEPTION_ADDR] = 0x022050bc,
978 [SWDEF_BASE_ADDR] = 0x411400,
979 [EXCEPTION_BASE_ADDR] = 0x022050BC,
980+ [WED_TX_RING] = 0xd7300,
981+ [WED_RX_RING] = 0xd7410,
982+ [WED_RX_DATA_RING] = 0xd4540,
983 };
984
985 static const u32 mt7986_reg[] = {
986@@ -62,6 +68,9 @@ static const u32 mt7986_reg[] = {
987 [FW_EXCEPTION_ADDR] = 0x02204ffc,
988 [SWDEF_BASE_ADDR] = 0x411400,
989 [EXCEPTION_BASE_ADDR] = 0x02204FFC,
990+ [WED_TX_RING] = 0x24420,
991+ [WED_RX_RING] = 0x24520,
992+ [WED_RX_DATA_RING] = 0x24540,
993 };
994
995 static const u32 mt7915_offs[] = {
developerf50c1802022-07-05 20:35:53 +0800996@@ -710,6 +719,7 @@ mt7915_pci_wed_init(struct mt7915_dev *dev, struct device *pdev, int *irq)
997 wed->wlan.bus_type = MTK_BUS_TYPE_PCIE;
998 wed->wlan.wpdma_int = base + MT_INT_WED_SOURCE_CSR;
999 wed->wlan.wpdma_mask = base + MT_INT_WED_MASK_CSR;
1000+ wed->wlan.wpdma_phys = base + MT_WFDMA_EXT_CSR_BASE;
1001 } else {
1002 struct platform_device *plat_dev;
1003 struct resource *res;
1004@@ -722,12 +732,19 @@ mt7915_pci_wed_init(struct mt7915_dev *dev, struct device *pdev, int *irq)
developer8cb3ac72022-07-04 10:55:14 +08001005 wed->wlan.wpdma_int = base + MT_INT_SOURCE_CSR;
1006 wed->wlan.wpdma_mask = base + MT_INT_MASK_CSR;
1007 }
1008+ wed->wlan.rx_pkt = MT7915_WED_RX_TOKEN_SIZE;
1009+ wed->wlan.phy_base = base;
1010 wed->wlan.wpdma_tx = base + MT_TXQ_WED_RING_BASE;
1011 wed->wlan.wpdma_txfree = base + MT_RXQ_WED_RING_BASE;
1012+ wed->wlan.wpdma_rx_glo = base + MT_WPDMA_GLO_CFG;
1013+ wed->wlan.wpdma_rx = base + MT_RXQ_WED_DATA_RING_BASE;
1014
1015 wed->wlan.tx_tbit[0] = MT_WED_TX_DONE_BAND0;
1016 wed->wlan.tx_tbit[1] = MT_WED_TX_DONE_BAND1;
1017 wed->wlan.txfree_tbit = MT_WED_TX_FREE_DONE;
1018+ wed->wlan.rx_tbit[0] = MT_WED_RX_DONE_BAND0;
1019+ wed->wlan.rx_tbit[1] = MT_WED_RX_DONE_BAND1;
1020+
1021 wed->wlan.nbuf = 7168;
1022 wed->wlan.token_start = MT7915_TOKEN_SIZE - wed->wlan.nbuf;
1023 wed->wlan.init_buf = mt7915_wed_init_buf;
developerf50c1802022-07-05 20:35:53 +08001024@@ -735,12 +752,15 @@ mt7915_pci_wed_init(struct mt7915_dev *dev, struct device *pdev, int *irq)
developer8cb3ac72022-07-04 10:55:14 +08001025 wed->wlan.offload_enable = mt7915_wed_offload_enable;
1026 wed->wlan.offload_disable = mt7915_wed_offload_disable;
1027
1028+ wed->wlan.rx_nbuf = 65536;
1029+ wed->wlan.rx_pkt_size = MTK_WED_RX_PKT_SIZE;
1030+ wed->wlan.init_rx_buf = mt7915_wed_init_rx_buf;
1031+ wed->wlan.release_rx_buf = mt7915_wed_release_rx_buf;
1032+
1033+ dev->mt76.rx_token_size = wed->wlan.rx_pkt + MT7915_RX_RING_SIZE * 2;
1034 if (mtk_wed_device_attach(wed) != 0)
1035 return 0;
1036
developerf50c1802022-07-05 20:35:53 +08001037- if (wed->ver == MTK_WED_V1)
1038- wed->wlan.wpdma_phys = base + MT_WFDMA_EXT_CSR_BASE;
1039-
1040 *irq = wed->irq;
1041 dev->mt76.dma_dev = wed->dev;
1042 mdev->token_size = wed->wlan.token_start;
developer8cb3ac72022-07-04 10:55:14 +08001043diff --git a/mt7915/mt7915.h b/mt7915/mt7915.h
developerf50c1802022-07-05 20:35:53 +08001044index fe407c5..e2f0d41 100644
developer8cb3ac72022-07-04 10:55:14 +08001045--- a/mt7915/mt7915.h
1046+++ b/mt7915/mt7915.h
developerf50c1802022-07-05 20:35:53 +08001047@@ -69,6 +69,7 @@
developer8cb3ac72022-07-04 10:55:14 +08001048 #define MT7915_MAX_STA_TWT_AGRT 8
1049 #define MT7915_MIN_TWT_DUR 64
1050 #define MT7915_MAX_QUEUE (__MT_RXQ_MAX + __MT_MCUQ_MAX + 2)
1051+#define MT7915_WED_RX_TOKEN_SIZE 12288
1052
1053 struct mt7915_vif;
1054 struct mt7915_sta;
developerf50c1802022-07-05 20:35:53 +08001055@@ -531,7 +532,9 @@ void mt7915_wfsys_reset(struct mt7915_dev *dev);
developer8cb3ac72022-07-04 10:55:14 +08001056 irqreturn_t mt7915_irq_handler(int irq, void *dev_instance);
1057 u64 __mt7915_get_tsf(struct ieee80211_hw *hw, struct mt7915_vif *mvif);
1058 u32 mt7915_wed_init_buf(void *ptr, dma_addr_t phys, int token_id);
1059-
1060+u32 mt7915_wed_init_rx_buf(struct mtk_wed_device *wed,
1061+ int pkt_num);
1062+void mt7915_wed_release_rx_buf(struct mtk_wed_device *wed);
1063 int mt7915_register_device(struct mt7915_dev *dev);
1064 void mt7915_unregister_device(struct mt7915_dev *dev);
1065 int mt7915_eeprom_init(struct mt7915_dev *dev);
developerf50c1802022-07-05 20:35:53 +08001066@@ -683,7 +686,7 @@ int mt7915_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
developer8cb3ac72022-07-04 10:55:14 +08001067 struct mt76_tx_info *tx_info);
1068 void mt7915_tx_token_put(struct mt7915_dev *dev);
1069 void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1070- struct sk_buff *skb);
1071+ struct sk_buff *skb, u32 info);
1072 bool mt7915_rx_check(struct mt76_dev *mdev, void *data, int len);
1073 void mt7915_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps);
1074 void mt7915_stats_work(struct work_struct *work);
1075diff --git a/mt7915/regs.h b/mt7915/regs.h
developerf50c1802022-07-05 20:35:53 +08001076index ffda5f6..08bf84c 100644
developer8cb3ac72022-07-04 10:55:14 +08001077--- a/mt7915/regs.h
1078+++ b/mt7915/regs.h
1079@@ -33,6 +33,9 @@ enum reg_rev {
1080 FW_EXCEPTION_ADDR,
1081 SWDEF_BASE_ADDR,
1082 EXCEPTION_BASE_ADDR,
1083+ WED_TX_RING,
1084+ WED_RX_RING,
1085+ WED_RX_DATA_RING,
1086 __MT_REG_MAX,
1087 };
1088
1089@@ -570,9 +573,13 @@ enum offs_rev {
1090 #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2 BIT(21)
1091
1092 #define MT_WFDMA0_RST_DTX_PTR MT_WFDMA0(0x20c)
1093+#define MT_WFDMA0_EXT0_CFG MT_WFDMA0(0x2b0)
1094+#define MT_WFDMA0_EXT0_RXWB_KEEP BIT(10)
1095+
1096 #define MT_WFDMA0_PRI_DLY_INT_CFG0 MT_WFDMA0(0x2f0)
1097 #define MT_WFDMA0_PRI_DLY_INT_CFG1 MT_WFDMA0(0x2f4)
1098 #define MT_WFDMA0_PRI_DLY_INT_CFG2 MT_WFDMA0(0x2f8)
1099+#define MT_WPDMA_GLO_CFG MT_WFDMA0(0x208)
1100
1101 #define MT_WFDMA0_MCU_HOST_INT_ENA MT_WFDMA0(0x1f4)
1102 #define MT_WFDMA0_MT_WA_WDT_INT BIT(31)
1103@@ -670,12 +677,15 @@ enum offs_rev {
1104 #define MT_TXQ_EXT_CTRL(q) (MT_Q_BASE(__TXQ(q)) + 0x600 + \
1105 MT_TXQ_ID(q)* 0x4)
1106
1107-#define MT_TXQ_WED_RING_BASE (!is_mt7986(mdev)? 0xd7300 : 0x24420)
1108-#define MT_RXQ_WED_RING_BASE (!is_mt7986(mdev)? 0xd7410 : 0x24520)
1109+#define MT_TXQ_WED_RING_BASE __REG(WED_TX_RING)
1110+#define MT_RXQ_WED_RING_BASE __REG(WED_RX_RING)
1111+#define MT_RXQ_WED_DATA_RING_BASE __REG(WED_RX_DATA_RING)
1112
1113 #define MT_WED_TX_DONE_BAND0 (is_mt7915(mdev)? 4 : 30)
1114 #define MT_WED_TX_DONE_BAND1 (is_mt7915(mdev)? 5 : 31)
1115 #define MT_WED_TX_FREE_DONE (is_mt7915(mdev)? 1 : 2)
1116+#define MT_WED_RX_DONE_BAND0 (is_mt7915(mdev)? 16 : 22)
1117+#define MT_WED_RX_DONE_BAND1 (is_mt7915(mdev)? 17 : 23)
1118
1119 #define MT_INT_SOURCE_CSR __REG(INT_SOURCE_CSR)
1120 #define MT_INT_MASK_CSR __REG(INT_MASK_CSR)
1121diff --git a/mt7921/mac.c b/mt7921/mac.c
developerf50c1802022-07-05 20:35:53 +08001122index 4fcadf8..4897940 100644
developer8cb3ac72022-07-04 10:55:14 +08001123--- a/mt7921/mac.c
1124+++ b/mt7921/mac.c
1125@@ -555,7 +555,7 @@ out:
1126 EXPORT_SYMBOL_GPL(mt7921_mac_add_txs);
1127
1128 void mt7921_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1129- struct sk_buff *skb)
1130+ struct sk_buff *skb, u32 info)
1131 {
1132 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
1133 __le32 *rxd = (__le32 *)skb->data;
1134diff --git a/mt7921/mt7921.h b/mt7921/mt7921.h
developerf50c1802022-07-05 20:35:53 +08001135index efeb82c..4b2e974 100644
developer8cb3ac72022-07-04 10:55:14 +08001136--- a/mt7921/mt7921.h
1137+++ b/mt7921/mt7921.h
1138@@ -388,7 +388,7 @@ int mt7921e_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
1139 void mt7921_tx_worker(struct mt76_worker *w);
1140 void mt7921_tx_token_put(struct mt7921_dev *dev);
1141 void mt7921_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1142- struct sk_buff *skb);
1143+ struct sk_buff *skb, u32 info);
1144 void mt7921_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps);
1145 void mt7921_stats_work(struct work_struct *work);
1146 void mt7921_set_stream_he_caps(struct mt7921_phy *phy);
1147@@ -424,7 +424,7 @@ int mt7921_mcu_parse_response(struct mt76_dev *mdev, int cmd,
1148
1149 bool mt7921e_rx_check(struct mt76_dev *mdev, void *data, int len);
1150 void mt7921e_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1151- struct sk_buff *skb);
1152+ struct sk_buff *skb, u32 info);
1153 int mt7921e_driver_own(struct mt7921_dev *dev);
1154 int mt7921e_mac_reset(struct mt7921_dev *dev);
1155 int mt7921e_mcu_init(struct mt7921_dev *dev);
1156diff --git a/mt7921/pci_mac.c b/mt7921/pci_mac.c
developerf50c1802022-07-05 20:35:53 +08001157index e180067..ca982eb 100644
developer8cb3ac72022-07-04 10:55:14 +08001158--- a/mt7921/pci_mac.c
1159+++ b/mt7921/pci_mac.c
1160@@ -182,7 +182,7 @@ bool mt7921e_rx_check(struct mt76_dev *mdev, void *data, int len)
1161 }
1162
1163 void mt7921e_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1164- struct sk_buff *skb)
1165+ struct sk_buff *skb, u32 info)
1166 {
1167 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
1168 __le32 *rxd = (__le32 *)skb->data;
1169@@ -196,7 +196,7 @@ void mt7921e_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1170 napi_consume_skb(skb, 1);
1171 break;
1172 default:
1173- mt7921_queue_rx_skb(mdev, q, skb);
1174+ mt7921_queue_rx_skb(mdev, q, skb, info);
1175 break;
1176 }
1177 }
1178diff --git a/tx.c b/tx.c
developerf50c1802022-07-05 20:35:53 +08001179index ae44afe..bccd206 100644
developer8cb3ac72022-07-04 10:55:14 +08001180--- a/tx.c
1181+++ b/tx.c
developerf50c1802022-07-05 20:35:53 +08001182@@ -767,3 +767,37 @@ mt76_token_release(struct mt76_dev *dev, int token, bool *wake)
developer8cb3ac72022-07-04 10:55:14 +08001183 return txwi;
1184 }
1185 EXPORT_SYMBOL_GPL(mt76_token_release);
1186+
1187+int mt76_rx_token_consume(struct mt76_dev *dev, void *ptr,
1188+ struct mt76_txwi_cache *r, dma_addr_t phys)
1189+{
1190+ int token;
1191+
1192+ spin_lock_bh(&dev->rx_token_lock);
1193+
1194+ token = idr_alloc(&dev->rx_token, r, 0, dev->rx_token_size, GFP_ATOMIC);
1195+
1196+ spin_unlock_bh(&dev->rx_token_lock);
1197+
1198+ r->buf = ptr;
1199+ r->dma_addr = phys;
1200+
1201+ return token;
1202+}
1203+EXPORT_SYMBOL_GPL(mt76_rx_token_consume);
1204+
1205+struct mt76_txwi_cache *
1206+mt76_rx_token_release(struct mt76_dev *dev, int token)
1207+{
1208+
1209+ struct mt76_txwi_cache *rxwi;
1210+
1211+ spin_lock_bh(&dev->rx_token_lock);
1212+
1213+ rxwi = idr_remove(&dev->rx_token, token);
1214+
1215+ spin_unlock_bh(&dev->rx_token_lock);
1216+
1217+ return rxwi;
1218+}
1219+EXPORT_SYMBOL_GPL(mt76_rx_token_release);
1220--
12212.18.0
1222