blob: 3ef5f631676dc6d073013c1b9e04ddabbf3394ec [file] [log] [blame]
developerd59e4772022-07-14 13:48:49 +08001From a6bbc51840c63e5992c2d0cee9fbbb795312da0c Mon Sep 17 00:00:00 2001
developer8cb3ac72022-07-04 10:55:14 +08002From: Sujuan Chen <sujuan.chen@mediatek.com>
developerf50c1802022-07-05 20:35:53 +08003Date: Tue, 5 Jul 2022 19:42:55 +0800
developerd59e4772022-07-14 13:48:49 +08004Subject: [PATCH 3002/3003] mt76 add wed rx support
developer8cb3ac72022-07-04 10:55:14 +08005
6Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
7---
developerd59e4772022-07-14 13:48:49 +08008 drivers/net/wireless/mediatek/mt76/dma.c | 246 +++++++++++++++---
9 drivers/net/wireless/mediatek/mt76/dma.h | 10 +
10 drivers/net/wireless/mediatek/mt76/mac80211.c | 8 +-
11 drivers/net/wireless/mediatek/mt76/mt76.h | 24 +-
12 .../net/wireless/mediatek/mt76/mt7603/dma.c | 2 +-
13 .../wireless/mediatek/mt76/mt7603/mt7603.h | 2 +-
14 .../net/wireless/mediatek/mt76/mt7615/mac.c | 2 +-
15 .../wireless/mediatek/mt76/mt7615/mt7615.h | 2 +-
16 .../wireless/mediatek/mt76/mt76_connac_mcu.c | 9 +
17 drivers/net/wireless/mediatek/mt76/mt76x02.h | 2 +-
18 .../net/wireless/mediatek/mt76/mt76x02_txrx.c | 2 +-
19 .../net/wireless/mediatek/mt76/mt7915/dma.c | 10 +
20 .../net/wireless/mediatek/mt76/mt7915/mac.c | 103 +++++++-
21 .../net/wireless/mediatek/mt76/mt7915/mcu.c | 3 +
22 .../net/wireless/mediatek/mt76/mt7915/mmio.c | 26 +-
23 .../wireless/mediatek/mt76/mt7915/mt7915.h | 7 +-
24 .../net/wireless/mediatek/mt76/mt7915/regs.h | 14 +-
25 .../net/wireless/mediatek/mt76/mt7921/mac.c | 2 +-
26 .../wireless/mediatek/mt76/mt7921/mt7921.h | 4 +-
27 .../wireless/mediatek/mt76/mt7921/pci_mac.c | 4 +-
28 drivers/net/wireless/mediatek/mt76/tx.c | 34 +++
developera3f86ed2022-07-08 14:15:13 +080029 21 files changed, 448 insertions(+), 68 deletions(-)
developer8cb3ac72022-07-04 10:55:14 +080030
31diff --git a/dma.c b/dma.c
developerd59e4772022-07-14 13:48:49 +080032index 03ee9109..3acba9a3 100644
developer8cb3ac72022-07-04 10:55:14 +080033--- a/dma.c
34+++ b/dma.c
35@@ -98,6 +98,63 @@ mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t)
36 }
37 EXPORT_SYMBOL_GPL(mt76_put_txwi);
38
39+static struct mt76_txwi_cache *
40+mt76_alloc_rxwi(struct mt76_dev *dev)
41+{
42+ struct mt76_txwi_cache *r;
43+ int size;
44+
45+ size = L1_CACHE_ALIGN(sizeof(*r));
46+ r = kzalloc(size, GFP_ATOMIC);
47+ if (!r)
48+ return NULL;
49+
50+ r->buf = NULL;
51+
52+ return r;
53+}
54+
55+static struct mt76_txwi_cache *
56+__mt76_get_rxwi(struct mt76_dev *dev)
57+{
58+ struct mt76_txwi_cache *r = NULL;
59+
60+ spin_lock(&dev->wed_lock);
61+ if (!list_empty(&dev->rxwi_cache)) {
62+ r = list_first_entry(&dev->rxwi_cache, struct mt76_txwi_cache,
63+ list);
64+ if(r)
65+ list_del(&r->list);
66+ }
67+ spin_unlock(&dev->wed_lock);
68+
69+ return r;
70+}
71+
72+struct mt76_txwi_cache *
73+mt76_get_rxwi(struct mt76_dev *dev)
74+{
75+ struct mt76_txwi_cache *r = __mt76_get_rxwi(dev);
76+
77+ if (r)
78+ return r;
79+
80+ return mt76_alloc_rxwi(dev);
81+}
82+EXPORT_SYMBOL_GPL(mt76_get_rxwi);
83+
84+void
85+mt76_put_rxwi(struct mt76_dev *dev, struct mt76_txwi_cache *r)
86+{
87+ if (!r)
88+ return;
89+
90+ spin_lock(&dev->wed_lock);
91+ list_add(&r->list, &dev->rxwi_cache);
92+ spin_unlock(&dev->wed_lock);
93+}
94+EXPORT_SYMBOL_GPL(mt76_put_rxwi);
95+
96 static void
97 mt76_free_pending_txwi(struct mt76_dev *dev)
98 {
developera3f86ed2022-07-08 14:15:13 +080099@@ -112,6 +169,21 @@ mt76_free_pending_txwi(struct mt76_dev *dev)
100 local_bh_enable();
101 }
102
103+static void
104+mt76_free_pending_rxwi(struct mt76_dev *dev)
105+{
106+ struct mt76_txwi_cache *r;
107+
108+ local_bh_disable();
109+ while ((r = __mt76_get_rxwi(dev)) != NULL) {
110+ if (r->buf)
111+ skb_free_frag(r->buf);
112+
113+ kfree(r);
114+ }
115+ local_bh_enable();
116+}
117+
118 static void
119 mt76_dma_sync_idx(struct mt76_dev *dev, struct mt76_queue *q)
120 {
121@@ -141,12 +213,15 @@ mt76_dma_queue_reset(struct mt76_dev *dev, struct mt76_queue *q)
developer8cb3ac72022-07-04 10:55:14 +0800122 static int
123 mt76_dma_add_buf(struct mt76_dev *dev, struct mt76_queue *q,
124 struct mt76_queue_buf *buf, int nbufs, u32 info,
125- struct sk_buff *skb, void *txwi)
126+ struct sk_buff *skb, void *txwi, void *rxwi)
127 {
128+ struct mtk_wed_device *wed = &dev->mmio.wed;
129+
130 struct mt76_queue_entry *entry;
131 struct mt76_desc *desc;
132 u32 ctrl;
133 int i, idx = -1;
134+ int type;
135
136 if (txwi) {
137 q->entry[q->head].txwi = DMA_DUMMY_DATA;
developera3f86ed2022-07-08 14:15:13 +0800138@@ -162,28 +237,42 @@ mt76_dma_add_buf(struct mt76_dev *dev, struct mt76_queue *q,
developer8cb3ac72022-07-04 10:55:14 +0800139 desc = &q->desc[idx];
140 entry = &q->entry[idx];
141
142- if (buf[0].skip_unmap)
143- entry->skip_buf0 = true;
144- entry->skip_buf1 = i == nbufs - 1;
145-
146- entry->dma_addr[0] = buf[0].addr;
147- entry->dma_len[0] = buf[0].len;
148-
149- ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, buf[0].len);
150- if (i < nbufs - 1) {
151- entry->dma_addr[1] = buf[1].addr;
152- entry->dma_len[1] = buf[1].len;
153- buf1 = buf[1].addr;
154- ctrl |= FIELD_PREP(MT_DMA_CTL_SD_LEN1, buf[1].len);
155- if (buf[1].skip_unmap)
156- entry->skip_buf1 = true;
157+ type = FIELD_GET(MT_QFLAG_WED_TYPE, q->flags);
158+ if (mtk_wed_device_active(wed) && type == MT76_WED_Q_RX) {
159+ struct mt76_txwi_cache *r = rxwi;
160+ int rx_token;
161+
162+ if (!r)
163+ return -ENOMEM;
164+
165+ rx_token = mt76_rx_token_consume(dev, (void *)skb, r, buf[0].addr);
166+
167+ buf1 |= FIELD_PREP(MT_DMA_CTL_TOKEN, rx_token);
168+ ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, MTK_WED_RX_PKT_SIZE);
169+ ctrl |= MT_DMA_CTL_TO_HOST;
170+ } else {
171+ if (buf[0].skip_unmap)
172+ entry->skip_buf0 = true;
173+ entry->skip_buf1 = i == nbufs - 1;
174+
175+ entry->dma_addr[0] = buf[0].addr;
176+ entry->dma_len[0] = buf[0].len;
177+
178+ ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, buf[0].len);
179+ if (i < nbufs - 1) {
180+ entry->dma_addr[1] = buf[1].addr;
181+ entry->dma_len[1] = buf[1].len;
182+ buf1 = buf[1].addr;
183+ ctrl |= FIELD_PREP(MT_DMA_CTL_SD_LEN1, buf[1].len);
184+ if (buf[1].skip_unmap)
185+ entry->skip_buf1 = true;
186+ }
187+ if (i == nbufs - 1)
188+ ctrl |= MT_DMA_CTL_LAST_SEC0;
189+ else if (i == nbufs - 2)
190+ ctrl |= MT_DMA_CTL_LAST_SEC1;
191 }
192
193- if (i == nbufs - 1)
194- ctrl |= MT_DMA_CTL_LAST_SEC0;
195- else if (i == nbufs - 2)
196- ctrl |= MT_DMA_CTL_LAST_SEC1;
197-
198 WRITE_ONCE(desc->buf0, cpu_to_le32(buf0));
199 WRITE_ONCE(desc->buf1, cpu_to_le32(buf1));
200 WRITE_ONCE(desc->info, cpu_to_le32(info));
developera3f86ed2022-07-08 14:15:13 +0800201@@ -272,33 +361,63 @@ mt76_dma_tx_cleanup(struct mt76_dev *dev, struct mt76_queue *q, bool flush)
developer8cb3ac72022-07-04 10:55:14 +0800202
203 static void *
204 mt76_dma_get_buf(struct mt76_dev *dev, struct mt76_queue *q, int idx,
205- int *len, u32 *info, bool *more)
206+ int *len, u32 *info, bool *more, bool *drop)
207 {
208 struct mt76_queue_entry *e = &q->entry[idx];
209 struct mt76_desc *desc = &q->desc[idx];
210 dma_addr_t buf_addr;
211 void *buf = e->buf;
212 int buf_len = SKB_WITH_OVERHEAD(q->buf_size);
213+ struct mtk_wed_device *wed = &dev->mmio.wed;
214+ int type;
215
216- buf_addr = e->dma_addr[0];
217 if (len) {
218 u32 ctl = le32_to_cpu(READ_ONCE(desc->ctrl));
219 *len = FIELD_GET(MT_DMA_CTL_SD_LEN0, ctl);
220 *more = !(ctl & MT_DMA_CTL_LAST_SEC0);
221 }
222
223- if (info)
224- *info = le32_to_cpu(desc->info);
225+ type = FIELD_GET(MT_QFLAG_WED_TYPE, q->flags);
226+ if (mtk_wed_device_active(wed) && type == MT76_WED_Q_RX) {
227+ u32 token;
228+ struct mt76_txwi_cache *r;
229+
230+ token = FIELD_GET(MT_DMA_CTL_TOKEN, desc->buf1);
231+
232+ r = mt76_rx_token_release(dev, token);
233+ if (!r)
234+ return NULL;
235+
236+ buf = page_frag_alloc(&q->rx_page, q->buf_size, GFP_ATOMIC);
237+ if (!buf)
238+ return NULL;
239+
240+ memcpy(buf, r->buf, MTK_WED_RX_PKT_SIZE);
241+ buf_addr = r->dma_addr;
242+ buf_len = MTK_WED_RX_PKT_SIZE;
243+ r->dma_addr = 0;
244+ //r->buf = NULL;
245+
246+ mt76_put_rxwi(dev, r);
247+
248+ if (desc->ctrl & (MT_DMA_CTL_TO_HOST_A | MT_DMA_CTL_DROP))
249+ *drop = true;
250+ } else {
251+ buf_addr = e->dma_addr[0];
252+ e->buf = NULL;
253+ }
254
255 dma_unmap_single(dev->dma_dev, buf_addr, buf_len, DMA_FROM_DEVICE);
256- e->buf = NULL;
257+
258+ if (info)
259+ *info = le32_to_cpu(desc->info);
260
261 return buf;
262 }
263
264 static void *
265 mt76_dma_dequeue(struct mt76_dev *dev, struct mt76_queue *q, bool flush,
266- int *len, u32 *info, bool *more)
267+ int *len, u32 *info, bool *more, bool *drop)
268 {
269 int idx = q->tail;
270
developera3f86ed2022-07-08 14:15:13 +0800271@@ -314,7 +433,7 @@ mt76_dma_dequeue(struct mt76_dev *dev, struct mt76_queue *q, bool flush,
developer8cb3ac72022-07-04 10:55:14 +0800272 q->tail = (q->tail + 1) % q->ndesc;
273 q->queued--;
274
275- return mt76_dma_get_buf(dev, q, idx, len, info, more);
276+ return mt76_dma_get_buf(dev, q, idx, len, info, more, drop);
277 }
278
279 static int
developera3f86ed2022-07-08 14:15:13 +0800280@@ -336,7 +455,7 @@ mt76_dma_tx_queue_skb_raw(struct mt76_dev *dev, struct mt76_queue *q,
developer8cb3ac72022-07-04 10:55:14 +0800281 buf.len = skb->len;
282
283 spin_lock_bh(&q->lock);
284- mt76_dma_add_buf(dev, q, &buf, 1, tx_info, skb, NULL);
285+ mt76_dma_add_buf(dev, q, &buf, 1, tx_info, skb, NULL, NULL);
286 mt76_dma_kick_queue(dev, q);
287 spin_unlock_bh(&q->lock);
288
developera3f86ed2022-07-08 14:15:13 +0800289@@ -413,7 +532,7 @@ mt76_dma_tx_queue_skb(struct mt76_dev *dev, struct mt76_queue *q,
developer8cb3ac72022-07-04 10:55:14 +0800290 goto unmap;
291
292 return mt76_dma_add_buf(dev, q, tx_info.buf, tx_info.nbuf,
293- tx_info.info, tx_info.skb, t);
294+ tx_info.info, tx_info.skb, t, NULL);
295
296 unmap:
297 for (n--; n > 0; n--)
developera3f86ed2022-07-08 14:15:13 +0800298@@ -448,6 +567,8 @@ mt76_dma_rx_fill(struct mt76_dev *dev, struct mt76_queue *q)
developer8cb3ac72022-07-04 10:55:14 +0800299 int frames = 0;
300 int len = SKB_WITH_OVERHEAD(q->buf_size);
301 int offset = q->buf_offset;
302+ struct mtk_wed_device *wed = &dev->mmio.wed;
developera3f86ed2022-07-08 14:15:13 +0800303+ struct page_frag_cache *rx_page;
developer8cb3ac72022-07-04 10:55:14 +0800304
305 if (!q->ndesc)
306 return 0;
developera3f86ed2022-07-08 14:15:13 +0800307@@ -456,10 +577,29 @@ mt76_dma_rx_fill(struct mt76_dev *dev, struct mt76_queue *q)
developer8cb3ac72022-07-04 10:55:14 +0800308
309 while (q->queued < q->ndesc - 1) {
310 struct mt76_queue_buf qbuf;
311+ int type = FIELD_GET(MT_QFLAG_WED_TYPE, q->flags);
312+ bool skip_alloc = false;
313+ struct mt76_txwi_cache *r = NULL;
314+
developera3f86ed2022-07-08 14:15:13 +0800315+ rx_page = &q->rx_page;
developer8cb3ac72022-07-04 10:55:14 +0800316+ if (mtk_wed_device_active(wed) && type == MT76_WED_Q_RX) {
developera3f86ed2022-07-08 14:15:13 +0800317+ rx_page = &wed->rx_page;
developer8cb3ac72022-07-04 10:55:14 +0800318+ r = mt76_get_rxwi(dev);
319+ if (!r)
320+ return -ENOMEM;
321+
322+ if (r->buf) {
323+ skip_alloc = true;
324+ len = MTK_WED_RX_PKT_SIZE;
325+ buf = r->buf;
326+ }
327+ }
328
329- buf = page_frag_alloc(&q->rx_page, q->buf_size, GFP_ATOMIC);
330- if (!buf)
331- break;
332+ if (!skip_alloc) {
developera3f86ed2022-07-08 14:15:13 +0800333+ buf = page_frag_alloc(rx_page, q->buf_size, GFP_ATOMIC);
developer8cb3ac72022-07-04 10:55:14 +0800334+ if (!buf)
335+ break;
336+ }
337
338 addr = dma_map_single(dev->dma_dev, buf, len, DMA_FROM_DEVICE);
339 if (unlikely(dma_mapping_error(dev->dma_dev, addr))) {
developera3f86ed2022-07-08 14:15:13 +0800340@@ -470,7 +610,7 @@ mt76_dma_rx_fill(struct mt76_dev *dev, struct mt76_queue *q)
developer8cb3ac72022-07-04 10:55:14 +0800341 qbuf.addr = addr + offset;
342 qbuf.len = len - offset;
343 qbuf.skip_unmap = false;
344- mt76_dma_add_buf(dev, q, &qbuf, 1, 0, buf, NULL);
345+ mt76_dma_add_buf(dev, q, &qbuf, 1, 0, buf, NULL, r);
346 frames++;
347 }
348
developera3f86ed2022-07-08 14:15:13 +0800349@@ -516,6 +656,11 @@ mt76_dma_wed_setup(struct mt76_dev *dev, struct mt76_queue *q)
developer8cb3ac72022-07-04 10:55:14 +0800350 if (!ret)
351 q->wed_regs = wed->txfree_ring.reg_base;
352 break;
353+ case MT76_WED_Q_RX:
354+ ret = mtk_wed_device_rx_ring_setup(wed, ring, q->regs);
355+ if (!ret)
356+ q->wed_regs = wed->rx_ring[ring].reg_base;
357+ break;
358 default:
359 ret = -EINVAL;
360 }
developera3f86ed2022-07-08 14:15:13 +0800361@@ -531,7 +676,8 @@ mt76_dma_alloc_queue(struct mt76_dev *dev, struct mt76_queue *q,
developer8cb3ac72022-07-04 10:55:14 +0800362 int idx, int n_desc, int bufsize,
363 u32 ring_base)
364 {
365- int ret, size;
366+ int ret, size, type;
367+ struct mtk_wed_device *wed = &dev->mmio.wed;
368
369 spin_lock_init(&q->lock);
370 spin_lock_init(&q->cleanup_lock);
developera3f86ed2022-07-08 14:15:13 +0800371@@ -541,6 +687,11 @@ mt76_dma_alloc_queue(struct mt76_dev *dev, struct mt76_queue *q,
developer8cb3ac72022-07-04 10:55:14 +0800372 q->buf_size = bufsize;
373 q->hw_idx = idx;
374
375+ type = FIELD_GET(MT_QFLAG_WED_TYPE, q->flags);
376+ if (mtk_wed_device_active(wed) && type == MT76_WED_Q_RX)
377+ q->buf_size = SKB_DATA_ALIGN(NET_SKB_PAD + MTK_WED_RX_PKT_SIZE) +
378+ SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
379+
380 size = q->ndesc * sizeof(struct mt76_desc);
381 q->desc = dmam_alloc_coherent(dev->dma_dev, size, &q->desc_dma, GFP_KERNEL);
382 if (!q->desc)
developera3f86ed2022-07-08 14:15:13 +0800383@@ -573,7 +724,7 @@ mt76_dma_rx_cleanup(struct mt76_dev *dev, struct mt76_queue *q)
developer8cb3ac72022-07-04 10:55:14 +0800384
385 spin_lock_bh(&q->lock);
386 do {
387- buf = mt76_dma_dequeue(dev, q, true, NULL, NULL, &more);
388+ buf = mt76_dma_dequeue(dev, q, true, NULL, NULL, &more, NULL);
389 if (!buf)
390 break;
391
developera3f86ed2022-07-08 14:15:13 +0800392@@ -614,7 +765,7 @@ mt76_dma_rx_reset(struct mt76_dev *dev, enum mt76_rxq_id qid)
developer8cb3ac72022-07-04 10:55:14 +0800393
394 static void
395 mt76_add_fragment(struct mt76_dev *dev, struct mt76_queue *q, void *data,
396- int len, bool more)
397+ int len, bool more, u32 info)
398 {
399 struct sk_buff *skb = q->rx_head;
400 struct skb_shared_info *shinfo = skb_shinfo(skb);
developera3f86ed2022-07-08 14:15:13 +0800401@@ -634,7 +785,7 @@ mt76_add_fragment(struct mt76_dev *dev, struct mt76_queue *q, void *data,
developer8cb3ac72022-07-04 10:55:14 +0800402
403 q->rx_head = NULL;
404 if (nr_frags < ARRAY_SIZE(shinfo->frags))
405- dev->drv->rx_skb(dev, q - dev->q_rx, skb);
406+ dev->drv->rx_skb(dev, q - dev->q_rx, skb, info);
407 else
408 dev_kfree_skb(skb);
409 }
developera3f86ed2022-07-08 14:15:13 +0800410@@ -655,6 +806,7 @@ mt76_dma_rx_process(struct mt76_dev *dev, struct mt76_queue *q, int budget)
developer8cb3ac72022-07-04 10:55:14 +0800411 }
412
413 while (done < budget) {
414+ bool drop = false;
415 u32 info;
416
417 if (check_ddone) {
developera3f86ed2022-07-08 14:15:13 +0800418@@ -665,10 +817,13 @@ mt76_dma_rx_process(struct mt76_dev *dev, struct mt76_queue *q, int budget)
developer8cb3ac72022-07-04 10:55:14 +0800419 break;
420 }
421
422- data = mt76_dma_dequeue(dev, q, false, &len, &info, &more);
423+ data = mt76_dma_dequeue(dev, q, false, &len, &info, &more, &drop);
424 if (!data)
425 break;
426
427+ if (drop)
428+ goto free_frag;
429+
430 if (q->rx_head)
431 data_len = q->buf_size;
432 else
developera3f86ed2022-07-08 14:15:13 +0800433@@ -681,7 +836,7 @@ mt76_dma_rx_process(struct mt76_dev *dev, struct mt76_queue *q, int budget)
developer8cb3ac72022-07-04 10:55:14 +0800434 }
435
436 if (q->rx_head) {
437- mt76_add_fragment(dev, q, data, len, more);
438+ mt76_add_fragment(dev, q, data, len, more, info);
439 continue;
440 }
441
developera3f86ed2022-07-08 14:15:13 +0800442@@ -708,7 +863,7 @@ mt76_dma_rx_process(struct mt76_dev *dev, struct mt76_queue *q, int budget)
developer8cb3ac72022-07-04 10:55:14 +0800443 continue;
444 }
445
446- dev->drv->rx_skb(dev, q - dev->q_rx, skb);
447+ dev->drv->rx_skb(dev, q - dev->q_rx, skb, info);
448 continue;
449
450 free_frag:
developerd59e4772022-07-14 13:48:49 +0800451@@ -785,7 +940,7 @@ EXPORT_SYMBOL_GPL(mt76_dma_attach);
developera3f86ed2022-07-08 14:15:13 +0800452
453 void mt76_dma_cleanup(struct mt76_dev *dev)
454 {
455- int i;
developera3f86ed2022-07-08 14:15:13 +0800456+ int i, type;
developerd59e4772022-07-14 13:48:49 +0800457
developera3f86ed2022-07-08 14:15:13 +0800458 mt76_worker_disable(&dev->tx_worker);
459 netif_napi_del(&dev->tx_napi);
developera3f86ed2022-07-08 14:15:13 +0800460@@ -801,12 +956,17 @@ void mt76_dma_cleanup(struct mt76_dev *dev)
461
462 mt76_for_each_q_rx(dev, i) {
463 netif_napi_del(&dev->napi[i]);
464- mt76_dma_rx_cleanup(dev, &dev->q_rx[i]);
465+ type = FIELD_GET(MT_QFLAG_WED_TYPE, dev->q_rx[i].flags);
466+ if (type != MT76_WED_Q_RX)
467+ mt76_dma_rx_cleanup(dev, &dev->q_rx[i]);
468 }
469
470 mt76_free_pending_txwi(dev);
471+ mt76_free_pending_rxwi(dev);
472
473 if (mtk_wed_device_active(&dev->mmio.wed))
474 mtk_wed_device_detach(&dev->mmio.wed);
475+
476+ mt76_free_pending_rxwi(dev);
477 }
478 EXPORT_SYMBOL_GPL(mt76_dma_cleanup);
developer8cb3ac72022-07-04 10:55:14 +0800479diff --git a/dma.h b/dma.h
developerd59e4772022-07-14 13:48:49 +0800480index fdf786f9..90370d12 100644
developer8cb3ac72022-07-04 10:55:14 +0800481--- a/dma.h
482+++ b/dma.h
483@@ -16,6 +16,16 @@
484 #define MT_DMA_CTL_LAST_SEC0 BIT(30)
485 #define MT_DMA_CTL_DMA_DONE BIT(31)
486
487+#define MT_DMA_CTL_TO_HOST BIT(8)
488+#define MT_DMA_CTL_TO_HOST_A BIT(12)
489+#define MT_DMA_CTL_DROP BIT(14)
490+
491+#define MT_DMA_CTL_TOKEN GENMASK(31, 16)
492+
493+#define MT_DMA_PPE_CPU_REASON GENMASK(15, 11)
494+#define MT_DMA_PPE_ENTRY GENMASK(30, 16)
495+#define MT_DMA_INFO_PPE_VLD BIT(31)
496+
497 #define MT_DMA_HDR_LEN 4
498 #define MT_RX_INFO_LEN 4
499 #define MT_FCE_INFO_LEN 4
500diff --git a/mac80211.c b/mac80211.c
developerd59e4772022-07-14 13:48:49 +0800501index af2c09ad..fa5ce6ec 100644
developer8cb3ac72022-07-04 10:55:14 +0800502--- a/mac80211.c
503+++ b/mac80211.c
504@@ -594,11 +594,14 @@ mt76_alloc_device(struct device *pdev, unsigned int size,
505 BIT(NL80211_IFTYPE_ADHOC);
506
507 spin_lock_init(&dev->token_lock);
508+ spin_lock_init(&dev->rx_token_lock);
509 idr_init(&dev->token);
510+ idr_init(&dev->rx_token);
511
512 INIT_LIST_HEAD(&dev->wcid_list);
513
514 INIT_LIST_HEAD(&dev->txwi_cache);
515+ INIT_LIST_HEAD(&dev->rxwi_cache);
516 dev->token_size = dev->drv->token_size;
517
518 for (i = 0; i < ARRAY_SIZE(dev->q_rx); i++)
519@@ -1296,7 +1299,10 @@ void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q,
520
521 while ((skb = __skb_dequeue(&dev->rx_skb[q])) != NULL) {
522 mt76_check_sta(dev, skb);
523- mt76_rx_aggr_reorder(skb, &frames);
524+ if (mtk_wed_device_active(&dev->mmio.wed))
525+ __skb_queue_tail(&frames, skb);
526+ else
527+ mt76_rx_aggr_reorder(skb, &frames);
528 }
529
530 mt76_rx_complete(dev, &frames, napi);
531diff --git a/mt76.h b/mt76.h
developerd59e4772022-07-14 13:48:49 +0800532index 49314895..9162213a 100644
developer8cb3ac72022-07-04 10:55:14 +0800533--- a/mt76.h
534+++ b/mt76.h
535@@ -20,6 +20,8 @@
536
537 #define MT_MCU_RING_SIZE 32
538 #define MT_RX_BUF_SIZE 2048
539+#define MTK_WED_RX_PKT_SIZE 1700
540+
541 #define MT_SKB_HEAD_LEN 256
542
543 #define MT_MAX_NON_AQL_PKT 16
544@@ -35,6 +37,7 @@
545 FIELD_PREP(MT_QFLAG_WED_TYPE, _type) | \
546 FIELD_PREP(MT_QFLAG_WED_RING, _n))
547 #define MT_WED_Q_TX(_n) __MT_WED_Q(MT76_WED_Q_TX, _n)
548+#define MT_WED_Q_RX(_n) __MT_WED_Q(MT76_WED_Q_RX, _n)
549 #define MT_WED_Q_TXFREE __MT_WED_Q(MT76_WED_Q_TXFREE, 0)
550
551 struct mt76_dev;
552@@ -56,6 +59,7 @@ enum mt76_bus_type {
553 enum mt76_wed_type {
554 MT76_WED_Q_TX,
555 MT76_WED_Q_TXFREE,
556+ MT76_WED_Q_RX,
557 };
558
559 struct mt76_bus_ops {
560@@ -305,7 +309,10 @@ struct mt76_txwi_cache {
561 struct list_head list;
562 dma_addr_t dma_addr;
563
564- struct sk_buff *skb;
565+ union {
566+ void *buf;
567+ struct sk_buff *skb;
568+ };
569 };
570
571 struct mt76_rx_tid {
572@@ -403,7 +410,7 @@ struct mt76_driver_ops {
573 bool (*rx_check)(struct mt76_dev *dev, void *data, int len);
574
575 void (*rx_skb)(struct mt76_dev *dev, enum mt76_rxq_id q,
576- struct sk_buff *skb);
577+ struct sk_buff *skb, u32 info);
578
579 void (*rx_poll_complete)(struct mt76_dev *dev, enum mt76_rxq_id q);
580
581@@ -747,6 +754,7 @@ struct mt76_dev {
582 struct ieee80211_hw *hw;
583
584 spinlock_t lock;
585+ spinlock_t wed_lock;
586 spinlock_t cc_lock;
587
588 u32 cur_cc_bss_rx;
589@@ -772,6 +780,7 @@ struct mt76_dev {
590 struct sk_buff_head rx_skb[__MT_RXQ_MAX];
591
592 struct list_head txwi_cache;
593+ struct list_head rxwi_cache;
594 struct mt76_queue *q_mcu[__MT_MCUQ_MAX];
595 struct mt76_queue q_rx[__MT_RXQ_MAX];
596 const struct mt76_queue_ops *queue_ops;
597@@ -785,6 +794,9 @@ struct mt76_dev {
598 u16 wed_token_count;
599 u16 token_count;
600 u16 token_size;
601+ u16 rx_token_size;
602+ spinlock_t rx_token_lock;
603+ struct idr rx_token;
604
605 wait_queue_head_t tx_wait;
606 /* spinclock used to protect wcid pktid linked list */
developerd59e4772022-07-14 13:48:49 +0800607@@ -1352,6 +1364,8 @@ mt76_tx_status_get_hw(struct mt76_dev *dev, struct sk_buff *skb)
developer8cb3ac72022-07-04 10:55:14 +0800608 }
609
610 void mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t);
611+void mt76_put_rxwi(struct mt76_dev *dev, struct mt76_txwi_cache *t);
612+struct mt76_txwi_cache *mt76_get_rxwi(struct mt76_dev *dev);
613 void mt76_rx_complete(struct mt76_dev *dev, struct sk_buff_head *frames,
614 struct napi_struct *napi);
615 void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q,
developerd59e4772022-07-14 13:48:49 +0800616@@ -1496,6 +1510,12 @@ struct mt76_txwi_cache *
developer8cb3ac72022-07-04 10:55:14 +0800617 mt76_token_release(struct mt76_dev *dev, int token, bool *wake);
618 int mt76_token_consume(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi);
619 void __mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked);
620+int mt76_rx_token_consume(struct mt76_dev *dev, void *ptr,
621+ struct mt76_txwi_cache *r, dma_addr_t phys);
622+void skb_trace(const struct sk_buff *skb, bool full_pkt);
623+
624+struct mt76_txwi_cache *
625+mt76_rx_token_release(struct mt76_dev *dev, int token);
626
627 static inline void mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked)
628 {
629diff --git a/mt7603/dma.c b/mt7603/dma.c
developerd59e4772022-07-14 13:48:49 +0800630index 590cff9d..2ff71c53 100644
developer8cb3ac72022-07-04 10:55:14 +0800631--- a/mt7603/dma.c
632+++ b/mt7603/dma.c
633@@ -69,7 +69,7 @@ free:
634 }
635
636 void mt7603_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
637- struct sk_buff *skb)
638+ struct sk_buff *skb, u32 info)
639 {
640 struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76);
641 __le32 *rxd = (__le32 *)skb->data;
642diff --git a/mt7603/mt7603.h b/mt7603/mt7603.h
developerd59e4772022-07-14 13:48:49 +0800643index 0fd46d90..f2ce22ae 100644
developer8cb3ac72022-07-04 10:55:14 +0800644--- a/mt7603/mt7603.h
645+++ b/mt7603/mt7603.h
646@@ -244,7 +244,7 @@ int mt7603_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
647 void mt7603_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue_entry *e);
648
649 void mt7603_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
650- struct sk_buff *skb);
651+ struct sk_buff *skb, u32 info);
652 void mt7603_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q);
653 void mt7603_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps);
654 int mt7603_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif,
655diff --git a/mt7615/mac.c b/mt7615/mac.c
developerd59e4772022-07-14 13:48:49 +0800656index 37286276..14cdd9a2 100644
developer8cb3ac72022-07-04 10:55:14 +0800657--- a/mt7615/mac.c
658+++ b/mt7615/mac.c
developerf50c1802022-07-05 20:35:53 +0800659@@ -1648,7 +1648,7 @@ bool mt7615_rx_check(struct mt76_dev *mdev, void *data, int len)
developer8cb3ac72022-07-04 10:55:14 +0800660 EXPORT_SYMBOL_GPL(mt7615_rx_check);
661
662 void mt7615_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
663- struct sk_buff *skb)
664+ struct sk_buff *skb, u32 info)
665 {
666 struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
667 __le32 *rxd = (__le32 *)skb->data;
668diff --git a/mt7615/mt7615.h b/mt7615/mt7615.h
developerd59e4772022-07-14 13:48:49 +0800669index 25880d1a..983469c7 100644
developer8cb3ac72022-07-04 10:55:14 +0800670--- a/mt7615/mt7615.h
671+++ b/mt7615/mt7615.h
developerf50c1802022-07-05 20:35:53 +0800672@@ -511,7 +511,7 @@ void mt7615_tx_worker(struct mt76_worker *w);
developer8cb3ac72022-07-04 10:55:14 +0800673 void mt7615_tx_token_put(struct mt7615_dev *dev);
674 bool mt7615_rx_check(struct mt76_dev *mdev, void *data, int len);
675 void mt7615_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
676- struct sk_buff *skb);
677+ struct sk_buff *skb, u32 info);
678 void mt7615_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps);
679 int mt7615_mac_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif,
680 struct ieee80211_sta *sta);
681diff --git a/mt76_connac_mcu.c b/mt76_connac_mcu.c
developerd59e4772022-07-14 13:48:49 +0800682index cd350689..24548469 100644
developer8cb3ac72022-07-04 10:55:14 +0800683--- a/mt76_connac_mcu.c
684+++ b/mt76_connac_mcu.c
685@@ -1190,6 +1190,7 @@ int mt76_connac_mcu_sta_ba(struct mt76_dev *dev, struct mt76_vif *mvif,
686 int cmd, bool enable, bool tx)
687 {
688 struct mt76_wcid *wcid = (struct mt76_wcid *)params->sta->drv_priv;
689+ struct mtk_wed_device *wed = &dev->mmio.wed;
690 struct wtbl_req_hdr *wtbl_hdr;
691 struct tlv *sta_wtbl;
692 struct sk_buff *skb;
developerf50c1802022-07-05 20:35:53 +0800693@@ -1210,6 +1211,8 @@ int mt76_connac_mcu_sta_ba(struct mt76_dev *dev, struct mt76_vif *mvif,
developer8cb3ac72022-07-04 10:55:14 +0800694 mt76_connac_mcu_wtbl_ba_tlv(dev, skb, params, enable, tx, sta_wtbl,
695 wtbl_hdr);
696
developerf50c1802022-07-05 20:35:53 +0800697+ if (mtk_wed_device_active(wed) && wed->ver > MTK_WED_V1)
developer6adfa0e2022-07-06 16:25:53 +0800698+ mtk_wed_device_update_msg(wed, WED_WO_STA_REC, skb->data, skb->len);
developer8cb3ac72022-07-04 10:55:14 +0800699 ret = mt76_mcu_skb_send_msg(dev, skb, cmd, true);
700 if (ret)
701 return ret;
developerf50c1802022-07-05 20:35:53 +0800702@@ -1220,6 +1223,8 @@ int mt76_connac_mcu_sta_ba(struct mt76_dev *dev, struct mt76_vif *mvif,
developer8cb3ac72022-07-04 10:55:14 +0800703
704 mt76_connac_mcu_sta_ba_tlv(skb, params, enable, tx);
705
developerf50c1802022-07-05 20:35:53 +0800706+ if (mtk_wed_device_active(wed) && wed->ver > MTK_WED_V1)
707+ mtk_wed_device_update_msg(wed, WED_WO_STA_REC, skb->data, skb->len);
developer8cb3ac72022-07-04 10:55:14 +0800708 return mt76_mcu_skb_send_msg(dev, skb, cmd, true);
709 }
710 EXPORT_SYMBOL_GPL(mt76_connac_mcu_sta_ba);
developerf50c1802022-07-05 20:35:53 +0800711@@ -2634,6 +2639,7 @@ int mt76_connac_mcu_add_key(struct mt76_dev *dev, struct ieee80211_vif *vif,
developer8cb3ac72022-07-04 10:55:14 +0800712 struct mt76_wcid *wcid, enum set_key_cmd cmd)
713 {
714 struct mt76_vif *mvif = (struct mt76_vif *)vif->drv_priv;
715+ struct mtk_wed_device *wed = &dev->mmio.wed;
716 struct sk_buff *skb;
717 int ret;
718
developerf50c1802022-07-05 20:35:53 +0800719@@ -2645,6 +2651,9 @@ int mt76_connac_mcu_add_key(struct mt76_dev *dev, struct ieee80211_vif *vif,
developer8cb3ac72022-07-04 10:55:14 +0800720 if (ret)
721 return ret;
722
developerf50c1802022-07-05 20:35:53 +0800723+ if (mtk_wed_device_active(wed) && wed->ver > MTK_WED_V1)
developer8cb3ac72022-07-04 10:55:14 +0800724+ mtk_wed_device_update_msg(wed, WED_WO_STA_REC, skb->data, skb->len);
725+
726 return mt76_mcu_skb_send_msg(dev, skb, mcu_cmd, true);
727 }
728 EXPORT_SYMBOL_GPL(mt76_connac_mcu_add_key);
729diff --git a/mt76x02.h b/mt76x02.h
developerd59e4772022-07-14 13:48:49 +0800730index f76fd22e..0b872af1 100644
developer8cb3ac72022-07-04 10:55:14 +0800731--- a/mt76x02.h
732+++ b/mt76x02.h
733@@ -173,7 +173,7 @@ int mt76x02_set_rts_threshold(struct ieee80211_hw *hw, u32 val);
734 void mt76x02_remove_hdr_pad(struct sk_buff *skb, int len);
735 bool mt76x02_tx_status_data(struct mt76_dev *mdev, u8 *update);
736 void mt76x02_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
737- struct sk_buff *skb);
738+ struct sk_buff *skb, u32 info);
739 void mt76x02_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q);
740 irqreturn_t mt76x02_irq_handler(int irq, void *dev_instance);
741 void mt76x02_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control,
742diff --git a/mt76x02_txrx.c b/mt76x02_txrx.c
developerd59e4772022-07-14 13:48:49 +0800743index 96fdf423..bf24d3e0 100644
developer8cb3ac72022-07-04 10:55:14 +0800744--- a/mt76x02_txrx.c
745+++ b/mt76x02_txrx.c
746@@ -33,7 +33,7 @@ void mt76x02_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control,
747 EXPORT_SYMBOL_GPL(mt76x02_tx);
748
749 void mt76x02_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
750- struct sk_buff *skb)
751+ struct sk_buff *skb, u32 info)
752 {
753 struct mt76x02_dev *dev = container_of(mdev, struct mt76x02_dev, mt76);
754 void *rxwi = skb->data;
755diff --git a/mt7915/dma.c b/mt7915/dma.c
developerd59e4772022-07-14 13:48:49 +0800756index 71223221..ac98e01b 100644
developer8cb3ac72022-07-04 10:55:14 +0800757--- a/mt7915/dma.c
758+++ b/mt7915/dma.c
759@@ -376,6 +376,8 @@ int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2)
760 FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_TX0, 18) |
761 FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_TX1, 19) |
762 FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_RX1, 1));
763+ mt76_rmw(dev, MT_WFDMA0_EXT0_CFG, MT_WFDMA0_EXT0_RXWB_KEEP,
764+ MT_WFDMA0_EXT0_RXWB_KEEP);
765 } else {
766 mt76_wr(dev, MT_WFDMA_WED_RING_CONTROL,
767 FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_TX0, 18) |
developerf50c1802022-07-05 20:35:53 +0800768@@ -451,6 +453,10 @@ int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2)
developer8cb3ac72022-07-04 10:55:14 +0800769
770 /* rx data queue for band0 */
771 if (!dev->phy.band_idx) {
developerf50c1802022-07-05 20:35:53 +0800772+ if (mtk_wed_device_active(&dev->mt76.mmio.wed) &&
773+ dev->mt76.mmio.wed.ver > MTK_WED_V1)
developer8cb3ac72022-07-04 10:55:14 +0800774+ dev->mt76.q_rx[MT_RXQ_MAIN].flags = MT_WED_Q_RX(MT7915_RXQ_BAND0);
775+
776 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN],
777 MT_RXQ_ID(MT_RXQ_MAIN),
778 MT7915_RX_RING_SIZE,
developerf50c1802022-07-05 20:35:53 +0800779@@ -482,6 +488,10 @@ int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2)
developer8cb3ac72022-07-04 10:55:14 +0800780
781 if (dev->dbdc_support || dev->phy.band_idx) {
782 /* rx data queue for band1 */
developerf50c1802022-07-05 20:35:53 +0800783+ if (mtk_wed_device_active(&dev->mt76.mmio.wed) &&
784+ dev->mt76.mmio.wed.ver > MTK_WED_V1)
developer8cb3ac72022-07-04 10:55:14 +0800785+ dev->mt76.q_rx[MT_RXQ_EXT].flags = MT_WED_Q_RX(MT7915_RXQ_BAND1);
786+
787 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_EXT],
788 MT_RXQ_ID(MT_RXQ_EXT),
789 MT7915_RX_RING_SIZE,
790diff --git a/mt7915/mac.c b/mt7915/mac.c
developerd59e4772022-07-14 13:48:49 +0800791index db21d83e..1f8e1230 100644
developer8cb3ac72022-07-04 10:55:14 +0800792--- a/mt7915/mac.c
793+++ b/mt7915/mac.c
794@@ -217,7 +217,7 @@ static void mt7915_mac_sta_poll(struct mt7915_dev *dev)
795 }
796
797 static int
798-mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
799+mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb, enum mt76_rxq_id q, u32 info)
800 {
801 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
802 struct mt76_phy *mphy = &dev->mt76.phy;
developera3f86ed2022-07-08 14:15:13 +0800803@@ -234,7 +234,7 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
804 bool unicast, insert_ccmp_hdr = false;
805 u8 remove_pad, amsdu_info;
806 u8 mode = 0, qos_ctl = 0;
807- struct mt7915_sta *msta;
808+ struct mt7915_sta *msta = NULL;
809 bool hdr_trans;
810 u16 hdr_gap;
811 u16 seq_ctrl = 0;
developer8cb3ac72022-07-04 10:55:14 +0800812@@ -494,6 +494,27 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
813 #endif
814 } else {
815 status->flag |= RX_FLAG_8023;
developera3f86ed2022-07-08 14:15:13 +0800816+ if (msta && msta->vif) {
developer8cb3ac72022-07-04 10:55:14 +0800817+ struct mtk_wed_device *wed;
818+ int type;
819+
820+ wed = &dev->mt76.mmio.wed;
821+ type = FIELD_GET(MT_QFLAG_WED_TYPE, dev->mt76.q_rx[q].flags);
822+ if ((mtk_wed_device_active(wed) && type == MT76_WED_Q_RX) &&
developera3f86ed2022-07-08 14:15:13 +0800823+ (info & MT_DMA_INFO_PPE_VLD)) {
developer8cb3ac72022-07-04 10:55:14 +0800824+ struct ieee80211_vif *vif;
825+ u32 hash, reason;
826+
827+ vif = container_of((void *)msta->vif, struct ieee80211_vif,
developera3f86ed2022-07-08 14:15:13 +0800828+ drv_priv);
developer8cb3ac72022-07-04 10:55:14 +0800829+
830+ skb->dev = ieee80211_vif_to_netdev(vif);
831+ reason = FIELD_GET(MT_DMA_PPE_CPU_REASON, info);
832+ hash = FIELD_GET(MT_DMA_PPE_ENTRY, info);
833+
834+ mtk_wed_device_ppe_check(wed, skb, reason, hash);
835+ }
836+ }
837 }
838
839 if (rxv && mode >= MT_PHY_TYPE_HE_SU && !(status->flag & RX_FLAG_8023))
developera3f86ed2022-07-08 14:15:13 +0800840@@ -840,6 +861,80 @@ u32 mt7915_wed_init_buf(void *ptr, dma_addr_t phys, int token_id)
developer8cb3ac72022-07-04 10:55:14 +0800841 return MT_TXD_TXP_BUF_SIZE;
842 }
843
844+u32
845+mt7915_wed_init_rx_buf(struct mtk_wed_device *wed, int pkt_num)
846+{
847+ struct mtk_rxbm_desc *desc = wed->rx_buf_ring.desc;
848+ struct mt7915_dev *dev;
849+ dma_addr_t buf_phys;
850+ void *buf;
851+ int i, token, buf_size;
852+
853+ buf_size = SKB_DATA_ALIGN(NET_SKB_PAD + wed->wlan.rx_pkt_size) +
854+ SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
855+
856+ dev = container_of(wed, struct mt7915_dev, mt76.mmio.wed);
857+ for (i = 0; i < pkt_num; i++) {
858+ struct mt76_txwi_cache *r = mt76_get_rxwi(&dev->mt76);
859+
860+ buf = page_frag_alloc(&wed->rx_page, buf_size, GFP_ATOMIC);
861+ if (!buf)
862+ return -ENOMEM;
863+
864+ buf_phys = dma_map_single(dev->mt76.dma_dev, buf, wed->wlan.rx_pkt_size,
865+ DMA_TO_DEVICE);
866+
867+ if (unlikely(dma_mapping_error(dev->mt76.dev, buf_phys))) {
868+ skb_free_frag(buf);
869+ break;
870+ }
871+
872+ desc->buf0 = buf_phys;
873+
874+ token = mt76_rx_token_consume(&dev->mt76, buf, r, buf_phys);
875+
876+ desc->token |= FIELD_PREP(MT_DMA_CTL_TOKEN, token);
877+ desc++;
878+ }
879+
880+ return 0;
881+}
882+
883+void mt7915_wed_release_rx_buf(struct mtk_wed_device *wed)
884+{
885+ struct mt76_txwi_cache *rxwi;
886+ struct mt7915_dev *dev;
developera3f86ed2022-07-08 14:15:13 +0800887+ struct page *page;
developer8cb3ac72022-07-04 10:55:14 +0800888+ int token;
889+
890+ dev = container_of(wed, struct mt7915_dev, mt76.mmio.wed);
891+
892+ for(token = 0; token < dev->mt76.rx_token_size; token++) {
893+ rxwi = mt76_rx_token_release(&dev->mt76, token);
894+ if(!rxwi)
895+ continue;
896+
developera3f86ed2022-07-08 14:15:13 +0800897+ if(!rxwi->buf)
898+ continue;
899+
developer8cb3ac72022-07-04 10:55:14 +0800900+ dma_unmap_single(dev->mt76.dma_dev, rxwi->dma_addr,
901+ wed->wlan.rx_pkt_size, DMA_FROM_DEVICE);
902+ skb_free_frag(rxwi->buf);
903+ rxwi->buf = NULL;
904+
905+ mt76_put_rxwi(&dev->mt76, rxwi);
906+ }
developera3f86ed2022-07-08 14:15:13 +0800907+
908+ if (wed->rx_page.va)
909+ return;
910+
911+ page = virt_to_page(wed->rx_page.va);
912+ __page_frag_cache_drain(page, wed->rx_page.pagecnt_bias);
913+ memset(&wed->rx_page, 0, sizeof(wed->rx_page));
914+
developer8cb3ac72022-07-04 10:55:14 +0800915+ return;
916+}
917+
918 static void
919 mt7915_tx_check_aggr(struct ieee80211_sta *sta, __le32 *txwi)
920 {
developera3f86ed2022-07-08 14:15:13 +0800921@@ -1120,7 +1215,7 @@ bool mt7915_rx_check(struct mt76_dev *mdev, void *data, int len)
developer8cb3ac72022-07-04 10:55:14 +0800922 }
923
924 void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
925- struct sk_buff *skb)
926+ struct sk_buff *skb, u32 info)
927 {
928 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
929 __le32 *rxd = (__le32 *)skb->data;
developera3f86ed2022-07-08 14:15:13 +0800930@@ -1154,7 +1249,7 @@ void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
developer8cb3ac72022-07-04 10:55:14 +0800931 dev_kfree_skb(skb);
932 break;
933 case PKT_TYPE_NORMAL:
934- if (!mt7915_mac_fill_rx(dev, skb)) {
935+ if (!mt7915_mac_fill_rx(dev, skb, q, info)) {
936 mt76_rx(&dev->mt76, q, skb);
937 return;
938 }
939diff --git a/mt7915/mcu.c b/mt7915/mcu.c
developerd59e4772022-07-14 13:48:49 +0800940index 674cbc4e..0ae6daf3 100644
developer8cb3ac72022-07-04 10:55:14 +0800941--- a/mt7915/mcu.c
942+++ b/mt7915/mcu.c
developerd59e4772022-07-14 13:48:49 +0800943@@ -1723,6 +1723,7 @@ int mt7915_mcu_add_sta(struct mt7915_dev *dev, struct ieee80211_vif *vif,
developer8cb3ac72022-07-04 10:55:14 +0800944 struct ieee80211_sta *sta, bool enable)
945 {
946 struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv;
947+ struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
948 struct mt7915_sta *msta;
949 struct sk_buff *skb;
950 int ret;
developerd59e4772022-07-14 13:48:49 +0800951@@ -1775,6 +1776,8 @@ int mt7915_mcu_add_sta(struct mt7915_dev *dev, struct ieee80211_vif *vif,
developer8cb3ac72022-07-04 10:55:14 +0800952 return ret;
953 }
954 out:
developerf50c1802022-07-05 20:35:53 +0800955+ if (mtk_wed_device_active(wed) && wed->ver > MTK_WED_V1)
956+ mtk_wed_device_update_msg(wed, WED_WO_STA_REC, skb->data, skb->len);
developer8cb3ac72022-07-04 10:55:14 +0800957 return mt76_mcu_skb_send_msg(&dev->mt76, skb,
958 MCU_EXT_CMD(STA_REC_UPDATE), true);
959 }
960diff --git a/mt7915/mmio.c b/mt7915/mmio.c
developerd59e4772022-07-14 13:48:49 +0800961index b4a3120d..08ff556e 100644
developer8cb3ac72022-07-04 10:55:14 +0800962--- a/mt7915/mmio.c
963+++ b/mt7915/mmio.c
964@@ -28,6 +28,9 @@ static const u32 mt7915_reg[] = {
965 [FW_EXCEPTION_ADDR] = 0x219848,
966 [SWDEF_BASE_ADDR] = 0x41f200,
967 [EXCEPTION_BASE_ADDR] = 0x219848,
968+ [WED_TX_RING] = 0xd7300,
969+ [WED_RX_RING] = 0xd7410,
970+ [WED_RX_DATA_RING] = 0xd4500,
971 };
972
973 static const u32 mt7916_reg[] = {
974@@ -45,6 +48,9 @@ static const u32 mt7916_reg[] = {
975 [FW_EXCEPTION_ADDR] = 0x022050bc,
976 [SWDEF_BASE_ADDR] = 0x411400,
977 [EXCEPTION_BASE_ADDR] = 0x022050BC,
978+ [WED_TX_RING] = 0xd7300,
979+ [WED_RX_RING] = 0xd7410,
980+ [WED_RX_DATA_RING] = 0xd4540,
981 };
982
983 static const u32 mt7986_reg[] = {
984@@ -62,6 +68,9 @@ static const u32 mt7986_reg[] = {
985 [FW_EXCEPTION_ADDR] = 0x02204ffc,
986 [SWDEF_BASE_ADDR] = 0x411400,
987 [EXCEPTION_BASE_ADDR] = 0x02204FFC,
988+ [WED_TX_RING] = 0x24420,
989+ [WED_RX_RING] = 0x24520,
990+ [WED_RX_DATA_RING] = 0x24540,
991 };
992
993 static const u32 mt7915_offs[] = {
developerf50c1802022-07-05 20:35:53 +0800994@@ -710,6 +719,7 @@ mt7915_pci_wed_init(struct mt7915_dev *dev, struct device *pdev, int *irq)
995 wed->wlan.bus_type = MTK_BUS_TYPE_PCIE;
996 wed->wlan.wpdma_int = base + MT_INT_WED_SOURCE_CSR;
997 wed->wlan.wpdma_mask = base + MT_INT_WED_MASK_CSR;
998+ wed->wlan.wpdma_phys = base + MT_WFDMA_EXT_CSR_BASE;
999 } else {
1000 struct platform_device *plat_dev;
1001 struct resource *res;
1002@@ -722,12 +732,19 @@ mt7915_pci_wed_init(struct mt7915_dev *dev, struct device *pdev, int *irq)
developer8cb3ac72022-07-04 10:55:14 +08001003 wed->wlan.wpdma_int = base + MT_INT_SOURCE_CSR;
1004 wed->wlan.wpdma_mask = base + MT_INT_MASK_CSR;
1005 }
1006+ wed->wlan.rx_pkt = MT7915_WED_RX_TOKEN_SIZE;
1007+ wed->wlan.phy_base = base;
1008 wed->wlan.wpdma_tx = base + MT_TXQ_WED_RING_BASE;
1009 wed->wlan.wpdma_txfree = base + MT_RXQ_WED_RING_BASE;
1010+ wed->wlan.wpdma_rx_glo = base + MT_WPDMA_GLO_CFG;
1011+ wed->wlan.wpdma_rx = base + MT_RXQ_WED_DATA_RING_BASE;
1012
1013 wed->wlan.tx_tbit[0] = MT_WED_TX_DONE_BAND0;
1014 wed->wlan.tx_tbit[1] = MT_WED_TX_DONE_BAND1;
1015 wed->wlan.txfree_tbit = MT_WED_TX_FREE_DONE;
1016+ wed->wlan.rx_tbit[0] = MT_WED_RX_DONE_BAND0;
1017+ wed->wlan.rx_tbit[1] = MT_WED_RX_DONE_BAND1;
1018+
1019 wed->wlan.nbuf = 7168;
1020 wed->wlan.token_start = MT7915_TOKEN_SIZE - wed->wlan.nbuf;
1021 wed->wlan.init_buf = mt7915_wed_init_buf;
developerf50c1802022-07-05 20:35:53 +08001022@@ -735,12 +752,15 @@ mt7915_pci_wed_init(struct mt7915_dev *dev, struct device *pdev, int *irq)
developer8cb3ac72022-07-04 10:55:14 +08001023 wed->wlan.offload_enable = mt7915_wed_offload_enable;
1024 wed->wlan.offload_disable = mt7915_wed_offload_disable;
1025
1026+ wed->wlan.rx_nbuf = 65536;
1027+ wed->wlan.rx_pkt_size = MTK_WED_RX_PKT_SIZE;
1028+ wed->wlan.init_rx_buf = mt7915_wed_init_rx_buf;
1029+ wed->wlan.release_rx_buf = mt7915_wed_release_rx_buf;
1030+
1031+ dev->mt76.rx_token_size = wed->wlan.rx_pkt + MT7915_RX_RING_SIZE * 2;
1032 if (mtk_wed_device_attach(wed) != 0)
1033 return 0;
1034
developerf50c1802022-07-05 20:35:53 +08001035- if (wed->ver == MTK_WED_V1)
1036- wed->wlan.wpdma_phys = base + MT_WFDMA_EXT_CSR_BASE;
1037-
1038 *irq = wed->irq;
1039 dev->mt76.dma_dev = wed->dev;
1040 mdev->token_size = wed->wlan.token_start;
developer8cb3ac72022-07-04 10:55:14 +08001041diff --git a/mt7915/mt7915.h b/mt7915/mt7915.h
developerd59e4772022-07-14 13:48:49 +08001042index 39127922..22399cc7 100644
developer8cb3ac72022-07-04 10:55:14 +08001043--- a/mt7915/mt7915.h
1044+++ b/mt7915/mt7915.h
developerd59e4772022-07-14 13:48:49 +08001045@@ -78,6 +78,7 @@
developer8cb3ac72022-07-04 10:55:14 +08001046 #define MT7915_MAX_STA_TWT_AGRT 8
1047 #define MT7915_MIN_TWT_DUR 64
1048 #define MT7915_MAX_QUEUE (__MT_RXQ_MAX + __MT_MCUQ_MAX + 2)
1049+#define MT7915_WED_RX_TOKEN_SIZE 12288
1050
1051 struct mt7915_vif;
1052 struct mt7915_sta;
developerd59e4772022-07-14 13:48:49 +08001053@@ -541,7 +542,9 @@ void mt7915_wfsys_reset(struct mt7915_dev *dev);
developer8cb3ac72022-07-04 10:55:14 +08001054 irqreturn_t mt7915_irq_handler(int irq, void *dev_instance);
1055 u64 __mt7915_get_tsf(struct ieee80211_hw *hw, struct mt7915_vif *mvif);
1056 u32 mt7915_wed_init_buf(void *ptr, dma_addr_t phys, int token_id);
1057-
1058+u32 mt7915_wed_init_rx_buf(struct mtk_wed_device *wed,
1059+ int pkt_num);
1060+void mt7915_wed_release_rx_buf(struct mtk_wed_device *wed);
1061 int mt7915_register_device(struct mt7915_dev *dev);
1062 void mt7915_unregister_device(struct mt7915_dev *dev);
1063 int mt7915_eeprom_init(struct mt7915_dev *dev);
developerd59e4772022-07-14 13:48:49 +08001064@@ -693,7 +696,7 @@ int mt7915_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
developer8cb3ac72022-07-04 10:55:14 +08001065 struct mt76_tx_info *tx_info);
1066 void mt7915_tx_token_put(struct mt7915_dev *dev);
1067 void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1068- struct sk_buff *skb);
1069+ struct sk_buff *skb, u32 info);
1070 bool mt7915_rx_check(struct mt76_dev *mdev, void *data, int len);
1071 void mt7915_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps);
1072 void mt7915_stats_work(struct work_struct *work);
1073diff --git a/mt7915/regs.h b/mt7915/regs.h
developerd59e4772022-07-14 13:48:49 +08001074index ffda5f6b..08bf84ce 100644
developer8cb3ac72022-07-04 10:55:14 +08001075--- a/mt7915/regs.h
1076+++ b/mt7915/regs.h
1077@@ -33,6 +33,9 @@ enum reg_rev {
1078 FW_EXCEPTION_ADDR,
1079 SWDEF_BASE_ADDR,
1080 EXCEPTION_BASE_ADDR,
1081+ WED_TX_RING,
1082+ WED_RX_RING,
1083+ WED_RX_DATA_RING,
1084 __MT_REG_MAX,
1085 };
1086
1087@@ -570,9 +573,13 @@ enum offs_rev {
1088 #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2 BIT(21)
1089
1090 #define MT_WFDMA0_RST_DTX_PTR MT_WFDMA0(0x20c)
1091+#define MT_WFDMA0_EXT0_CFG MT_WFDMA0(0x2b0)
1092+#define MT_WFDMA0_EXT0_RXWB_KEEP BIT(10)
1093+
1094 #define MT_WFDMA0_PRI_DLY_INT_CFG0 MT_WFDMA0(0x2f0)
1095 #define MT_WFDMA0_PRI_DLY_INT_CFG1 MT_WFDMA0(0x2f4)
1096 #define MT_WFDMA0_PRI_DLY_INT_CFG2 MT_WFDMA0(0x2f8)
1097+#define MT_WPDMA_GLO_CFG MT_WFDMA0(0x208)
1098
1099 #define MT_WFDMA0_MCU_HOST_INT_ENA MT_WFDMA0(0x1f4)
1100 #define MT_WFDMA0_MT_WA_WDT_INT BIT(31)
1101@@ -670,12 +677,15 @@ enum offs_rev {
1102 #define MT_TXQ_EXT_CTRL(q) (MT_Q_BASE(__TXQ(q)) + 0x600 + \
1103 MT_TXQ_ID(q)* 0x4)
1104
1105-#define MT_TXQ_WED_RING_BASE (!is_mt7986(mdev)? 0xd7300 : 0x24420)
1106-#define MT_RXQ_WED_RING_BASE (!is_mt7986(mdev)? 0xd7410 : 0x24520)
1107+#define MT_TXQ_WED_RING_BASE __REG(WED_TX_RING)
1108+#define MT_RXQ_WED_RING_BASE __REG(WED_RX_RING)
1109+#define MT_RXQ_WED_DATA_RING_BASE __REG(WED_RX_DATA_RING)
1110
1111 #define MT_WED_TX_DONE_BAND0 (is_mt7915(mdev)? 4 : 30)
1112 #define MT_WED_TX_DONE_BAND1 (is_mt7915(mdev)? 5 : 31)
1113 #define MT_WED_TX_FREE_DONE (is_mt7915(mdev)? 1 : 2)
1114+#define MT_WED_RX_DONE_BAND0 (is_mt7915(mdev)? 16 : 22)
1115+#define MT_WED_RX_DONE_BAND1 (is_mt7915(mdev)? 17 : 23)
1116
1117 #define MT_INT_SOURCE_CSR __REG(INT_SOURCE_CSR)
1118 #define MT_INT_MASK_CSR __REG(INT_MASK_CSR)
1119diff --git a/mt7921/mac.c b/mt7921/mac.c
developerd59e4772022-07-14 13:48:49 +08001120index 4fcadf86..4897940b 100644
developer8cb3ac72022-07-04 10:55:14 +08001121--- a/mt7921/mac.c
1122+++ b/mt7921/mac.c
1123@@ -555,7 +555,7 @@ out:
1124 EXPORT_SYMBOL_GPL(mt7921_mac_add_txs);
1125
1126 void mt7921_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1127- struct sk_buff *skb)
1128+ struct sk_buff *skb, u32 info)
1129 {
1130 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
1131 __le32 *rxd = (__le32 *)skb->data;
1132diff --git a/mt7921/mt7921.h b/mt7921/mt7921.h
developerd59e4772022-07-14 13:48:49 +08001133index efeb82cb..4b2e974b 100644
developer8cb3ac72022-07-04 10:55:14 +08001134--- a/mt7921/mt7921.h
1135+++ b/mt7921/mt7921.h
1136@@ -388,7 +388,7 @@ int mt7921e_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
1137 void mt7921_tx_worker(struct mt76_worker *w);
1138 void mt7921_tx_token_put(struct mt7921_dev *dev);
1139 void mt7921_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1140- struct sk_buff *skb);
1141+ struct sk_buff *skb, u32 info);
1142 void mt7921_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps);
1143 void mt7921_stats_work(struct work_struct *work);
1144 void mt7921_set_stream_he_caps(struct mt7921_phy *phy);
1145@@ -424,7 +424,7 @@ int mt7921_mcu_parse_response(struct mt76_dev *mdev, int cmd,
1146
1147 bool mt7921e_rx_check(struct mt76_dev *mdev, void *data, int len);
1148 void mt7921e_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1149- struct sk_buff *skb);
1150+ struct sk_buff *skb, u32 info);
1151 int mt7921e_driver_own(struct mt7921_dev *dev);
1152 int mt7921e_mac_reset(struct mt7921_dev *dev);
1153 int mt7921e_mcu_init(struct mt7921_dev *dev);
1154diff --git a/mt7921/pci_mac.c b/mt7921/pci_mac.c
developerd59e4772022-07-14 13:48:49 +08001155index e1800674..ca982eb5 100644
developer8cb3ac72022-07-04 10:55:14 +08001156--- a/mt7921/pci_mac.c
1157+++ b/mt7921/pci_mac.c
1158@@ -182,7 +182,7 @@ bool mt7921e_rx_check(struct mt76_dev *mdev, void *data, int len)
1159 }
1160
1161 void mt7921e_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1162- struct sk_buff *skb)
1163+ struct sk_buff *skb, u32 info)
1164 {
1165 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
1166 __le32 *rxd = (__le32 *)skb->data;
1167@@ -196,7 +196,7 @@ void mt7921e_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1168 napi_consume_skb(skb, 1);
1169 break;
1170 default:
1171- mt7921_queue_rx_skb(mdev, q, skb);
1172+ mt7921_queue_rx_skb(mdev, q, skb, info);
1173 break;
1174 }
1175 }
1176diff --git a/tx.c b/tx.c
developerd59e4772022-07-14 13:48:49 +08001177index ae44afe0..bccd206e 100644
developer8cb3ac72022-07-04 10:55:14 +08001178--- a/tx.c
1179+++ b/tx.c
developerf50c1802022-07-05 20:35:53 +08001180@@ -767,3 +767,37 @@ mt76_token_release(struct mt76_dev *dev, int token, bool *wake)
developer8cb3ac72022-07-04 10:55:14 +08001181 return txwi;
1182 }
1183 EXPORT_SYMBOL_GPL(mt76_token_release);
1184+
1185+int mt76_rx_token_consume(struct mt76_dev *dev, void *ptr,
1186+ struct mt76_txwi_cache *r, dma_addr_t phys)
1187+{
1188+ int token;
1189+
1190+ spin_lock_bh(&dev->rx_token_lock);
1191+
1192+ token = idr_alloc(&dev->rx_token, r, 0, dev->rx_token_size, GFP_ATOMIC);
1193+
1194+ spin_unlock_bh(&dev->rx_token_lock);
1195+
1196+ r->buf = ptr;
1197+ r->dma_addr = phys;
1198+
1199+ return token;
1200+}
1201+EXPORT_SYMBOL_GPL(mt76_rx_token_consume);
1202+
1203+struct mt76_txwi_cache *
1204+mt76_rx_token_release(struct mt76_dev *dev, int token)
1205+{
1206+
1207+ struct mt76_txwi_cache *rxwi;
1208+
1209+ spin_lock_bh(&dev->rx_token_lock);
1210+
1211+ rxwi = idr_remove(&dev->rx_token, token);
1212+
1213+ spin_unlock_bh(&dev->rx_token_lock);
1214+
1215+ return rxwi;
1216+}
1217+EXPORT_SYMBOL_GPL(mt76_rx_token_release);
1218--
developerd59e4772022-07-14 13:48:49 +080012192.25.1
developer8cb3ac72022-07-04 10:55:14 +08001220