blob: 093c55417d793defc631f17771e4bef3ff672881 [file] [log] [blame]
developer356ecec2022-11-14 10:25:04 +08001From 30ccfabd2dccb876067ca6ca666a862a9c693bdc Mon Sep 17 00:00:00 2001
developer8cb3ac72022-07-04 10:55:14 +08002From: Sujuan Chen <sujuan.chen@mediatek.com>
developerf50c1802022-07-05 20:35:53 +08003Date: Tue, 5 Jul 2022 19:42:55 +0800
developer356ecec2022-11-14 10:25:04 +08004Subject: [PATCH 3003/3011] mt76 add wed rx support
developer8cb3ac72022-07-04 10:55:14 +08005
6Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
developer887da632022-10-28 09:35:38 +08007Signed-off-by: StanleyYP Wang <StanleyYP.Wang@mediatek.com>
developer8cb3ac72022-07-04 10:55:14 +08008---
developerbbca0f92022-07-26 17:26:12 +08009 dma.c | 250 ++++++++++++++++++++++++++++++++++++++--------
10 dma.h | 10 ++
11 mac80211.c | 8 +-
developere0cbe332022-09-10 17:36:02 +080012 mt76.h | 24 ++++-
developerbbca0f92022-07-26 17:26:12 +080013 mt7603/dma.c | 2 +-
14 mt7603/mt7603.h | 2 +-
15 mt7615/mac.c | 2 +-
16 mt7615/mt7615.h | 2 +-
17 mt76_connac_mcu.c | 9 ++
18 mt76x02.h | 2 +-
19 mt76x02_txrx.c | 2 +-
developerc226de82022-10-03 12:24:57 +080020 mt7915/dma.c | 17 +++-
developer20747c12022-09-16 14:09:40 +080021 mt7915/mac.c | 101 ++++++++++++++++++-
developere0cbe332022-09-10 17:36:02 +080022 mt7915/mcu.c | 3 +
developerc226de82022-10-03 12:24:57 +080023 mt7915/mmio.c | 30 ++++--
developere0cbe332022-09-10 17:36:02 +080024 mt7915/mt7915.h | 7 +-
developerc226de82022-10-03 12:24:57 +080025 mt7915/regs.h | 6 ++
developerbbca0f92022-07-26 17:26:12 +080026 mt7921/mac.c | 2 +-
developer20747c12022-09-16 14:09:40 +080027 mt7921/mt7921.h | 2 +-
developerbbca0f92022-07-26 17:26:12 +080028 tx.c | 34 +++++++
developerc226de82022-10-03 12:24:57 +080029 20 files changed, 448 insertions(+), 67 deletions(-)
developer8cb3ac72022-07-04 10:55:14 +080030
31diff --git a/dma.c b/dma.c
developer356ecec2022-11-14 10:25:04 +080032index 82b4da26..a8739eb4 100644
developer8cb3ac72022-07-04 10:55:14 +080033--- a/dma.c
34+++ b/dma.c
35@@ -98,6 +98,63 @@ mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t)
36 }
37 EXPORT_SYMBOL_GPL(mt76_put_txwi);
38
39+static struct mt76_txwi_cache *
40+mt76_alloc_rxwi(struct mt76_dev *dev)
41+{
42+ struct mt76_txwi_cache *r;
43+ int size;
44+
45+ size = L1_CACHE_ALIGN(sizeof(*r));
46+ r = kzalloc(size, GFP_ATOMIC);
47+ if (!r)
48+ return NULL;
49+
50+ r->buf = NULL;
51+
52+ return r;
53+}
54+
55+static struct mt76_txwi_cache *
56+__mt76_get_rxwi(struct mt76_dev *dev)
57+{
58+ struct mt76_txwi_cache *r = NULL;
59+
60+ spin_lock(&dev->wed_lock);
61+ if (!list_empty(&dev->rxwi_cache)) {
62+ r = list_first_entry(&dev->rxwi_cache, struct mt76_txwi_cache,
63+ list);
64+ if(r)
65+ list_del(&r->list);
66+ }
67+ spin_unlock(&dev->wed_lock);
68+
69+ return r;
70+}
71+
72+struct mt76_txwi_cache *
73+mt76_get_rxwi(struct mt76_dev *dev)
74+{
75+ struct mt76_txwi_cache *r = __mt76_get_rxwi(dev);
76+
77+ if (r)
78+ return r;
79+
80+ return mt76_alloc_rxwi(dev);
81+}
82+EXPORT_SYMBOL_GPL(mt76_get_rxwi);
83+
84+void
85+mt76_put_rxwi(struct mt76_dev *dev, struct mt76_txwi_cache *r)
86+{
87+ if (!r)
88+ return;
89+
90+ spin_lock(&dev->wed_lock);
91+ list_add(&r->list, &dev->rxwi_cache);
92+ spin_unlock(&dev->wed_lock);
93+}
94+EXPORT_SYMBOL_GPL(mt76_put_rxwi);
95+
96 static void
97 mt76_free_pending_txwi(struct mt76_dev *dev)
98 {
developera3f86ed2022-07-08 14:15:13 +080099@@ -112,6 +169,21 @@ mt76_free_pending_txwi(struct mt76_dev *dev)
100 local_bh_enable();
101 }
102
103+static void
104+mt76_free_pending_rxwi(struct mt76_dev *dev)
105+{
106+ struct mt76_txwi_cache *r;
107+
108+ local_bh_disable();
109+ while ((r = __mt76_get_rxwi(dev)) != NULL) {
110+ if (r->buf)
111+ skb_free_frag(r->buf);
112+
113+ kfree(r);
114+ }
115+ local_bh_enable();
116+}
117+
118 static void
119 mt76_dma_sync_idx(struct mt76_dev *dev, struct mt76_queue *q)
120 {
121@@ -141,12 +213,15 @@ mt76_dma_queue_reset(struct mt76_dev *dev, struct mt76_queue *q)
developer8cb3ac72022-07-04 10:55:14 +0800122 static int
123 mt76_dma_add_buf(struct mt76_dev *dev, struct mt76_queue *q,
124 struct mt76_queue_buf *buf, int nbufs, u32 info,
125- struct sk_buff *skb, void *txwi)
126+ struct sk_buff *skb, void *txwi, void *rxwi)
127 {
128+ struct mtk_wed_device *wed = &dev->mmio.wed;
129+
130 struct mt76_queue_entry *entry;
131 struct mt76_desc *desc;
132 u32 ctrl;
133 int i, idx = -1;
134+ int type;
135
136 if (txwi) {
137 q->entry[q->head].txwi = DMA_DUMMY_DATA;
developera3f86ed2022-07-08 14:15:13 +0800138@@ -162,28 +237,42 @@ mt76_dma_add_buf(struct mt76_dev *dev, struct mt76_queue *q,
developer8cb3ac72022-07-04 10:55:14 +0800139 desc = &q->desc[idx];
140 entry = &q->entry[idx];
141
142- if (buf[0].skip_unmap)
143- entry->skip_buf0 = true;
144- entry->skip_buf1 = i == nbufs - 1;
145-
146- entry->dma_addr[0] = buf[0].addr;
147- entry->dma_len[0] = buf[0].len;
148-
149- ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, buf[0].len);
150- if (i < nbufs - 1) {
151- entry->dma_addr[1] = buf[1].addr;
152- entry->dma_len[1] = buf[1].len;
153- buf1 = buf[1].addr;
154- ctrl |= FIELD_PREP(MT_DMA_CTL_SD_LEN1, buf[1].len);
155- if (buf[1].skip_unmap)
156- entry->skip_buf1 = true;
157+ type = FIELD_GET(MT_QFLAG_WED_TYPE, q->flags);
158+ if (mtk_wed_device_active(wed) && type == MT76_WED_Q_RX) {
159+ struct mt76_txwi_cache *r = rxwi;
160+ int rx_token;
161+
162+ if (!r)
163+ return -ENOMEM;
164+
165+ rx_token = mt76_rx_token_consume(dev, (void *)skb, r, buf[0].addr);
166+
167+ buf1 |= FIELD_PREP(MT_DMA_CTL_TOKEN, rx_token);
168+ ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, MTK_WED_RX_PKT_SIZE);
169+ ctrl |= MT_DMA_CTL_TO_HOST;
170+ } else {
171+ if (buf[0].skip_unmap)
172+ entry->skip_buf0 = true;
173+ entry->skip_buf1 = i == nbufs - 1;
174+
175+ entry->dma_addr[0] = buf[0].addr;
176+ entry->dma_len[0] = buf[0].len;
177+
178+ ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, buf[0].len);
179+ if (i < nbufs - 1) {
180+ entry->dma_addr[1] = buf[1].addr;
181+ entry->dma_len[1] = buf[1].len;
182+ buf1 = buf[1].addr;
183+ ctrl |= FIELD_PREP(MT_DMA_CTL_SD_LEN1, buf[1].len);
184+ if (buf[1].skip_unmap)
185+ entry->skip_buf1 = true;
186+ }
187+ if (i == nbufs - 1)
188+ ctrl |= MT_DMA_CTL_LAST_SEC0;
189+ else if (i == nbufs - 2)
190+ ctrl |= MT_DMA_CTL_LAST_SEC1;
191 }
192
193- if (i == nbufs - 1)
194- ctrl |= MT_DMA_CTL_LAST_SEC0;
195- else if (i == nbufs - 2)
196- ctrl |= MT_DMA_CTL_LAST_SEC1;
197-
198 WRITE_ONCE(desc->buf0, cpu_to_le32(buf0));
199 WRITE_ONCE(desc->buf1, cpu_to_le32(buf1));
200 WRITE_ONCE(desc->info, cpu_to_le32(info));
developerc32bdb22022-07-20 16:15:39 +0800201@@ -272,33 +361,65 @@ mt76_dma_tx_cleanup(struct mt76_dev *dev, struct mt76_queue *q, bool flush)
developer8cb3ac72022-07-04 10:55:14 +0800202
203 static void *
204 mt76_dma_get_buf(struct mt76_dev *dev, struct mt76_queue *q, int idx,
205- int *len, u32 *info, bool *more)
206+ int *len, u32 *info, bool *more, bool *drop)
207 {
208 struct mt76_queue_entry *e = &q->entry[idx];
209 struct mt76_desc *desc = &q->desc[idx];
210 dma_addr_t buf_addr;
developerc32bdb22022-07-20 16:15:39 +0800211- void *buf = e->buf;
212+ void *buf = e->buf, *copy = NULL;
developer8cb3ac72022-07-04 10:55:14 +0800213 int buf_len = SKB_WITH_OVERHEAD(q->buf_size);
214+ struct mtk_wed_device *wed = &dev->mmio.wed;
215+ int type;
216
217- buf_addr = e->dma_addr[0];
218 if (len) {
219 u32 ctl = le32_to_cpu(READ_ONCE(desc->ctrl));
220 *len = FIELD_GET(MT_DMA_CTL_SD_LEN0, ctl);
221 *more = !(ctl & MT_DMA_CTL_LAST_SEC0);
222 }
223
224- if (info)
225- *info = le32_to_cpu(desc->info);
226+ type = FIELD_GET(MT_QFLAG_WED_TYPE, q->flags);
227+ if (mtk_wed_device_active(wed) && type == MT76_WED_Q_RX) {
228+ u32 token;
229+ struct mt76_txwi_cache *r;
230+
231+ token = FIELD_GET(MT_DMA_CTL_TOKEN, desc->buf1);
232+
233+ r = mt76_rx_token_release(dev, token);
234+ if (!r)
235+ return NULL;
236+
237+ buf = page_frag_alloc(&q->rx_page, q->buf_size, GFP_ATOMIC);
238+ if (!buf)
239+ return NULL;
240+
developerc32bdb22022-07-20 16:15:39 +0800241+ copy = r->buf;
developer8cb3ac72022-07-04 10:55:14 +0800242+ buf_addr = r->dma_addr;
243+ buf_len = MTK_WED_RX_PKT_SIZE;
244+ r->dma_addr = 0;
developer8cb3ac72022-07-04 10:55:14 +0800245+
246+ mt76_put_rxwi(dev, r);
247+
248+ if (desc->ctrl & (MT_DMA_CTL_TO_HOST_A | MT_DMA_CTL_DROP))
249+ *drop = true;
250+ } else {
251+ buf_addr = e->dma_addr[0];
252+ e->buf = NULL;
253+ }
254
255 dma_unmap_single(dev->dma_dev, buf_addr, buf_len, DMA_FROM_DEVICE);
256- e->buf = NULL;
257+
developerc32bdb22022-07-20 16:15:39 +0800258+ if (copy)
259+ memcpy(buf, copy, MTK_WED_RX_PKT_SIZE);
260+
developer8cb3ac72022-07-04 10:55:14 +0800261+ if (info)
262+ *info = le32_to_cpu(desc->info);
263
264 return buf;
265 }
266
267 static void *
268 mt76_dma_dequeue(struct mt76_dev *dev, struct mt76_queue *q, bool flush,
269- int *len, u32 *info, bool *more)
270+ int *len, u32 *info, bool *more, bool *drop)
271 {
272 int idx = q->tail;
273
developerbbca0f92022-07-26 17:26:12 +0800274@@ -314,7 +435,7 @@ mt76_dma_dequeue(struct mt76_dev *dev, struct mt76_queue *q, bool flush,
developer8cb3ac72022-07-04 10:55:14 +0800275 q->tail = (q->tail + 1) % q->ndesc;
276 q->queued--;
277
278- return mt76_dma_get_buf(dev, q, idx, len, info, more);
279+ return mt76_dma_get_buf(dev, q, idx, len, info, more, drop);
280 }
281
282 static int
developerbbca0f92022-07-26 17:26:12 +0800283@@ -336,7 +457,7 @@ mt76_dma_tx_queue_skb_raw(struct mt76_dev *dev, struct mt76_queue *q,
developer8cb3ac72022-07-04 10:55:14 +0800284 buf.len = skb->len;
285
286 spin_lock_bh(&q->lock);
287- mt76_dma_add_buf(dev, q, &buf, 1, tx_info, skb, NULL);
288+ mt76_dma_add_buf(dev, q, &buf, 1, tx_info, skb, NULL, NULL);
289 mt76_dma_kick_queue(dev, q);
290 spin_unlock_bh(&q->lock);
291
developerbbca0f92022-07-26 17:26:12 +0800292@@ -413,7 +534,7 @@ mt76_dma_tx_queue_skb(struct mt76_dev *dev, struct mt76_queue *q,
developer8cb3ac72022-07-04 10:55:14 +0800293 goto unmap;
294
295 return mt76_dma_add_buf(dev, q, tx_info.buf, tx_info.nbuf,
296- tx_info.info, tx_info.skb, t);
297+ tx_info.info, tx_info.skb, t, NULL);
298
299 unmap:
300 for (n--; n > 0; n--)
developerbbca0f92022-07-26 17:26:12 +0800301@@ -448,6 +569,8 @@ mt76_dma_rx_fill(struct mt76_dev *dev, struct mt76_queue *q)
developer8cb3ac72022-07-04 10:55:14 +0800302 int frames = 0;
303 int len = SKB_WITH_OVERHEAD(q->buf_size);
304 int offset = q->buf_offset;
305+ struct mtk_wed_device *wed = &dev->mmio.wed;
developera3f86ed2022-07-08 14:15:13 +0800306+ struct page_frag_cache *rx_page;
developer8cb3ac72022-07-04 10:55:14 +0800307
308 if (!q->ndesc)
309 return 0;
developerbbca0f92022-07-26 17:26:12 +0800310@@ -456,10 +579,29 @@ mt76_dma_rx_fill(struct mt76_dev *dev, struct mt76_queue *q)
developer8cb3ac72022-07-04 10:55:14 +0800311
312 while (q->queued < q->ndesc - 1) {
313 struct mt76_queue_buf qbuf;
314+ int type = FIELD_GET(MT_QFLAG_WED_TYPE, q->flags);
315+ bool skip_alloc = false;
316+ struct mt76_txwi_cache *r = NULL;
317+
developera3f86ed2022-07-08 14:15:13 +0800318+ rx_page = &q->rx_page;
developer8cb3ac72022-07-04 10:55:14 +0800319+ if (mtk_wed_device_active(wed) && type == MT76_WED_Q_RX) {
developera3f86ed2022-07-08 14:15:13 +0800320+ rx_page = &wed->rx_page;
developer8cb3ac72022-07-04 10:55:14 +0800321+ r = mt76_get_rxwi(dev);
322+ if (!r)
323+ return -ENOMEM;
324+
325+ if (r->buf) {
326+ skip_alloc = true;
327+ len = MTK_WED_RX_PKT_SIZE;
328+ buf = r->buf;
329+ }
330+ }
331
332- buf = page_frag_alloc(&q->rx_page, q->buf_size, GFP_ATOMIC);
333- if (!buf)
334- break;
335+ if (!skip_alloc) {
developera3f86ed2022-07-08 14:15:13 +0800336+ buf = page_frag_alloc(rx_page, q->buf_size, GFP_ATOMIC);
developer8cb3ac72022-07-04 10:55:14 +0800337+ if (!buf)
338+ break;
339+ }
340
341 addr = dma_map_single(dev->dma_dev, buf, len, DMA_FROM_DEVICE);
342 if (unlikely(dma_mapping_error(dev->dma_dev, addr))) {
developerbbca0f92022-07-26 17:26:12 +0800343@@ -470,7 +612,7 @@ mt76_dma_rx_fill(struct mt76_dev *dev, struct mt76_queue *q)
developer8cb3ac72022-07-04 10:55:14 +0800344 qbuf.addr = addr + offset;
345 qbuf.len = len - offset;
346 qbuf.skip_unmap = false;
347- mt76_dma_add_buf(dev, q, &qbuf, 1, 0, buf, NULL);
348+ mt76_dma_add_buf(dev, q, &qbuf, 1, 0, buf, NULL, r);
349 frames++;
350 }
351
developerbbca0f92022-07-26 17:26:12 +0800352@@ -516,6 +658,11 @@ mt76_dma_wed_setup(struct mt76_dev *dev, struct mt76_queue *q)
developer8cb3ac72022-07-04 10:55:14 +0800353 if (!ret)
354 q->wed_regs = wed->txfree_ring.reg_base;
355 break;
356+ case MT76_WED_Q_RX:
357+ ret = mtk_wed_device_rx_ring_setup(wed, ring, q->regs);
358+ if (!ret)
359+ q->wed_regs = wed->rx_ring[ring].reg_base;
360+ break;
361 default:
362 ret = -EINVAL;
363 }
developerbbca0f92022-07-26 17:26:12 +0800364@@ -531,7 +678,8 @@ mt76_dma_alloc_queue(struct mt76_dev *dev, struct mt76_queue *q,
developer8cb3ac72022-07-04 10:55:14 +0800365 int idx, int n_desc, int bufsize,
366 u32 ring_base)
367 {
368- int ret, size;
369+ int ret, size, type;
370+ struct mtk_wed_device *wed = &dev->mmio.wed;
371
372 spin_lock_init(&q->lock);
373 spin_lock_init(&q->cleanup_lock);
developerbbca0f92022-07-26 17:26:12 +0800374@@ -541,6 +689,11 @@ mt76_dma_alloc_queue(struct mt76_dev *dev, struct mt76_queue *q,
developer8cb3ac72022-07-04 10:55:14 +0800375 q->buf_size = bufsize;
376 q->hw_idx = idx;
377
378+ type = FIELD_GET(MT_QFLAG_WED_TYPE, q->flags);
379+ if (mtk_wed_device_active(wed) && type == MT76_WED_Q_RX)
380+ q->buf_size = SKB_DATA_ALIGN(NET_SKB_PAD + MTK_WED_RX_PKT_SIZE) +
381+ SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
382+
383 size = q->ndesc * sizeof(struct mt76_desc);
384 q->desc = dmam_alloc_coherent(dev->dma_dev, size, &q->desc_dma, GFP_KERNEL);
385 if (!q->desc)
developerbbca0f92022-07-26 17:26:12 +0800386@@ -573,7 +726,7 @@ mt76_dma_rx_cleanup(struct mt76_dev *dev, struct mt76_queue *q)
developer8cb3ac72022-07-04 10:55:14 +0800387
388 spin_lock_bh(&q->lock);
389 do {
390- buf = mt76_dma_dequeue(dev, q, true, NULL, NULL, &more);
391+ buf = mt76_dma_dequeue(dev, q, true, NULL, NULL, &more, NULL);
392 if (!buf)
393 break;
394
developerbbca0f92022-07-26 17:26:12 +0800395@@ -614,7 +767,7 @@ mt76_dma_rx_reset(struct mt76_dev *dev, enum mt76_rxq_id qid)
developer8cb3ac72022-07-04 10:55:14 +0800396
397 static void
398 mt76_add_fragment(struct mt76_dev *dev, struct mt76_queue *q, void *data,
399- int len, bool more)
400+ int len, bool more, u32 info)
401 {
402 struct sk_buff *skb = q->rx_head;
403 struct skb_shared_info *shinfo = skb_shinfo(skb);
developerbbca0f92022-07-26 17:26:12 +0800404@@ -634,7 +787,7 @@ mt76_add_fragment(struct mt76_dev *dev, struct mt76_queue *q, void *data,
developer8cb3ac72022-07-04 10:55:14 +0800405
406 q->rx_head = NULL;
407 if (nr_frags < ARRAY_SIZE(shinfo->frags))
408- dev->drv->rx_skb(dev, q - dev->q_rx, skb);
409+ dev->drv->rx_skb(dev, q - dev->q_rx, skb, info);
410 else
411 dev_kfree_skb(skb);
412 }
developerbbca0f92022-07-26 17:26:12 +0800413@@ -655,6 +808,7 @@ mt76_dma_rx_process(struct mt76_dev *dev, struct mt76_queue *q, int budget)
developer8cb3ac72022-07-04 10:55:14 +0800414 }
415
416 while (done < budget) {
417+ bool drop = false;
418 u32 info;
419
420 if (check_ddone) {
developerbbca0f92022-07-26 17:26:12 +0800421@@ -665,10 +819,13 @@ mt76_dma_rx_process(struct mt76_dev *dev, struct mt76_queue *q, int budget)
developer8cb3ac72022-07-04 10:55:14 +0800422 break;
423 }
424
425- data = mt76_dma_dequeue(dev, q, false, &len, &info, &more);
426+ data = mt76_dma_dequeue(dev, q, false, &len, &info, &more, &drop);
427 if (!data)
428 break;
429
430+ if (drop)
431+ goto free_frag;
432+
433 if (q->rx_head)
434 data_len = q->buf_size;
435 else
developerbbca0f92022-07-26 17:26:12 +0800436@@ -681,7 +838,7 @@ mt76_dma_rx_process(struct mt76_dev *dev, struct mt76_queue *q, int budget)
developer8cb3ac72022-07-04 10:55:14 +0800437 }
438
439 if (q->rx_head) {
440- mt76_add_fragment(dev, q, data, len, more);
441+ mt76_add_fragment(dev, q, data, len, more, info);
442 continue;
443 }
444
developer81ca9d62022-10-14 11:23:22 +0800445@@ -705,7 +862,7 @@ mt76_dma_rx_process(struct mt76_dev *dev, struct mt76_queue *q, int budget)
developer8cb3ac72022-07-04 10:55:14 +0800446 continue;
447 }
448
449- dev->drv->rx_skb(dev, q - dev->q_rx, skb);
450+ dev->drv->rx_skb(dev, q - dev->q_rx, skb, info);
451 continue;
452
453 free_frag:
developer81ca9d62022-10-14 11:23:22 +0800454@@ -782,7 +939,7 @@ EXPORT_SYMBOL_GPL(mt76_dma_attach);
developera3f86ed2022-07-08 14:15:13 +0800455
456 void mt76_dma_cleanup(struct mt76_dev *dev)
457 {
458- int i;
developera3f86ed2022-07-08 14:15:13 +0800459+ int i, type;
developerd59e4772022-07-14 13:48:49 +0800460
developera3f86ed2022-07-08 14:15:13 +0800461 mt76_worker_disable(&dev->tx_worker);
462 netif_napi_del(&dev->tx_napi);
developer81ca9d62022-10-14 11:23:22 +0800463@@ -803,12 +960,17 @@ void mt76_dma_cleanup(struct mt76_dev *dev)
developera3f86ed2022-07-08 14:15:13 +0800464
465 mt76_for_each_q_rx(dev, i) {
466 netif_napi_del(&dev->napi[i]);
467- mt76_dma_rx_cleanup(dev, &dev->q_rx[i]);
468+ type = FIELD_GET(MT_QFLAG_WED_TYPE, dev->q_rx[i].flags);
469+ if (type != MT76_WED_Q_RX)
470+ mt76_dma_rx_cleanup(dev, &dev->q_rx[i]);
471 }
472
473 mt76_free_pending_txwi(dev);
474+ mt76_free_pending_rxwi(dev);
475
476 if (mtk_wed_device_active(&dev->mmio.wed))
477 mtk_wed_device_detach(&dev->mmio.wed);
478+
479+ mt76_free_pending_rxwi(dev);
480 }
481 EXPORT_SYMBOL_GPL(mt76_dma_cleanup);
developer8cb3ac72022-07-04 10:55:14 +0800482diff --git a/dma.h b/dma.h
developer356ecec2022-11-14 10:25:04 +0800483index fdf786f9..90370d12 100644
developer8cb3ac72022-07-04 10:55:14 +0800484--- a/dma.h
485+++ b/dma.h
486@@ -16,6 +16,16 @@
487 #define MT_DMA_CTL_LAST_SEC0 BIT(30)
488 #define MT_DMA_CTL_DMA_DONE BIT(31)
489
490+#define MT_DMA_CTL_TO_HOST BIT(8)
491+#define MT_DMA_CTL_TO_HOST_A BIT(12)
492+#define MT_DMA_CTL_DROP BIT(14)
493+
494+#define MT_DMA_CTL_TOKEN GENMASK(31, 16)
495+
496+#define MT_DMA_PPE_CPU_REASON GENMASK(15, 11)
497+#define MT_DMA_PPE_ENTRY GENMASK(30, 16)
498+#define MT_DMA_INFO_PPE_VLD BIT(31)
499+
500 #define MT_DMA_HDR_LEN 4
501 #define MT_RX_INFO_LEN 4
502 #define MT_FCE_INFO_LEN 4
503diff --git a/mac80211.c b/mac80211.c
developer356ecec2022-11-14 10:25:04 +0800504index c84c9ef0..32961b60 100644
developer8cb3ac72022-07-04 10:55:14 +0800505--- a/mac80211.c
506+++ b/mac80211.c
developerc226de82022-10-03 12:24:57 +0800507@@ -603,11 +603,14 @@ mt76_alloc_device(struct device *pdev, unsigned int size,
developer8cb3ac72022-07-04 10:55:14 +0800508 BIT(NL80211_IFTYPE_ADHOC);
509
510 spin_lock_init(&dev->token_lock);
511+ spin_lock_init(&dev->rx_token_lock);
512 idr_init(&dev->token);
513+ idr_init(&dev->rx_token);
514
515 INIT_LIST_HEAD(&dev->wcid_list);
516
517 INIT_LIST_HEAD(&dev->txwi_cache);
518+ INIT_LIST_HEAD(&dev->rxwi_cache);
519 dev->token_size = dev->drv->token_size;
520
521 for (i = 0; i < ARRAY_SIZE(dev->q_rx); i++)
developer356ecec2022-11-14 10:25:04 +0800522@@ -1304,7 +1307,10 @@ void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q,
developer8cb3ac72022-07-04 10:55:14 +0800523
524 while ((skb = __skb_dequeue(&dev->rx_skb[q])) != NULL) {
525 mt76_check_sta(dev, skb);
526- mt76_rx_aggr_reorder(skb, &frames);
527+ if (mtk_wed_device_active(&dev->mmio.wed))
528+ __skb_queue_tail(&frames, skb);
529+ else
530+ mt76_rx_aggr_reorder(skb, &frames);
531 }
532
533 mt76_rx_complete(dev, &frames, napi);
534diff --git a/mt76.h b/mt76.h
developer356ecec2022-11-14 10:25:04 +0800535index b86c8355..627bcbf9 100644
developer8cb3ac72022-07-04 10:55:14 +0800536--- a/mt76.h
537+++ b/mt76.h
538@@ -20,6 +20,8 @@
539
540 #define MT_MCU_RING_SIZE 32
541 #define MT_RX_BUF_SIZE 2048
542+#define MTK_WED_RX_PKT_SIZE 1700
543+
544 #define MT_SKB_HEAD_LEN 256
545
546 #define MT_MAX_NON_AQL_PKT 16
547@@ -35,6 +37,7 @@
548 FIELD_PREP(MT_QFLAG_WED_TYPE, _type) | \
549 FIELD_PREP(MT_QFLAG_WED_RING, _n))
550 #define MT_WED_Q_TX(_n) __MT_WED_Q(MT76_WED_Q_TX, _n)
551+#define MT_WED_Q_RX(_n) __MT_WED_Q(MT76_WED_Q_RX, _n)
552 #define MT_WED_Q_TXFREE __MT_WED_Q(MT76_WED_Q_TXFREE, 0)
553
554 struct mt76_dev;
555@@ -56,6 +59,7 @@ enum mt76_bus_type {
556 enum mt76_wed_type {
557 MT76_WED_Q_TX,
558 MT76_WED_Q_TXFREE,
559+ MT76_WED_Q_RX,
560 };
561
562 struct mt76_bus_ops {
developer20747c12022-09-16 14:09:40 +0800563@@ -339,7 +343,10 @@ struct mt76_txwi_cache {
developer8cb3ac72022-07-04 10:55:14 +0800564 struct list_head list;
565 dma_addr_t dma_addr;
566
567- struct sk_buff *skb;
568+ union {
569+ void *buf;
570+ struct sk_buff *skb;
571+ };
572 };
573
574 struct mt76_rx_tid {
developerc226de82022-10-03 12:24:57 +0800575@@ -439,7 +446,7 @@ struct mt76_driver_ops {
developer8cb3ac72022-07-04 10:55:14 +0800576 bool (*rx_check)(struct mt76_dev *dev, void *data, int len);
577
578 void (*rx_skb)(struct mt76_dev *dev, enum mt76_rxq_id q,
579- struct sk_buff *skb);
580+ struct sk_buff *skb, u32 info);
581
582 void (*rx_poll_complete)(struct mt76_dev *dev, enum mt76_rxq_id q);
583
developer356ecec2022-11-14 10:25:04 +0800584@@ -782,6 +789,7 @@ struct mt76_dev {
developer8cb3ac72022-07-04 10:55:14 +0800585 struct ieee80211_hw *hw;
586
587 spinlock_t lock;
588+ spinlock_t wed_lock;
589 spinlock_t cc_lock;
590
591 u32 cur_cc_bss_rx;
developer356ecec2022-11-14 10:25:04 +0800592@@ -807,6 +815,7 @@ struct mt76_dev {
developer8cb3ac72022-07-04 10:55:14 +0800593 struct sk_buff_head rx_skb[__MT_RXQ_MAX];
594
595 struct list_head txwi_cache;
596+ struct list_head rxwi_cache;
597 struct mt76_queue *q_mcu[__MT_MCUQ_MAX];
598 struct mt76_queue q_rx[__MT_RXQ_MAX];
599 const struct mt76_queue_ops *queue_ops;
developer356ecec2022-11-14 10:25:04 +0800600@@ -820,6 +829,9 @@ struct mt76_dev {
developer8cb3ac72022-07-04 10:55:14 +0800601 u16 wed_token_count;
602 u16 token_count;
603 u16 token_size;
604+ u16 rx_token_size;
605+ spinlock_t rx_token_lock;
606+ struct idr rx_token;
607
608 wait_queue_head_t tx_wait;
609 /* spinclock used to protect wcid pktid linked list */
developer356ecec2022-11-14 10:25:04 +0800610@@ -1361,6 +1373,8 @@ mt76_tx_status_get_hw(struct mt76_dev *dev, struct sk_buff *skb)
developer8cb3ac72022-07-04 10:55:14 +0800611 }
612
613 void mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t);
614+void mt76_put_rxwi(struct mt76_dev *dev, struct mt76_txwi_cache *t);
615+struct mt76_txwi_cache *mt76_get_rxwi(struct mt76_dev *dev);
616 void mt76_rx_complete(struct mt76_dev *dev, struct sk_buff_head *frames,
617 struct napi_struct *napi);
618 void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q,
developer356ecec2022-11-14 10:25:04 +0800619@@ -1505,6 +1519,12 @@ struct mt76_txwi_cache *
developer8cb3ac72022-07-04 10:55:14 +0800620 mt76_token_release(struct mt76_dev *dev, int token, bool *wake);
621 int mt76_token_consume(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi);
622 void __mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked);
623+int mt76_rx_token_consume(struct mt76_dev *dev, void *ptr,
624+ struct mt76_txwi_cache *r, dma_addr_t phys);
625+void skb_trace(const struct sk_buff *skb, bool full_pkt);
626+
627+struct mt76_txwi_cache *
628+mt76_rx_token_release(struct mt76_dev *dev, int token);
629
630 static inline void mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked)
631 {
632diff --git a/mt7603/dma.c b/mt7603/dma.c
developer356ecec2022-11-14 10:25:04 +0800633index 590cff9d..2ff71c53 100644
developer8cb3ac72022-07-04 10:55:14 +0800634--- a/mt7603/dma.c
635+++ b/mt7603/dma.c
636@@ -69,7 +69,7 @@ free:
637 }
638
639 void mt7603_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
640- struct sk_buff *skb)
641+ struct sk_buff *skb, u32 info)
642 {
643 struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76);
644 __le32 *rxd = (__le32 *)skb->data;
645diff --git a/mt7603/mt7603.h b/mt7603/mt7603.h
developer356ecec2022-11-14 10:25:04 +0800646index 0fd46d90..f2ce22ae 100644
developer8cb3ac72022-07-04 10:55:14 +0800647--- a/mt7603/mt7603.h
648+++ b/mt7603/mt7603.h
649@@ -244,7 +244,7 @@ int mt7603_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
650 void mt7603_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue_entry *e);
651
652 void mt7603_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
653- struct sk_buff *skb);
654+ struct sk_buff *skb, u32 info);
655 void mt7603_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q);
656 void mt7603_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps);
657 int mt7603_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif,
658diff --git a/mt7615/mac.c b/mt7615/mac.c
developer356ecec2022-11-14 10:25:04 +0800659index 305bf182..4aed123b 100644
developer8cb3ac72022-07-04 10:55:14 +0800660--- a/mt7615/mac.c
661+++ b/mt7615/mac.c
developer356ecec2022-11-14 10:25:04 +0800662@@ -1666,7 +1666,7 @@ bool mt7615_rx_check(struct mt76_dev *mdev, void *data, int len)
developer8cb3ac72022-07-04 10:55:14 +0800663 EXPORT_SYMBOL_GPL(mt7615_rx_check);
664
665 void mt7615_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
666- struct sk_buff *skb)
667+ struct sk_buff *skb, u32 info)
668 {
669 struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
670 __le32 *rxd = (__le32 *)skb->data;
671diff --git a/mt7615/mt7615.h b/mt7615/mt7615.h
developer356ecec2022-11-14 10:25:04 +0800672index 1080d202..91b30373 100644
developer8cb3ac72022-07-04 10:55:14 +0800673--- a/mt7615/mt7615.h
674+++ b/mt7615/mt7615.h
developer356ecec2022-11-14 10:25:04 +0800675@@ -514,7 +514,7 @@ void mt7615_tx_worker(struct mt76_worker *w);
developer8cb3ac72022-07-04 10:55:14 +0800676 void mt7615_tx_token_put(struct mt7615_dev *dev);
677 bool mt7615_rx_check(struct mt76_dev *mdev, void *data, int len);
678 void mt7615_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
679- struct sk_buff *skb);
680+ struct sk_buff *skb, u32 info);
681 void mt7615_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps);
682 int mt7615_mac_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif,
683 struct ieee80211_sta *sta);
684diff --git a/mt76_connac_mcu.c b/mt76_connac_mcu.c
developer356ecec2022-11-14 10:25:04 +0800685index afdd42ff..1b01ef26 100644
developer8cb3ac72022-07-04 10:55:14 +0800686--- a/mt76_connac_mcu.c
687+++ b/mt76_connac_mcu.c
developer20747c12022-09-16 14:09:40 +0800688@@ -1192,6 +1192,7 @@ int mt76_connac_mcu_sta_ba(struct mt76_dev *dev, struct mt76_vif *mvif,
developer8cb3ac72022-07-04 10:55:14 +0800689 int cmd, bool enable, bool tx)
690 {
691 struct mt76_wcid *wcid = (struct mt76_wcid *)params->sta->drv_priv;
692+ struct mtk_wed_device *wed = &dev->mmio.wed;
693 struct wtbl_req_hdr *wtbl_hdr;
694 struct tlv *sta_wtbl;
695 struct sk_buff *skb;
developer20747c12022-09-16 14:09:40 +0800696@@ -1212,6 +1213,8 @@ int mt76_connac_mcu_sta_ba(struct mt76_dev *dev, struct mt76_vif *mvif,
developer8cb3ac72022-07-04 10:55:14 +0800697 mt76_connac_mcu_wtbl_ba_tlv(dev, skb, params, enable, tx, sta_wtbl,
698 wtbl_hdr);
699
developerf50c1802022-07-05 20:35:53 +0800700+ if (mtk_wed_device_active(wed) && wed->ver > MTK_WED_V1)
developer6adfa0e2022-07-06 16:25:53 +0800701+ mtk_wed_device_update_msg(wed, WED_WO_STA_REC, skb->data, skb->len);
developer8cb3ac72022-07-04 10:55:14 +0800702 ret = mt76_mcu_skb_send_msg(dev, skb, cmd, true);
703 if (ret)
704 return ret;
developer20747c12022-09-16 14:09:40 +0800705@@ -1222,6 +1225,8 @@ int mt76_connac_mcu_sta_ba(struct mt76_dev *dev, struct mt76_vif *mvif,
developer8cb3ac72022-07-04 10:55:14 +0800706
707 mt76_connac_mcu_sta_ba_tlv(skb, params, enable, tx);
708
developerf50c1802022-07-05 20:35:53 +0800709+ if (mtk_wed_device_active(wed) && wed->ver > MTK_WED_V1)
710+ mtk_wed_device_update_msg(wed, WED_WO_STA_REC, skb->data, skb->len);
developer8cb3ac72022-07-04 10:55:14 +0800711 return mt76_mcu_skb_send_msg(dev, skb, cmd, true);
712 }
713 EXPORT_SYMBOL_GPL(mt76_connac_mcu_sta_ba);
developer356ecec2022-11-14 10:25:04 +0800714@@ -2651,6 +2656,7 @@ int mt76_connac_mcu_add_key(struct mt76_dev *dev, struct ieee80211_vif *vif,
developer8cb3ac72022-07-04 10:55:14 +0800715 struct mt76_wcid *wcid, enum set_key_cmd cmd)
716 {
717 struct mt76_vif *mvif = (struct mt76_vif *)vif->drv_priv;
718+ struct mtk_wed_device *wed = &dev->mmio.wed;
719 struct sk_buff *skb;
720 int ret;
721
developer356ecec2022-11-14 10:25:04 +0800722@@ -2662,6 +2668,9 @@ int mt76_connac_mcu_add_key(struct mt76_dev *dev, struct ieee80211_vif *vif,
developer8cb3ac72022-07-04 10:55:14 +0800723 if (ret)
724 return ret;
725
developerf50c1802022-07-05 20:35:53 +0800726+ if (mtk_wed_device_active(wed) && wed->ver > MTK_WED_V1)
developer8cb3ac72022-07-04 10:55:14 +0800727+ mtk_wed_device_update_msg(wed, WED_WO_STA_REC, skb->data, skb->len);
728+
729 return mt76_mcu_skb_send_msg(dev, skb, mcu_cmd, true);
730 }
731 EXPORT_SYMBOL_GPL(mt76_connac_mcu_add_key);
732diff --git a/mt76x02.h b/mt76x02.h
developer356ecec2022-11-14 10:25:04 +0800733index 849c2644..49112ab6 100644
developer8cb3ac72022-07-04 10:55:14 +0800734--- a/mt76x02.h
735+++ b/mt76x02.h
developerc226de82022-10-03 12:24:57 +0800736@@ -187,7 +187,7 @@ int mt76x02_set_rts_threshold(struct ieee80211_hw *hw, u32 val);
developer8cb3ac72022-07-04 10:55:14 +0800737 void mt76x02_remove_hdr_pad(struct sk_buff *skb, int len);
738 bool mt76x02_tx_status_data(struct mt76_dev *mdev, u8 *update);
739 void mt76x02_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
740- struct sk_buff *skb);
741+ struct sk_buff *skb, u32 info);
742 void mt76x02_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q);
743 irqreturn_t mt76x02_irq_handler(int irq, void *dev_instance);
744 void mt76x02_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control,
745diff --git a/mt76x02_txrx.c b/mt76x02_txrx.c
developer356ecec2022-11-14 10:25:04 +0800746index 3a313075..5d6c8f71 100644
developer8cb3ac72022-07-04 10:55:14 +0800747--- a/mt76x02_txrx.c
748+++ b/mt76x02_txrx.c
749@@ -33,7 +33,7 @@ void mt76x02_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control,
750 EXPORT_SYMBOL_GPL(mt76x02_tx);
751
752 void mt76x02_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
753- struct sk_buff *skb)
754+ struct sk_buff *skb, u32 info)
755 {
756 struct mt76x02_dev *dev = container_of(mdev, struct mt76x02_dev, mt76);
757 void *rxwi = skb->data;
758diff --git a/mt7915/dma.c b/mt7915/dma.c
developer356ecec2022-11-14 10:25:04 +0800759index 9a57ad8f..6f6550f5 100644
developer8cb3ac72022-07-04 10:55:14 +0800760--- a/mt7915/dma.c
761+++ b/mt7915/dma.c
developer356ecec2022-11-14 10:25:04 +0800762@@ -365,7 +365,8 @@ static int mt7915_dma_enable(struct mt7915_dev *dev)
developer8d18bff2022-09-26 17:39:49 +0800763 wed_irq_mask |= MT_INT_TX_DONE_BAND0 | MT_INT_TX_DONE_BAND1;
764 if (!is_mt7986(&dev->mt76))
765 mt76_wr(dev, MT_INT_WED_MASK_CSR, wed_irq_mask);
766- mt76_wr(dev, MT_INT_MASK_CSR, wed_irq_mask);
767+ else
768+ mt76_wr(dev, MT_INT_MASK_CSR, wed_irq_mask);
769 mtk_wed_device_start(&dev->mt76.mmio.wed, wed_irq_mask);
770 }
developerc226de82022-10-03 12:24:57 +0800771
developer356ecec2022-11-14 10:25:04 +0800772@@ -377,6 +378,7 @@ static int mt7915_dma_enable(struct mt7915_dev *dev)
developerc1b2cd12022-07-28 18:35:24 +0800773 int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2)
774 {
775 struct mt76_dev *mdev = &dev->mt76;
776+ struct mtk_wed_device *wed = &mdev->mmio.wed;
777 u32 wa_rx_base, wa_rx_idx;
778 u32 hif1_ofs = 0;
779 int ret;
developer356ecec2022-11-14 10:25:04 +0800780@@ -401,6 +403,9 @@ int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2)
developerc226de82022-10-03 12:24:57 +0800781 FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_TX1, 19) |
782 FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_RX1,
783 wed_control_rx1));
784+ if(is_mt7915(mdev))
developerc1b2cd12022-07-28 18:35:24 +0800785+ mt76_rmw(dev, MT_WFDMA0_EXT0_CFG, MT_WFDMA0_EXT0_RXWB_KEEP,
developerc226de82022-10-03 12:24:57 +0800786+ MT_WFDMA0_EXT0_RXWB_KEEP);
787 }
788 } else {
789 mt76_clear(dev, MT_WFDMA_HOST_CONFIG, MT_WFDMA_HOST_CONFIG_WED);
developer356ecec2022-11-14 10:25:04 +0800790@@ -473,6 +478,11 @@ int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2)
developer8cb3ac72022-07-04 10:55:14 +0800791
792 /* rx data queue for band0 */
793 if (!dev->phy.band_idx) {
developerc1b2cd12022-07-28 18:35:24 +0800794+ if (mtk_wed_device_active(wed) && wed->ver > MTK_WED_V1) {
developer8cb3ac72022-07-04 10:55:14 +0800795+ dev->mt76.q_rx[MT_RXQ_MAIN].flags = MT_WED_Q_RX(MT7915_RXQ_BAND0);
developerc1b2cd12022-07-28 18:35:24 +0800796+ dev->mt76.rx_token_size += MT7915_RX_RING_SIZE;
797+ }
developer8cb3ac72022-07-04 10:55:14 +0800798+
799 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN],
800 MT_RXQ_ID(MT_RXQ_MAIN),
801 MT7915_RX_RING_SIZE,
developer356ecec2022-11-14 10:25:04 +0800802@@ -503,6 +513,11 @@ int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2)
developer1d9fede2022-08-29 15:24:07 +0800803 }
developer8cb3ac72022-07-04 10:55:14 +0800804
805 if (dev->dbdc_support || dev->phy.band_idx) {
developerc1b2cd12022-07-28 18:35:24 +0800806+ if (mtk_wed_device_active(wed) && wed->ver > MTK_WED_V1) {
developer1d9fede2022-08-29 15:24:07 +0800807+ dev->mt76.q_rx[MT_RXQ_BAND1].flags = MT_WED_Q_RX(MT7915_RXQ_BAND1);
developerc1b2cd12022-07-28 18:35:24 +0800808+ dev->mt76.rx_token_size += MT7915_RX_RING_SIZE;
809+ }
developer8cb3ac72022-07-04 10:55:14 +0800810+
developer1d9fede2022-08-29 15:24:07 +0800811 /* rx data queue for band1 */
812 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_BAND1],
813 MT_RXQ_ID(MT_RXQ_BAND1),
developer8cb3ac72022-07-04 10:55:14 +0800814diff --git a/mt7915/mac.c b/mt7915/mac.c
developer356ecec2022-11-14 10:25:04 +0800815index 20e5b705..eac49465 100644
developer8cb3ac72022-07-04 10:55:14 +0800816--- a/mt7915/mac.c
817+++ b/mt7915/mac.c
developer356ecec2022-11-14 10:25:04 +0800818@@ -247,7 +247,7 @@ void mt7915_mac_enable_rtscts(struct mt7915_dev *dev,
developer8cb3ac72022-07-04 10:55:14 +0800819 }
820
821 static int
822-mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
823+mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb, enum mt76_rxq_id q, u32 info)
824 {
825 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
826 struct mt76_phy *mphy = &dev->mt76.phy;
developer356ecec2022-11-14 10:25:04 +0800827@@ -526,6 +526,27 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
developer8cb3ac72022-07-04 10:55:14 +0800828 #endif
829 } else {
830 status->flag |= RX_FLAG_8023;
developera3f86ed2022-07-08 14:15:13 +0800831+ if (msta && msta->vif) {
developer8cb3ac72022-07-04 10:55:14 +0800832+ struct mtk_wed_device *wed;
833+ int type;
834+
835+ wed = &dev->mt76.mmio.wed;
836+ type = FIELD_GET(MT_QFLAG_WED_TYPE, dev->mt76.q_rx[q].flags);
837+ if ((mtk_wed_device_active(wed) && type == MT76_WED_Q_RX) &&
developera3f86ed2022-07-08 14:15:13 +0800838+ (info & MT_DMA_INFO_PPE_VLD)) {
developer8cb3ac72022-07-04 10:55:14 +0800839+ struct ieee80211_vif *vif;
840+ u32 hash, reason;
841+
842+ vif = container_of((void *)msta->vif, struct ieee80211_vif,
developera3f86ed2022-07-08 14:15:13 +0800843+ drv_priv);
developer8cb3ac72022-07-04 10:55:14 +0800844+
845+ skb->dev = ieee80211_vif_to_netdev(vif);
846+ reason = FIELD_GET(MT_DMA_PPE_CPU_REASON, info);
847+ hash = FIELD_GET(MT_DMA_PPE_ENTRY, info);
848+
849+ mtk_wed_device_ppe_check(wed, skb, reason, hash);
850+ }
851+ }
852 }
853
854 if (rxv && mode >= MT_PHY_TYPE_HE_SU && !(status->flag & RX_FLAG_8023))
developer356ecec2022-11-14 10:25:04 +0800855@@ -863,6 +884,80 @@ u32 mt7915_wed_init_buf(void *ptr, dma_addr_t phys, int token_id)
developer8cb3ac72022-07-04 10:55:14 +0800856 return MT_TXD_TXP_BUF_SIZE;
857 }
858
859+u32
860+mt7915_wed_init_rx_buf(struct mtk_wed_device *wed, int pkt_num)
861+{
862+ struct mtk_rxbm_desc *desc = wed->rx_buf_ring.desc;
863+ struct mt7915_dev *dev;
864+ dma_addr_t buf_phys;
865+ void *buf;
866+ int i, token, buf_size;
867+
868+ buf_size = SKB_DATA_ALIGN(NET_SKB_PAD + wed->wlan.rx_pkt_size) +
869+ SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
870+
871+ dev = container_of(wed, struct mt7915_dev, mt76.mmio.wed);
872+ for (i = 0; i < pkt_num; i++) {
873+ struct mt76_txwi_cache *r = mt76_get_rxwi(&dev->mt76);
874+
875+ buf = page_frag_alloc(&wed->rx_page, buf_size, GFP_ATOMIC);
876+ if (!buf)
877+ return -ENOMEM;
878+
879+ buf_phys = dma_map_single(dev->mt76.dma_dev, buf, wed->wlan.rx_pkt_size,
880+ DMA_TO_DEVICE);
881+
882+ if (unlikely(dma_mapping_error(dev->mt76.dev, buf_phys))) {
883+ skb_free_frag(buf);
884+ break;
885+ }
886+
887+ desc->buf0 = buf_phys;
888+
889+ token = mt76_rx_token_consume(&dev->mt76, buf, r, buf_phys);
890+
891+ desc->token |= FIELD_PREP(MT_DMA_CTL_TOKEN, token);
892+ desc++;
893+ }
894+
895+ return 0;
896+}
897+
898+void mt7915_wed_release_rx_buf(struct mtk_wed_device *wed)
899+{
900+ struct mt76_txwi_cache *rxwi;
901+ struct mt7915_dev *dev;
developera3f86ed2022-07-08 14:15:13 +0800902+ struct page *page;
developer8cb3ac72022-07-04 10:55:14 +0800903+ int token;
904+
905+ dev = container_of(wed, struct mt7915_dev, mt76.mmio.wed);
906+
907+ for(token = 0; token < dev->mt76.rx_token_size; token++) {
908+ rxwi = mt76_rx_token_release(&dev->mt76, token);
909+ if(!rxwi)
910+ continue;
911+
developera3f86ed2022-07-08 14:15:13 +0800912+ if(!rxwi->buf)
913+ continue;
914+
developer8cb3ac72022-07-04 10:55:14 +0800915+ dma_unmap_single(dev->mt76.dma_dev, rxwi->dma_addr,
916+ wed->wlan.rx_pkt_size, DMA_FROM_DEVICE);
917+ skb_free_frag(rxwi->buf);
918+ rxwi->buf = NULL;
919+
920+ mt76_put_rxwi(&dev->mt76, rxwi);
921+ }
developera3f86ed2022-07-08 14:15:13 +0800922+
923+ if (wed->rx_page.va)
924+ return;
925+
926+ page = virt_to_page(wed->rx_page.va);
927+ __page_frag_cache_drain(page, wed->rx_page.pagecnt_bias);
928+ memset(&wed->rx_page, 0, sizeof(wed->rx_page));
929+
developer8cb3ac72022-07-04 10:55:14 +0800930+ return;
931+}
932+
933 static void
934 mt7915_tx_check_aggr(struct ieee80211_sta *sta, __le32 *txwi)
935 {
developer356ecec2022-11-14 10:25:04 +0800936@@ -1147,7 +1242,7 @@ bool mt7915_rx_check(struct mt76_dev *mdev, void *data, int len)
developer8cb3ac72022-07-04 10:55:14 +0800937 }
938
939 void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
940- struct sk_buff *skb)
941+ struct sk_buff *skb, u32 info)
942 {
943 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
944 __le32 *rxd = (__le32 *)skb->data;
developer356ecec2022-11-14 10:25:04 +0800945@@ -1181,7 +1276,7 @@ void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
developer8cb3ac72022-07-04 10:55:14 +0800946 dev_kfree_skb(skb);
947 break;
948 case PKT_TYPE_NORMAL:
949- if (!mt7915_mac_fill_rx(dev, skb)) {
950+ if (!mt7915_mac_fill_rx(dev, skb, q, info)) {
951 mt76_rx(&dev->mt76, q, skb);
952 return;
953 }
954diff --git a/mt7915/mcu.c b/mt7915/mcu.c
developer356ecec2022-11-14 10:25:04 +0800955index eb9343ca..c11e575a 100644
developer8cb3ac72022-07-04 10:55:14 +0800956--- a/mt7915/mcu.c
957+++ b/mt7915/mcu.c
developer356ecec2022-11-14 10:25:04 +0800958@@ -1653,6 +1653,7 @@ int mt7915_mcu_add_sta(struct mt7915_dev *dev, struct ieee80211_vif *vif,
developer8cb3ac72022-07-04 10:55:14 +0800959 struct ieee80211_sta *sta, bool enable)
960 {
961 struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv;
962+ struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
963 struct mt7915_sta *msta;
964 struct sk_buff *skb;
965 int ret;
developer356ecec2022-11-14 10:25:04 +0800966@@ -1705,6 +1706,8 @@ int mt7915_mcu_add_sta(struct mt7915_dev *dev, struct ieee80211_vif *vif,
developer8cb3ac72022-07-04 10:55:14 +0800967 return ret;
968 }
969 out:
developerf50c1802022-07-05 20:35:53 +0800970+ if (mtk_wed_device_active(wed) && wed->ver > MTK_WED_V1)
971+ mtk_wed_device_update_msg(wed, WED_WO_STA_REC, skb->data, skb->len);
developer8cb3ac72022-07-04 10:55:14 +0800972 return mt76_mcu_skb_send_msg(&dev->mt76, skb,
973 MCU_EXT_CMD(STA_REC_UPDATE), true);
974 }
975diff --git a/mt7915/mmio.c b/mt7915/mmio.c
developer356ecec2022-11-14 10:25:04 +0800976index e45cd2d5..1e22ec98 100644
developer8cb3ac72022-07-04 10:55:14 +0800977--- a/mt7915/mmio.c
978+++ b/mt7915/mmio.c
developer356ecec2022-11-14 10:25:04 +0800979@@ -44,6 +44,7 @@ static const u32 mt7915_reg[] = {
developer8cb3ac72022-07-04 10:55:14 +0800980 [SWDEF_BASE_ADDR] = 0x41f200,
developerc226de82022-10-03 12:24:57 +0800981 [TXQ_WED_RING_BASE] = 0xd7300,
982 [RXQ_WED_RING_BASE] = 0xd7410,
developer8cb3ac72022-07-04 10:55:14 +0800983+ [WED_RX_DATA_RING] = 0xd4500,
984 };
985
developer356ecec2022-11-14 10:25:04 +0800986 static const u32 mt7916_reg[] = {
987@@ -77,6 +78,7 @@ static const u32 mt7916_reg[] = {
developer8cb3ac72022-07-04 10:55:14 +0800988 [SWDEF_BASE_ADDR] = 0x411400,
developerc226de82022-10-03 12:24:57 +0800989 [TXQ_WED_RING_BASE] = 0xd7300,
990 [RXQ_WED_RING_BASE] = 0xd7410,
developer8cb3ac72022-07-04 10:55:14 +0800991+ [WED_RX_DATA_RING] = 0xd4540,
992 };
993
developer356ecec2022-11-14 10:25:04 +0800994 static const u32 mt7986_reg[] = {
995@@ -110,6 +112,7 @@ static const u32 mt7986_reg[] = {
developer8cb3ac72022-07-04 10:55:14 +0800996 [SWDEF_BASE_ADDR] = 0x411400,
developerc226de82022-10-03 12:24:57 +0800997 [TXQ_WED_RING_BASE] = 0x24420,
998 [RXQ_WED_RING_BASE] = 0x24520,
developer8cb3ac72022-07-04 10:55:14 +0800999+ [WED_RX_DATA_RING] = 0x24540,
1000 };
1001
developer356ecec2022-11-14 10:25:04 +08001002 static const u32 mt7915_offs[] = {
1003@@ -605,7 +608,7 @@ int mt7915_mmio_wed_init(struct mt7915_dev *dev, void *pdev_ptr,
developerc226de82022-10-03 12:24:57 +08001004 struct pci_dev *pci_dev = pdev_ptr;
1005
1006 wed->wlan.pci_dev = pci_dev;
1007- wed->wlan.bus_type = MTK_WED_BUS_PCIE;
1008+ wed->wlan.bus_type = MTK_BUS_TYPE_PCIE;
1009 wed->wlan.base = (void __iomem *)ioremap(
1010 pci_resource_start(pci_dev, 0),
1011 pci_resource_len(pci_dev, 0));
developer356ecec2022-11-14 10:25:04 +08001012@@ -619,6 +622,10 @@ int mt7915_mmio_wed_init(struct mt7915_dev *dev, void *pdev_ptr,
developerc226de82022-10-03 12:24:57 +08001013 MT_TXQ_WED_RING_BASE;
1014 wed->wlan.wpdma_txfree = pci_resource_start(pci_dev, 0) +
1015 MT_RXQ_WED_RING_BASE;
1016+ wed->wlan.wpdma_rx_glo = pci_resource_start(pci_dev, 0) +
1017+ MT_WPDMA_GLO_CFG;
1018+ wed->wlan.wpdma_rx = pci_resource_start(pci_dev, 0) +
1019+ MT_RXQ_WED_DATA_RING_BASE;
1020 wed->wlan.phy_base = pci_resource_start(pci_dev, 0);
developerf50c1802022-07-05 20:35:53 +08001021 } else {
developerc226de82022-10-03 12:24:57 +08001022 struct platform_device *plat_dev = pdev_ptr;
developer356ecec2022-11-14 10:25:04 +08001023@@ -628,27 +635,38 @@ int mt7915_mmio_wed_init(struct mt7915_dev *dev, void *pdev_ptr,
developerc226de82022-10-03 12:24:57 +08001024 if (!res)
1025 return -ENOMEM;
1026
1027- wed->wlan.platform_dev = plat_dev;
1028- wed->wlan.bus_type = MTK_WED_BUS_AXI;
1029+ //wed->wlan.platform_dev = plat_dev;
1030+ wed->wlan.bus_type = MTK_BUS_TYPE_AXI;
1031 wed->wlan.base = (void __iomem *)ioremap(res->start,
1032 resource_size(res));
1033 wed->wlan.wpdma_int = res->start + MT_INT_SOURCE_CSR;
1034 wed->wlan.wpdma_mask = res->start + MT_INT_MASK_CSR;
1035 wed->wlan.wpdma_tx = res->start + MT_TXQ_WED_RING_BASE;
1036 wed->wlan.wpdma_txfree = res->start + MT_RXQ_WED_RING_BASE;
1037+ wed->wlan.wpdma_rx_glo = res->start + MT_WPDMA_GLO_CFG;
1038+ wed->wlan.wpdma_rx = res->start + MT_RXQ_WED_DATA_RING_BASE;
1039 wed->wlan.phy_base = res->start;
developer8cb3ac72022-07-04 10:55:14 +08001040 }
developerc226de82022-10-03 12:24:57 +08001041- wed->wlan.nbuf = 4096;
developer8cb3ac72022-07-04 10:55:14 +08001042+ wed->wlan.rx_pkt = MT7915_WED_RX_TOKEN_SIZE;
developerc226de82022-10-03 12:24:57 +08001043+ wed->wlan.nbuf = 7168;
1044 wed->wlan.tx_tbit[0] = is_mt7915(&dev->mt76) ? 4 : 30;
1045 wed->wlan.tx_tbit[1] = is_mt7915(&dev->mt76) ? 5 : 31;
1046- wed->wlan.txfree_tbit = is_mt7915(&dev->mt76) ? 1 : 2;
1047+ wed->wlan.txfree_tbit = (is_mt7986(&dev->mt76) ? 2 : 1);
1048+ wed->wlan.rx_tbit[0] = (is_mt7915(&dev->mt76) ? 16 : (is_mt7986(&dev->mt76) ? 22 : 18));
1049+ wed->wlan.rx_tbit[1] = (is_mt7915(&dev->mt76) ? 17 : (is_mt7986(&dev->mt76) ? 23 : 19));
developer8cb3ac72022-07-04 10:55:14 +08001050 wed->wlan.token_start = MT7915_TOKEN_SIZE - wed->wlan.nbuf;
1051 wed->wlan.init_buf = mt7915_wed_init_buf;
developerc226de82022-10-03 12:24:57 +08001052 wed->wlan.offload_enable = mt7915_mmio_wed_offload_enable;
1053 wed->wlan.offload_disable = mt7915_mmio_wed_offload_disable;
1054- if (!is_mt7915(mdev))
1055+ if (!is_mt7915(&dev->mt76))
developer203096a2022-09-13 21:07:19 +08001056 wed->wlan.wcid_512 = true;
developer8cb3ac72022-07-04 10:55:14 +08001057
1058+ wed->wlan.rx_nbuf = 65536;
1059+ wed->wlan.rx_pkt_size = MTK_WED_RX_PKT_SIZE;
1060+ wed->wlan.init_rx_buf = mt7915_wed_init_rx_buf;
1061+ wed->wlan.release_rx_buf = mt7915_wed_release_rx_buf;
1062+
developerc1b2cd12022-07-28 18:35:24 +08001063+ dev->mt76.rx_token_size = wed->wlan.rx_pkt;
developerc226de82022-10-03 12:24:57 +08001064 if (mtk_wed_device_attach(wed))
developer8cb3ac72022-07-04 10:55:14 +08001065 return 0;
1066
1067diff --git a/mt7915/mt7915.h b/mt7915/mt7915.h
developer356ecec2022-11-14 10:25:04 +08001068index ba12a2d2..acc345a2 100644
developer8cb3ac72022-07-04 10:55:14 +08001069--- a/mt7915/mt7915.h
1070+++ b/mt7915/mt7915.h
developere0cbe332022-09-10 17:36:02 +08001071@@ -81,6 +81,7 @@
developer8cb3ac72022-07-04 10:55:14 +08001072 #define MT7915_MAX_STA_TWT_AGRT 8
1073 #define MT7915_MIN_TWT_DUR 64
developer1d9fede2022-08-29 15:24:07 +08001074 #define MT7915_MAX_QUEUE (MT_RXQ_BAND2 + __MT_MCUQ_MAX + 2)
developer8cb3ac72022-07-04 10:55:14 +08001075+#define MT7915_WED_RX_TOKEN_SIZE 12288
1076
1077 struct mt7915_vif;
1078 struct mt7915_sta;
developer356ecec2022-11-14 10:25:04 +08001079@@ -559,7 +560,9 @@ void mt7915_wfsys_reset(struct mt7915_dev *dev);
developer8cb3ac72022-07-04 10:55:14 +08001080 irqreturn_t mt7915_irq_handler(int irq, void *dev_instance);
1081 u64 __mt7915_get_tsf(struct ieee80211_hw *hw, struct mt7915_vif *mvif);
1082 u32 mt7915_wed_init_buf(void *ptr, dma_addr_t phys, int token_id);
1083-
1084+u32 mt7915_wed_init_rx_buf(struct mtk_wed_device *wed,
1085+ int pkt_num);
1086+void mt7915_wed_release_rx_buf(struct mtk_wed_device *wed);
1087 int mt7915_register_device(struct mt7915_dev *dev);
1088 void mt7915_unregister_device(struct mt7915_dev *dev);
developer81ca9d62022-10-14 11:23:22 +08001089 void mt7915_eeprom_rebonding(struct mt7915_dev *dev);
developer356ecec2022-11-14 10:25:04 +08001090@@ -719,7 +722,7 @@ int mt7915_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
developer8cb3ac72022-07-04 10:55:14 +08001091 struct mt76_tx_info *tx_info);
1092 void mt7915_tx_token_put(struct mt7915_dev *dev);
1093 void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1094- struct sk_buff *skb);
1095+ struct sk_buff *skb, u32 info);
1096 bool mt7915_rx_check(struct mt76_dev *mdev, void *data, int len);
developere0cbe332022-09-10 17:36:02 +08001097 bool mt7915_wed_wds_check(struct mt76_dev *mdev, struct ieee80211_sta *sta);
developer8cb3ac72022-07-04 10:55:14 +08001098 void mt7915_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps);
developer8cb3ac72022-07-04 10:55:14 +08001099diff --git a/mt7915/regs.h b/mt7915/regs.h
developer356ecec2022-11-14 10:25:04 +08001100index 9b6266c1..faaac08c 100644
developer8cb3ac72022-07-04 10:55:14 +08001101--- a/mt7915/regs.h
1102+++ b/mt7915/regs.h
developer356ecec2022-11-14 10:25:04 +08001103@@ -43,6 +43,7 @@ enum reg_rev {
developer8cb3ac72022-07-04 10:55:14 +08001104 SWDEF_BASE_ADDR,
developerc226de82022-10-03 12:24:57 +08001105 TXQ_WED_RING_BASE,
1106 RXQ_WED_RING_BASE,
developer8cb3ac72022-07-04 10:55:14 +08001107+ WED_RX_DATA_RING,
1108 __MT_REG_MAX,
1109 };
developer356ecec2022-11-14 10:25:04 +08001110
1111@@ -603,9 +604,13 @@ enum offs_rev {
developer8cb3ac72022-07-04 10:55:14 +08001112 #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2 BIT(21)
1113
1114 #define MT_WFDMA0_RST_DTX_PTR MT_WFDMA0(0x20c)
1115+#define MT_WFDMA0_EXT0_CFG MT_WFDMA0(0x2b0)
1116+#define MT_WFDMA0_EXT0_RXWB_KEEP BIT(10)
1117+
1118 #define MT_WFDMA0_PRI_DLY_INT_CFG0 MT_WFDMA0(0x2f0)
1119 #define MT_WFDMA0_PRI_DLY_INT_CFG1 MT_WFDMA0(0x2f4)
1120 #define MT_WFDMA0_PRI_DLY_INT_CFG2 MT_WFDMA0(0x2f8)
1121+#define MT_WPDMA_GLO_CFG MT_WFDMA0(0x208)
1122
developer356ecec2022-11-14 10:25:04 +08001123 /* WFDMA1 */
1124 #define MT_WFDMA1_BASE 0xd5000
1125@@ -701,6 +706,7 @@ enum offs_rev {
developer8cb3ac72022-07-04 10:55:14 +08001126
developerc226de82022-10-03 12:24:57 +08001127 #define MT_TXQ_WED_RING_BASE __REG(TXQ_WED_RING_BASE)
1128 #define MT_RXQ_WED_RING_BASE __REG(RXQ_WED_RING_BASE)
developer8cb3ac72022-07-04 10:55:14 +08001129+#define MT_RXQ_WED_DATA_RING_BASE __REG(WED_RX_DATA_RING)
1130
developer8cb3ac72022-07-04 10:55:14 +08001131 #define MT_INT_SOURCE_CSR __REG(INT_SOURCE_CSR)
1132 #define MT_INT_MASK_CSR __REG(INT_MASK_CSR)
1133diff --git a/mt7921/mac.c b/mt7921/mac.c
developer356ecec2022-11-14 10:25:04 +08001134index 7b15193c..ea6dd953 100644
developer8cb3ac72022-07-04 10:55:14 +08001135--- a/mt7921/mac.c
1136+++ b/mt7921/mac.c
developer81ca9d62022-10-14 11:23:22 +08001137@@ -692,7 +692,7 @@ bool mt7921_rx_check(struct mt76_dev *mdev, void *data, int len)
developer20747c12022-09-16 14:09:40 +08001138 EXPORT_SYMBOL_GPL(mt7921_rx_check);
developer8cb3ac72022-07-04 10:55:14 +08001139
1140 void mt7921_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1141- struct sk_buff *skb)
1142+ struct sk_buff *skb, u32 info)
1143 {
1144 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
1145 __le32 *rxd = (__le32 *)skb->data;
1146diff --git a/mt7921/mt7921.h b/mt7921/mt7921.h
developer356ecec2022-11-14 10:25:04 +08001147index d9d78f6b..0c9924a5 100644
developer8cb3ac72022-07-04 10:55:14 +08001148--- a/mt7921/mt7921.h
1149+++ b/mt7921/mt7921.h
developer356ecec2022-11-14 10:25:04 +08001150@@ -422,7 +422,7 @@ void mt7921_tx_worker(struct mt76_worker *w);
developer8cb3ac72022-07-04 10:55:14 +08001151 void mt7921_tx_token_put(struct mt7921_dev *dev);
developer20747c12022-09-16 14:09:40 +08001152 bool mt7921_rx_check(struct mt76_dev *mdev, void *data, int len);
developer8cb3ac72022-07-04 10:55:14 +08001153 void mt7921_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1154- struct sk_buff *skb);
1155+ struct sk_buff *skb, u32 info);
1156 void mt7921_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps);
1157 void mt7921_stats_work(struct work_struct *work);
1158 void mt7921_set_stream_he_caps(struct mt7921_phy *phy);
developer8cb3ac72022-07-04 10:55:14 +08001159diff --git a/tx.c b/tx.c
developer356ecec2022-11-14 10:25:04 +08001160index 8b33186b..b812d067 100644
developer8cb3ac72022-07-04 10:55:14 +08001161--- a/tx.c
1162+++ b/tx.c
developer1d9fede2022-08-29 15:24:07 +08001163@@ -778,3 +778,37 @@ mt76_token_release(struct mt76_dev *dev, int token, bool *wake)
developer8cb3ac72022-07-04 10:55:14 +08001164 return txwi;
1165 }
1166 EXPORT_SYMBOL_GPL(mt76_token_release);
1167+
1168+int mt76_rx_token_consume(struct mt76_dev *dev, void *ptr,
1169+ struct mt76_txwi_cache *r, dma_addr_t phys)
1170+{
1171+ int token;
1172+
1173+ spin_lock_bh(&dev->rx_token_lock);
1174+
1175+ token = idr_alloc(&dev->rx_token, r, 0, dev->rx_token_size, GFP_ATOMIC);
1176+
1177+ spin_unlock_bh(&dev->rx_token_lock);
1178+
1179+ r->buf = ptr;
1180+ r->dma_addr = phys;
1181+
1182+ return token;
1183+}
1184+EXPORT_SYMBOL_GPL(mt76_rx_token_consume);
1185+
1186+struct mt76_txwi_cache *
1187+mt76_rx_token_release(struct mt76_dev *dev, int token)
1188+{
1189+
1190+ struct mt76_txwi_cache *rxwi;
1191+
1192+ spin_lock_bh(&dev->rx_token_lock);
1193+
1194+ rxwi = idr_remove(&dev->rx_token, token);
1195+
1196+ spin_unlock_bh(&dev->rx_token_lock);
1197+
1198+ return rxwi;
1199+}
1200+EXPORT_SYMBOL_GPL(mt76_rx_token_release);
1201--
developer887da632022-10-28 09:35:38 +080012022.18.0
developer8cb3ac72022-07-04 10:55:14 +08001203