[][[Merlin][AX3000][MT76][Performance] DBDC 5G HE160,peak throughput test , HWNAT CPU idle only 50.77%]
[Description]
Fix CPU idle only 50.77% issue when binding
DL: MT76 handle txfree notify interrupt
when all token are belongs to wed
UL: Merlin Rx data interrupt bit changes
to bit[19:18] from bit[23:22] when wed on
[Release-log]
N/A
[[Info to Customer]]
none
Change-Id: Icbfb4e0b6714e74ce2f7c501078bf37d164bda0e
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/6563470
Build: srv_hbgsm110
diff --git a/autobuild_mac80211_release/package/kernel/mt76/patches/3003-mt76-add-wed-rx-support.patch b/autobuild_mac80211_release/package/kernel/mt76/patches/3003-mt76-add-wed-rx-support.patch
index d07d072..4646c44 100644
--- a/autobuild_mac80211_release/package/kernel/mt76/patches/3003-mt76-add-wed-rx-support.patch
+++ b/autobuild_mac80211_release/package/kernel/mt76/patches/3003-mt76-add-wed-rx-support.patch
@@ -758,7 +758,17 @@
index ac30698f..197a0169 100644
--- a/mt7915/dma.c
+++ b/mt7915/dma.c
-@@ -349,6 +349,7 @@ static int mt7915_dma_enable(struct mt7915_dev *dev)
+@@ -337,7 +337,8 @@ static int mt7915_dma_enable(struct mt7915_dev *dev)
+ wed_irq_mask |= MT_INT_TX_DONE_BAND0 | MT_INT_TX_DONE_BAND1;
+ if (!is_mt7986(&dev->mt76))
+ mt76_wr(dev, MT_INT_WED_MASK_CSR, wed_irq_mask);
+- mt76_wr(dev, MT_INT_MASK_CSR, wed_irq_mask);
++ else
++ mt76_wr(dev, MT_INT_MASK_CSR, wed_irq_mask);
+ mtk_wed_device_start(&dev->mt76.mmio.wed, wed_irq_mask);
+ }
+
+@@ -349,6 +350,7 @@ static int mt7915_dma_enable(struct mt7915_dev *dev)
int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2)
{
struct mt76_dev *mdev = &dev->mt76;
@@ -1127,7 +1137,7 @@
#define MT_WFDMA0_MCU_HOST_INT_ENA MT_WFDMA0(0x1f4)
#define MT_WFDMA0_MT_WA_WDT_INT BIT(31)
-@@ -668,12 +675,15 @@ enum offs_rev {
+@@ -668,12 +675,18 @@ enum offs_rev {
#define MT_TXQ_EXT_CTRL(q) (MT_Q_BASE(__TXQ(q)) + 0x600 + \
MT_TXQ_ID(q)* 0x4)
@@ -1139,9 +1149,13 @@
#define MT_WED_TX_DONE_BAND0 (is_mt7915(mdev)? 4 : 30)
#define MT_WED_TX_DONE_BAND1 (is_mt7915(mdev)? 5 : 31)
- #define MT_WED_TX_FREE_DONE (is_mt7915(mdev)? 1 : 2)
-+#define MT_WED_RX_DONE_BAND0 (is_mt7915(mdev)? 16 : 22)
-+#define MT_WED_RX_DONE_BAND1 (is_mt7915(mdev)? 17 : 23)
+-#define MT_WED_TX_FREE_DONE (is_mt7915(mdev)? 1 : 2)
++#define MT_WED_TX_FREE_DONE (is_mt7986(mdev) ? 2 : 1)
++#define MT_WED_RX_DONE_BAND0 (is_mt7915(mdev) ? 16 : \
++ (is_mt7986(mdev) ? 22 : 18))
++#define MT_WED_RX_DONE_BAND1 (is_mt7915(mdev) ? 17 : \
++ (is_mt7986(mdev) ? 23 : 19))
++
#define MT_INT_SOURCE_CSR __REG(INT_SOURCE_CSR)
#define MT_INT_MASK_CSR __REG(INT_MASK_CSR)