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git01.mediatek.com / filogic / uboot / 4518ba0ebf4cd1b3021597cf59107b6a3834a578 / drivers / ddr / fsl / ctrl_regs.c
  1. d3e6816 Revert "drivers/ddr/fsl: Dual-license DDR driver" by Tom Rini · Wed Feb 14 21:34:05 2018 -0500
  2. 6d49eda drivers/ddr/fsl: Dual-license DDR driver by York Sun · Wed Feb 07 11:47:22 2018 -0800
  3. bc2f32a drivers/ddr/fsl: Add calculation of register control words by York Sun · Mon Jan 29 10:24:08 2018 -0800
  4. 6db4fdd drivers/ddr/fsl: Add 3DS RDIMM support by York Sun · Mon Jan 29 09:44:35 2018 -0800
  5. d9f7fa0 drivers/ddr/fsl: Fix DDR4 RDIMM support by York Sun · Mon Jan 29 09:44:33 2018 -0800
  6. 89e0a3a common: arm: freescale: layerscape: Move header files out of common.h by Simon Glass · Wed May 17 08:23:10 2017 -0600
  7. 243182c common: freescale: Move arch-specific declarations by Simon Glass · Wed May 17 08:23:06 2017 -0600
  8. fe84507 ddr: fsl: Merge macro CONFIG_NUM_DDR_CONTROLLERS and CONFIG_SYS_NUM_DDR_CTRLS by York Sun · Wed Dec 28 08:43:45 2016 -0800
  9. 15875a5 fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum by Shengzhou Liu · Mon Nov 21 11:36:48 2016 +0800
  10. 32be34d powerpc: MPC8555: Remove macro CONFIG_MPC8555 by York Sun · Wed Nov 16 11:23:23 2016 -0800
  11. bf820c0 powerpc: mpc8541: Remove macro CONFIG_MPC8541 by York Sun · Wed Nov 16 11:18:31 2016 -0800
  12. e3cef9f driver/ddr/fsl: Fix timing_cfg_2 by York Sun · Fri Jul 29 09:02:29 2016 -0700
  13. 8d56db9 Various, unrelated tree-wide typo fixes. by Robert P. J. Day · Fri Jul 15 13:44:45 2016 -0400
  14. 3abd16b drivers/ddr/fsl: Fix timing_cfg_2 register by York Sun · Wed May 18 21:11:19 2016 -0700
  15. 3b33dd2 drivers/ddr/fsl: Update clk_adjust of sdram_clk_cntl by Shengzhou Liu · Wed May 04 10:20:21 2016 +0800
  16. 5219944 driver/ddr/fsl: Add address parity support for DDR4 UDIMM/discrete by Shengzhou Liu · Thu Mar 10 17:36:56 2016 +0800
  17. 77594b3 driver/ddr/fsl: Update timing config for heavy load by York Sun · Wed Nov 04 10:03:21 2015 -0800
  18. d192126 driver/ddr/fsl: Update MR5 RTT park by York Sun · Wed Nov 04 10:03:19 2015 -0800
  19. d4d97ef driver/ddr/fsl: Update DDR4 MR6 for Vref range by York Sun · Wed Nov 04 10:03:18 2015 -0800
  20. 6dc192d drivers/ddr/fsl_ddr: Make SR_IE configurable by Joakim Tjernlund · Wed Oct 14 16:32:00 2015 +0200
  21. fc63b28 driver/ddr/fsl: Fix driver to support empty first slot by York Sun · Thu Mar 19 09:30:27 2015 -0700
  22. 55eb5fa drivers/ddr/fsl: Update DDR driver for DDR4 by York Sun · Thu Mar 19 09:30:26 2015 -0700
  23. 6aff153 MPC8541/MPC8555: Enable SS_EN in DDR_SDRAM_CLK_CNLT register by Curt Brune · Fri Feb 13 10:57:11 2015 -0800
  24. 5e52647 driver/ddr/fsl: Fix a typo in timing_cfg_8 calculation by York Sun · Tue Jan 06 13:18:52 2015 -0800
  25. 2c0b62d driver/ddr/fsl: Add support for multiple DDR clocks by York Sun · Tue Jan 06 13:18:50 2015 -0800
  26. 63f5771 driver/ddr/fsl: Adjust CAS to preamble override for emulator by York Sun · Tue Jan 06 13:18:45 2015 -0800
  27. 1b07ef1 driver/ddr/fsl: Fix MRC_CYC calculation for DDR3 by York Sun · Tue Dec 02 11:18:09 2014 -0800
  28. fbce88c driver/ddr/fsl: Adjust timing_cfg_0 to better support two DDR slots by York Sun · Fri Nov 07 12:14:36 2014 -0800
  29. db20464 linux/kernel.h: sync min, max, min3, max3 macros with Linux by Masahiro Yamada · Fri Nov 07 03:03:31 2014 +0900
  30. a8b3d52 driver/ddr/fsl: Fix DDR4 driver by York Sun · Thu Sep 11 13:32:06 2014 -0700
  31. c1bf24f driver/ddr/fsl: Fix tXP and tCKE by York Sun · Thu Aug 21 16:13:22 2014 -0700
  32. e0f6046 driver/ddr/fsl: Add support of overriding chip select write leveling by York Sun · Fri Sep 05 13:52:43 2014 +0800
  33. 5d6c626 driver/ddr/freescale: Add support of accumulate ECC by York Sun · Fri Sep 05 13:52:41 2014 +0800
  34. f0e4f6d driver/ddr: Fix DDR register timing_cfg_8 by York Sun · Thu Jun 26 11:14:44 2014 -0700
  35. 9982579 powerpc/mpc85xx: Add workaround for DDR erratum A004508 by York Sun · Fri May 23 13:15:00 2014 -0700
  36. edbeee1 drivers/ddr: Fix possible out of bounds error by York Sun · Tue Apr 01 14:20:49 2014 -0700
  37. 2896cb7 driver/ddr/fsl: Add DDR4 support to Freescale DDR driver by York Sun · Thu Mar 27 17:54:47 2014 -0700
  38. c459ae6 driver/ddr: Add 256 byte interleaving support by York Sun · Mon Feb 10 13:59:44 2014 -0800
  39. 29647ab driver/ddr: Change Freescale ARM DDR driver to support both big and little endian by York Sun · Mon Feb 10 13:59:42 2014 -0800
  40. 63c91cd powerpc/mpc8xxx: Extend DDR registers' fields by York Sun · Mon Jun 03 12:39:06 2013 -0700
  41. a21803d Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx by York Sun · Mon Nov 18 10:29:32 2013 -0800
  42. f062659 Driver/DDR: Moving Freescale DDR driver to a common driver by York Sun · Mon Sep 30 09:22:09 2013 -0700[Renamed (97%) from arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c]
  43. 0b81093 mpc8xxx: set x2 DDR3 refresh rate if SPD config requires it by Valentin Longchamp · Fri Oct 18 11:47:20 2013 +0200
  44. 4a71741 powerpc: Fix CamelCase warnings in DDR related code by Priyanka Jain · Wed Sep 25 10:41:19 2013 +0530
  45. 26681f5 powerpc/mpc8xxx: Fix TIMING_CFG_3[EXT_ACTTOPRE] by James Yang · Mon Jul 22 09:35:26 2013 -0700
  46. 4889c98 powerpc/mpc8xxx: Add x4 DDR device support by York Sun · Tue Jun 25 11:37:47 2013 -0700
  47. c21a739 powerpc/mpc8xxx: Set inactive csn_bnds to 0xffffffff by York Sun · Tue Jun 25 11:37:45 2013 -0700
  48. 972cc40 mpc85xx: Base emulator support by York Sun · Tue Jun 25 11:37:41 2013 -0700
  49. d79de1d Add GPL-2.0+ SPDX-License-Identifier to source files by Wolfgang Denk · Mon Jul 08 09:37:19 2013 +0200
  50. 021b7ae mpc8xxx: fix DDR init value to use CONFIG_MEM_INIT_VALUE by Anatolij Gustschin · Mon Jan 21 23:50:27 2013 +0000
  51. 992562c 8xxx: Change all 8*xx_DDR addresses to 8xxx by Andy Fleming · Tue Oct 23 19:03:46 2012 -0500
  52. 82f576f arch/powerpc/cpu/mpc8xxx/: sparse fixes by Kim Phillips · Mon Oct 29 13:34:37 2012 +0000
  53. 98df4d1 powerpc/mpc8xxx: Fix DDR driver handling quad-rank DIMMs and address calculation by York Sun · Mon Oct 08 07:44:23 2012 +0000
  54. 7d69ea3 powerpc/mpc8xxx: Update DDR registers by York Sun · Mon Oct 08 07:44:22 2012 +0000
  55. cd077cf powerpc/mpc8xxx: Fix bug for extended DDR timing by York Sun · Fri Aug 17 08:22:40 2012 +0000
  56. e8dc17b powerpc/mpc8xxx: Enable 3-way and 4-way DDR interleaving by York Sun · Fri Aug 17 08:22:39 2012 +0000
  57. bad8209 powerpc/mpc8xxx: Add support for cas latency 12 and above by York Sun · Fri Aug 17 08:22:38 2012 +0000
  58. d5bbe66 arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c: Fix GCC 4.6 build warning by Kumar Gala · Wed Nov 09 10:05:10 2011 -0600
  59. e12ce98 powerpc/mpc83xx: Migrate from spd_sdram to unified DDR driver by York Sun · Fri Aug 26 11:32:44 2011 -0700
  60. 15f874a powerpc/mpc8xxx: Fix DDR code for empty first DIMM slot and enable DQS_en by York Sun · Fri Aug 26 11:32:40 2011 -0700
  61. 7a16d64 powerpc/mpc8xxx: Extend CWL table by York Sun · Wed Aug 24 09:40:25 2011 -0700
  62. f8691fc powerpc/mpc8xxx: Allow override DDR read-to-write turnaround time by York Sun · Fri May 27 13:44:28 2011 +0800
  63. 4513d76 powerpc/8xxx: Fix typo for address hashing message by Kumar Gala · Fri Mar 18 11:53:06 2011 -0500
  64. b78c7bf powerpc/8xxx: Replace fsl_ddr_get_mem_data_rate with get_ddr_freq() by Kumar Gala · Mon Jan 31 20:36:02 2011 -0600
  65. 501b70d powerpc/mpc8xxx: disable rcw_en bit for non-DDR3 by York Sun · Thu Mar 17 11:18:12 2011 -0700
  66. 3673f2c powerpc/mpc8xxx: Fix DDR3 timing_cfg_1 and sdram_mode registers by York Sun · Wed Mar 02 14:24:11 2011 -0800
  67. 27f83be powerpc/8xxx: Add additional cycle to write-to-read turnaound for DDR3 by York Sun · Thu Feb 10 10:13:10 2011 -0800
  68. 65b5be2 powerpc/8xxx: Fix compile warning when build for a DDR1 or DDR2 board by Kumar Gala · Thu Jan 20 01:53:15 2011 -0600
  69. ba0c2eb mpc85xx: Enable unique mode registers and dynamic ODT for DDR3 by York Sun · Mon Jan 10 12:03:00 2011 +0000
  70. 80ad401 8xxx/ddr: add support to only compute the ddr sdram size by Haiying Wang · Wed Dec 01 10:35:31 2010 -0500
  71. 2927c5e Disable unused chip-select for DDR controller interleaving by York Sun · Mon Oct 18 13:46:50 2010 -0700
  72. 5207e77 Fix parameters to support RDIMM for P2020DS by York Sun · Fri Aug 27 16:25:56 2010 -0500
  73. 1714e49 powerpc/8xxx: Improvement to DDR parameters by york · Fri Jul 02 22:25:56 2010 +0000
  74. de87932 powerpc/8xxx: Enable DDR3 RDIMM support by york · Fri Jul 02 22:25:55 2010 +0000
  75. 4260372 powerpc/8xxx: Enabled address hashing for 85xx by york · Fri Jul 02 22:25:54 2010 +0000
  76. f4f93c6 powerpc/8xxx: Enable quad-rank DIMMs. by york · Fri Jul 02 22:25:53 2010 +0000
  77. 93799ca powerpc/8xxx: Fix bug in memctrl interleaving & bank interleaving on cs0~cs4 by york · Fri Jul 02 22:25:52 2010 +0000
  78. 8107926 fsl-ddr: Add extra cycle to turnaround times by Dave Liu · Tue Dec 08 11:56:48 2009 +0800
  79. 88fbf93 Move arch/ppc to arch/powerpc by Stefan Roese · Thu Apr 15 16:07:28 2010 +0200[Renamed from arch/ppc/cpu/mpc8xxx/ddr/ctrl_regs.c]
  80. 29514c7 ppc: Move cpu/$CPU to arch/ppc/cpu/$CPU by Peter Tyser · Mon Apr 12 22:28:09 2010 -0500[Renamed from cpu/mpc8xxx/ddr/ctrl_regs.c]
  81. 3525e1a fsl-ddr: Fix the turnaround timing for TIMING_CFG_4 by Dave Liu · Fri Mar 05 12:22:00 2010 +0800
  82. 625b268 fsl-ddr: setup ODT_RD_CFG & ODT_WR_CFG when we interleave by Dave Liu · Wed Dec 16 10:24:39 2009 -0600
  83. 2d0f125 fsl-ddr: add override for the Rtt_Wr by Dave Liu · Wed Dec 16 10:24:38 2009 -0600
  84. 64ee7df fsl-ddr: add the override for write leveling by Dave Liu · Wed Dec 16 10:24:37 2009 -0600
  85. c7d983a fsl-ddr: Fix power-down timing settings by Dave Liu · Wed Dec 16 10:24:36 2009 -0600
  86. 14f2eb1 ppc/8xxx: Misc DDR related fixes by Kumar Gala · Thu Sep 10 14:54:55 2009 -0500
  87. 24aa71a ppc/8xxx: Remove ddr_pd_cntl register since it doesn't exist by Kumar Gala · Tue Sep 01 22:01:54 2009 -0500
  88. 68ef4bd fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BIT by Kumar Gala · Thu Jun 11 23:42:35 2009 -0500
  89. 4be87b2 fsl-ddr: add the DDR3 SPD infrastructure by Dave Liu · Sat Mar 14 12:48:30 2009 +0800
  90. 82aa953 fsl-ddr: Fix two bugs in the ddr infrastructure by Dave Liu · Sat Mar 14 12:48:19 2009 +0800
  91. 2aad0ae fsl-ddr: make the self refresh idle threshold configurable by Dave Liu · Fri Nov 21 16:31:35 2008 +0800
  92. 4758d53 fsl-ddr: clean up the ddr code for DDR3 controller by Dave Liu · Fri Nov 21 16:31:29 2008 +0800
  93. 5c1bb51 fsl-ddr: update the bit mask for DDR3 controller by Dave Liu · Fri Nov 21 16:31:22 2008 +0800
  94. d90e040 Add debug information for DDR controller registers by Haiying Wang · Fri Oct 03 12:37:26 2008 -0400
  95. 272b596 Make DDR interleaving mode work correctly by Haiying Wang · Fri Oct 03 12:36:39 2008 -0400
  96. 35ad58d Fix compiler warning in mpc8xxx ddr code by Kumar Gala · Fri Sep 05 14:40:29 2008 -0500
  97. 124b082 FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. by Kumar Gala · Tue Aug 26 15:01:29 2008 -0500