| commit | e3cef9f5616ee5a427627cf221bb438bafbf6576 | [log] [tgz] |
|---|---|---|
| author | York Sun <york.sun@nxp.com> | Fri Jul 29 09:02:29 2016 -0700 |
| committer | York Sun <york.sun@nxp.com> | Tue Aug 02 09:47:34 2016 -0700 |
| tree | 2c7aa873b2e5068cfc3aeefd2022719dc0e06fff | |
| parent | 704e41587a17ef7435761f2f258ed362eebfb644 [diff] |
driver/ddr/fsl: Fix timing_cfg_2 Commit 5605dc6 tried to fix wr_lat bit in timing_cfg_2, but the change was wrong. wr_lat has 5 bits with MSB at [13] and lower 4 bits at [9:12], in big-endian convention. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Thomas Schaefer <Thomas.Schaefer@kontron.com>